REQUIRED TEXT: M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals, Pearson/Prentice Hall, 3 rd edition, 2004
REFERENCE TEXTS:
- CMOS VLSI Design: A Circuits and Systems Perspective, Weste & Harris, 4th Ed., Addison Wesley
- Switching and Finite Automata Theory, Kohavi & Jha, 3rd Ed., Cambridge University Press
- Logic Synthesis and Verification Algorithms, Hachtel & Somenzi, Springer
- Contemporary Logic Design, Katz & Borriello, 2nd Ed., Pearson/Prentice Hall
COURSE COORDINATOR:
COURSE GOALS: To teach design and synthesis of two-level/multilevel combinational logic as well as finite state machine design, optimization, and synthesis. Material reinforced with the use of contemporary EDA tools. Introduces the use of a hardware-description language (VHDL).
PREREQUISITE: EECS 203
PREREQUISITES BY TOPIC:
1) Number systems
2) Logic simplification using Boolean algebra and Karnaugh maps
3) Combinational logic implementation using AND/OR/NOT, NAND/NOR gates, PLAs
4) Exposure to MSI components, e.g., adders, decoders, and multiplexers.
5) Exposure to memory elements and flip-flops
6) Basic FSM design experience
7) Registers, counters, and other basic sequential devices
DETAILED COURSE TOPICS:
Week 1: Introduction to logic design: class administration, digital design methodology, introduction to Mentor Graphics tools, review of Boolean algebra and two level minimization: logic gates, Boolean algebra review, two level minimization, Karnaugh maps.
Week 2: Two level logic minimization algorithms: Unate covering, Quine McCluskey Method, CAD tools for two level minimization, ESPRESSO algorithm.
Week 3: Combinational logic implementation technologies: programmable logic arrays, MOS transistor logic, multiplexers, decoders, ROMS, field programmable gate arrays (FPGAs). Delays and timing in multilogic logic synthesis: gate delays, timing waveforms, static/dynamic hazards and glitches, designs to avoid hazards.
Week 4: Multilevel logic synthesis: Mapping 2-level logic to NANDs and NORs, CAD tools for multilevel logic, Factoring, Extraction, Simplification. Arithmetic Logic Circuits: review of number systems, Adders, ripple carry, carry lookahead, carry select adders, combinational array multipliers, ALUs, general function units. Binate covering and technology mapping.
Week 5: Memory elements and clocking: Sequential logic networks, latches, flip-flops, timing issues, setup and hold times. Registers and counters: Registers, register files, counters, designs of counters with various flip flops.
Week 6: Memory Design: Random Access Memory (RAMS), Static RAMS, Dynamic RAMS, Memory Organizations, Read Only Memories (ROM).
Week 7: Finite State Machine Design: Review of state machine design, Moore/Mealy machine, finite state machine word problems. Transformation from non-deterministic representations. Finite State Machine Optimization: Motivation for FSM Optimization, state minimization algorithms, implication chart method, CAD tools for optimization.
Week 8: Finite State Machine Assignment: motivation for state assignment, example for state assignment, paper and pencil methods for state assignment, one-hot encodings, EDA tools for state assignment. Finite State Machine Implementations: Mapping FSM to random logic, ROMs, PLAs, and FPGAs.
Week 9: Introduction to VHDL: VHDL language basics, interface, architecture body, behavioral VHDL, process statements, delay models. VHDL Structural Modeling: Review of VHDL, structural VHDL modeling, use of hierarchy, combinational designs, component instantiation, concurrent statements, test benches.
Week 10: VHDL Modeling of Sequential Machines: Describing sequential behavior in VHDL, latches, flip-flops, FSMs, synthesis using VHDL, packages in VHDL. Case Study of VHDL design, overview of design, VHDL behavioral design, VHDL structural design.
COMPUTER USAGE: Students learn to use industrial EDA tools from Mentor Graphics and Synopsys. Specifically, they use the tools, Design Architect for schematic capture, QuickSim-II for gate level logic simulation, ModelSim for VHDL simulation, and Design Compiler for VHDL synthesis. Students use the Unix workstations in the ECE Wilkinson lab. In addition, students also use the SIS synthesis tools.
HOMEWORK ASSIGNMENTS:
Homework 1: Design problems dealing with two level logic minimization using Boolean algebra, Karnaugh Maps, Quine McCluskey method.
Homework 2: Design problems dealing with multilevel logic synthesis, combinational logic implementations using PLAs, multiplexers, CMOS transistors, delays and timing in combinational logic.
Homework 3: Finite state machine design.
Homework 4: Finite state machine word problems. Non-deterministic specifications. Efficient state minimization and assignment.
Homework 5: Comprehensive course review homework assignment.
LABORATORY PROJECTS:
Lab 1: Introduction to the use of the Mentor Graphics tools. Use of Design Architect schematic entry system, the QuickSim-II logic simulator.
Lab 2: Use of ESPRESSO for two-level minimization.
Lab 3: Use of MIS for multi-level minimization.
Lab 4: Use MIS and Mentor Graphics tools to design and simulate a finite state machine capable of repairing a damaged video controller circuit.
Lab 5: Use Mentor Graphics ModelSim and Synopsys Design Compiler for finite state machine simulation and synthesis.
GRADES:
- Homework assignments - 25%
- Lab assignments - 25%
- Midterm exam - 20%
- Final exam - 30%
COURSE OBJECTIVES: Students completing this course should be able to
1) Do two-level logic minimization using Boolean algebra, Karnaugh maps, the Quine McCluskey method, and the Espresso software;
2) Do multi-level logic simplification using factoring and the MIS software;
3) Understand and use advanced technology mapping algorithms;
4) Understand advanced two-level minimization heuristics;
5) Design using a variety of implementation technologies, e.g., PLAs, multiplexors, CMOS transistors, and field-programmable gate arrays;
5) Draw and interpret timing diagrams;
6) Identify and accelerate a circuit's critical timing path;
7) Design static and dynamic hazard free logic;
8) Do efficient FSM state minimization, assignment, and splitting;
9) Design various arithmetic, logic, and memory components, e.g., ALUs, shifters, decoders, multiplexers, RAMs, and ROMs;
10) Design combinational and sequential circuits using VHDL;
11) Use a research-quality EDA software to perform two-level combinational logic minimization, multilevel combinational synthesis, state minimization, and state assignment of sequential logic; and
12) Use industrial EDA tools for schematic capture, gate-level logic simulation as well as HDL simulation and synthesis.
