CATALOG DESCRIPTION: I ssues that arise in the design and analysis of VLSI circuits at high speeds such as buffer sizing, repeater insertion, noise, electromigration, Elmore delay, scaling trends, and power consumption.

REQUIRED TEXTS: None.

REFERENCE TEXTS: Papers distributed in class.

COURSE COORDINATOR: Yehea Ismail

COURSE GOALS: To discuss issues that arise in the design and analysis of VLSI circuits at high speeds. The course also aims to help students acquire the basic skills for graduate study such as collecting technical materials, reading and writing papers, and presentation skills.

PREREQUISITES: EECS 391 or equivalent

DETAILED COURSE TOPICS:

  • Review of basic concepts in CMOS circuits
  • Technology scaling trends in CMOS circuits
  • Dynamic, short-circuit, and leakage power consumption of CMOS circuits
  • Cascaded buffer design for driving large capacitive loads and repeater insertion within RC interconnect
  • Design and analysis of integrated circuits including the inductance of the interconnect
  • Characterizing the delay and power consumption of CMOS gates driving C , RC, and RLC loads.
  • Approximate temporal information in RC and RLC trees (Elmore, Wyatt, Penfield-Rubinstein delay models, and equivalent Elmore delay for RLC trees)
  • Accurate temporal information in RC and RLC trees (model order reduction techniques such as AWE and DTT)
  • Power distribution network design, electromigration, Ldi/dt noise, and RI drops
  • Coupling and simultaneous switching noise
  • High-speed clock distribution network design: Retiming, register allocation, skew control, and clock scheduling.

PROJECTS:

Each student is required to select a topic for which s/he finds related technical papers and information, gives a presentation in front of the class about the selected topic, and writes a paper that summarizes the research area. A list of topics to choose from will be given at the beginning of the class. Also, students are allowed to suggest their own topics if enough interest in these topics exist.

GRADES:

  • Topic presentation: 20%
  • Summary paper: 20%
  • Class attendance and contribution: 10%
  • Midterm Exam: 15%
  • Final Exam: 20%
  • Homeworks: 15%

COURSE OUTCOMES: When a student completes this course, s/he should be able to:

  • Understand the issues that arise in integrated circuits at high speeds.
  • Identify and deal with the state of art problems in VLSI.
  • Improve his/her presentation style.
  • Read and write technical papers.
  • Pursue research and development in the area of high-speed integrated circuits either in academia or in industry.

ABET CONTENT CATEGORY: 100% Engineering.