CATALOG DESCRIPTION: Introduction to advanced topics in synthesis and modeling of complex VLSI systems at behavioral and logic level. Topics include resource allocation, resource binding, scheduling, and controller design in high level synthesis, C to hardware compilation flows, logic synthesis, survey of stat-of-the-art in high level and system level design methods and tools.

COURSE COORDINATOR: Prof. Seda Ogrenci Memik

COURSE OBJECTIVES: After a student completes this course he or she should be able to:

  • Model computation in form of networks and task graphs.
  • Conceptually construct an end-to-end synthesis flow with judicious choices on the allocation, binding, and scheduling algorithms for a given optimization objective and set of constraints.
  • Cite one seminal and one recent academic work of last 3-5 years in high level synthesis methods and tools for allocation, binding, and scheduling and describe their relevance.
  • Cite one current commercial product in use for C to hardware conversion.

PREREQUISITES: Senior or graduate standing in EECS majors.

RECOMMENDED PREPARATION: EECS 303, EECS 361, EECS 336.

REQUIRED TEXT: None

RECOMMENED READING MATERIALS: Synthesis and Optimization of Digital Circuits, G. De Micheli.

GRADES: Grades will be based on Homework Assignments, Literature Surveys & Presentations