EECS Main
>
Events
Event Details
|
Meet the Faculty: Gokhan Memik4:00 p.m. April 11, 2008 Tech L324
Gokhan Memik, Assistant Professor, EECS Department "Learning and Leveraging the Relationship between Architectural Properties and User Satisfaction" | Processors will continue to rely on technology scaling (i.e., smaller manufacturing technologies) to meet aggressive performance targets. Although technology scaling has been in the core of advances in processor performance in the previous decades, further scaling introduces several important challenges: power densities are increasing rapidly, processor reliability is diminishing, and yield levels are going down drastically. In this talk, I will overview some projects aiming to minimize these effects.
The first part of the talk focuses on a recent project aimed at understanding the user satisfaction with architectural decisions. Specifically, we have investigated the relationship between microarchitectural parameters and user satisfaction: we analyzed the relationship between hardware performance counter (HPC) readings and individual satisfaction levels reported by users for several interactive applications. Our results show that the satisfaction of the user is strongly correlated to the performance of the underlying hardware and more importantly, that user satisfaction is highly user-dependent. To take advantage of these observations, we developed a framework called Individualized Dynamic Voltage and Frequency Scaling (iDVFS). A set of user studies demonstrates that iDVFS reduces the CPU power consumption by over 25% in representative applications as compared to the Windows DVFS algorithm.
In the second part of the talk, I will highlight various other ongoing projects. First, we have developed variable access latency caches that can be used to increase the performance under large variations in circuit properties (i.e., process and thermal variations). I will then describe how architectures can be designed to minimize the yield losses and highlight possible effects of such architectural schemes on the profits obtained from a set of chips. Then, I will present the clumsy processors and finalize the talk with a short discussion of thermal-aware architectures. |
|