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Monday, March 17, 2014, 11:00am


Mieszko Lis 2Mieszko Lis

Graduate Student, MIT

"The Execution Migration Machine: Hardware-Level Thread Migration in a 110-Core Shared-Memory Multiprocessor"

Abstract: Chip multiprocessors with hundreds of cores are becoming a reality as technology nodes continue shrinking: it is now possible to combine hundreds of processor cores in a single chip. Building such massive-scale processors, however, brings new challenges. All those cores must be fed data to stay busy, and have to communicate with other cores over dramatically larger distances. These challenges, we believe, call for bold architectural innovations.
In this talk, we describe one such innovation: hardware-level thread migration. An enabling technology that accelerates intercore thread movement by several orders of magnitude, hardware-level migration has allowed us to design a novel shared memory scheme that can perform comparably to traditional directory-based coherence. Our proof-of-concept implementation of this technique in a 110-core shared-memory processor ASIC is the largest multicore to date in terms of core count.

Bio: Mieszko Lis is a Ph.D. candidate at the Massachusetts Institute of Technology, where he focuses on massive-scale multicore processors and various architectural techniques required to build them. He is committed to raising the level of abstraction across the computing landscape -- an interest he has also explored as co-designer of the high-level hardware design language Bluespec and designer of a high-level language for immunology research.
Before coming to MIT for his doctoral studies, Mieszko accumulated extensive industry experience as a co-founder of two start-up companies.

Hosted by: EECS Professor Seda Ogrenci-Memik

Location Tech Room L324
Monday, March 17, 2014 at 11:00am
Contact Amanda Zarate at or 847-491-3451

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