Latest EECS News
- M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals, Pearson/Prentice Hall, latest Edition
- Logic Synthesis and Verification Algorithms, Hachtel & Somenzi, Springer
- CMOS VLSI Design: A Circuits and Systems Perspective, Weste & Harris, 4th Ed., Addison Wesley
COURSE COORDINATOR: Prof. Seda Ogrenci Memik
COURSE GOALS: To teach design and synthesis of two-level/multilevel combinational logic as well as finite state machine design, optimization, and synthesis. Material reinforced with the use of contemporary EDA tools. Introduces the use of a hardware-description language (VHDguL).
PREREQUISITE: EECS 203
PREREQUISITES BY TOPIC:
- 1) Number systems
- 2) Logic simplification using Boolean algebra and Karnaugh maps
- 3) Combinational logic implementation using AND/OR/NOT, NAND/NOR gates, PLAs
- 4) Exposure to basic components, e.g., adders, decoders, and multiplexers.
- 5) Exposure to memory elements and flip-flops
- 6) Basic FSM design experience
DETAILED COURSE TOPICS:
Week 1: Introduction to logic design: class administration, digital design methodology, review of two level minimization, Karnaugh maps.
Week 2: Two level logic minimization algorithms: Unate covering, Quine McCluskey Method,
Week 3: CAD tools for two level minimization, ESPRESSO algorithm.
Week 4: Multilevel logic synthesis: Mapping 2-level logic to NANDs and NORs, CAD tools for multilevel logic, Factoring, Extraction, Simplification.
Week 5: Technology Mapping, Binate covering.
Week 6: Memory elements and clocking: Sequential logic networks, latches, flip-flops, timing issues, setup and hold times. Timing Analysis for Sequential and Combinational Logic.
Week 7: Finite State Machine Design: Review of state machine design, Moore/Mealy machine, finite state machine word problems. Motivation for FSM Optimization, state minimization algorithms, implication chart method. Finite State Machine Assignment: motivation for state assignment, example for state assignment, paper and pencil methods for state assignment, one-hot encodings.
Week 8: Programmable Logic Technologies.
Week 9: Introduction to VHDL: VHDL language basics, interface, architecture body, behavioral VHDL, process statements, delay models.
Week 10: VHDL Structural Modeling: Review of VHDL, structural VHDL modeling, use of hierarchy, combinational designs, component instantiation, concurrent statements, test benches.
COMPUTER USAGE: Students learn to use industrial EDA tools such as Altera Quartus, ModelSim for VHDL simulation. In addition, students also use the SIS synthesis tools. Students use the Unix workstations in the ECE Wilkinson lab as well as Web Edition software on their own PCs.
Lab 1: Use of ESPRESSO for two-level minimization.
Lab 2: Quartus and ModelSim for VHDL simulation and synthesis.
- Homework & Lab assignments - 45%
- Midterm exam - 25%
- Final exam - 30%
COURSE OBJECTIVES: Students completing this course should be able to
1) Do two-level logic minimization using Boolean algebra, Karnaugh maps, the Quine McCluskey method, and the Espresso software;
2) Do multi-level logic simplification using factoring;
3) Understand and use advanced technology mapping algorithms;
4) Understand advanced two-level minimization heuristics;
5) Draw and interpret timing diagrams;
6) Identify and accelerate a circuit's critical timing path;
7) Do efficient FSM state minimization, assignment, and splitting;
8) Design combinational circuits using VHDL;
9) Use a research-quality EDA software to perform two-level combinational logic minimization; and
10) Use industrial EDA tools for schematic capture, gate-level logic simulation as well as HDL simulation and synthesis.
1. M. Morris Mano and Charles R. Kime, Logic and Computer Design Fundamentals, Pearson/Prentice Hall, latest Edition. 2. Logic Synthesis and Verification Algorithms, Hachtel & Somenzi, Springer 3. CMOS VLSI Design: A Circuits and Systems Perspective, Weste & Harris, 4th Ed., Addison Wesley