entity string_checker is
  port (X, clock: in bit; Z1, Z2: out bit);
end string_checker;

architecture diagram of string_checker is
  -- decleration of type and variable
  type state is (S0, S1, S2, S3, S4, S5, S6, S7);
begin
  process
    variable current: state := S0;
  begin
  -- Please fill in your design

  end process;
end diagram;

architecture gate_and_FF of string_checker is
  -- decleration of signals
  signal QA, QB, QC: bit := '0';
begin
  -- Please fill in your design

end gate_and_FF;

entity test_bench is
end test_bench;

architecture test1 of test_bench is
  signal clk, input, diagram_Z1, diagram_Z2, gate_Z1, gate_Z2: bit := '0';
  component string_checker
    port (X, clock: in bit; Z1, Z2: out bit);
  end component;
  for U1: string_checker use entity work.string_checker(diagram);
  for U2: string_checker use entity work.string_checker(gate_and_FF);
begin
  U1: string_checker port map (input, clk, diagram_Z1, diagram_Z2);
  U2: string_checker port map (input, clk, gate_Z1, gate_Z2);

  clock_tic: process
  begin
    loop
      clk <= '1';
      wait for 5 ns;
      clk <= '0';
      wait for 5 ns;
    end loop;
  end process;

  input_changes: process
  begin
    input <= 	'1' after 0 ns,
		'1' after 10 ns,
		'1' after 20 ns,
		'0' after 30 ns,
		'0' after 40 ns,
		'1' after 50 ns,
		'0' after 60 ns,
		'1' after 70 ns,
		'0' after 80 ns,
		'0' after 90 ns,
		'0' after 100 ns,
		'1' after 110 ns,
		'1' after 120 ns,
		'0' after 130 ns,
		'1' after 140 ns,
		'0' after 150 ns,
		'1' after 160 ns,
		'1' after 170 ns;
    wait;
  end process;
end test1;