Publications of NuCAD Group

Many of the papers have been made available as a courtesy. Please be aware that almost all of them are copyrighted by the organizations responsible for the corresponding conferences or journals.

Dissertations and book chapters

• H. Zhou, Signal Integrity and Low Power Issues in Deep Sub-Micron VLSI Design. Ph.D. Dissertation, University of Texas at Austin, May 1999.
• C. Lin, Timing Optimization Algorithms for Sequential Circuits. Ph.D. Dissertation, Northwestern University, June 2006.
• D. Sinha, Analysis and Optimization under Crosstalk and Variability in Deep Sub-Micron VLSI Circuits. Ph.D. Dissertation, Northwestern University, June 2006.
• R. Chen, Timing Analysis and Optimization Techniques for VLSI Circuits. Ph.D. Dissertation, Northwestern University, December 2007.
• J. Wang, System-Level Optimizations for High Performance DSM Circuits. Ph.D. Dissertation, Northwestern University, June 2008. (EECS Best Dissertation Award)
• H.-M. Chen, D.F. Wong, H. Zhou, F.Y. Young, H.H. Yang, and N. Sherwani, Integrated Floorplanning and Interconnect Planning. Layout Optimizations in VLSI Designs, D.-Z. Du, S. Sapatnekar, and B. Lu eds., Kluwer Academic Publishers. Boston, MA, 2001.
• D. Mehta and H. Zhou, Basic Data Structures, in Handbook of Algorithms for Physical Design Automation, C. Alpert, D. Mehta, and S. Sapatnekar eds., CRC Press. 2007.
• H. Zhou, Rectilinear Spanning Tree (2002; Zhou, Shenoy, Nicholls), in Encyclopedia of Algorithms, M.-Y. Kao eds., Springer. 2008.
• H. Zhou, Circuit Retiming (1991; Leiserson and Saxe). in Encyclopedia of Algorithms, M.-Y. Kao eds., Springer. 2008.
• H. Zhou, Rectilinear Steiner Tree (2004; Zhou). in Encyclopedia of Algorithms, M.-Y. Kao eds., Springer. 2008.
• H. Zhou, Circuit Retiming: An Incremental Approach (2005; Zhou). in Encyclopedia of Algorithms, M.-Y. Kao eds., Springer. 2008.

  Journal articles

• H. Zhou and D.F. Wong, Optimal River Routing with Crosstalk Constraints. ACM Transactions on Design Automation of Electronic Systems, 3(3), pp. 496-514, July 1998.
• H. Zhou and D. F. Wong, Global Routing with Crosstalk Constraints. IEEE Transactions on Computer-Aided Design, 18(11), pp. 1683-1688, Nov. 1999.
• H. Zhou, D. F. Wong, I-M. Liu, and A. Aziz, Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. IEEE Transactions on Computer-Aided Design, 19(7), pp. 819-824, July 2000.
• H. Zhou and A. Aziz, Buffer Minimization in Pass Transistor Logic. IEEE Transactions on Computer-Aided Design, 20(5), pp. 693-697, May 2001.
• H. Zhou, N. Shenoy, and W. Nicholls, Efficient Minimum Spanning Tree Construction without Delaunay Triangulation. Information Processing Letters, 81(5), pp. 271-276, 2002.
• A. Goel, K. Sajid, H. Zhou, A. Aziz, and V. Singhal, BDD-based Procedures for a Theory of Equality with Uninterpreted Functions. Formal Methods in System Design, 22(3), pp. 205-224, May 2003.
• H. Zhou, Timing Analysis with Crosstalk is a Fixpoint on a Complete Lattice. IEEE Transactions on Computer-Aided Design. 22(9), pp. 1261-1269, Sept. 2003. (IEEE Donald O. Pederson award finalist)
• H. Zhou, Efficient Steiner Tree Construction Based on Spanning Graphs. IEEE Transactions on Computer-Aided Design. 23(5), pp. 704-710, May 2004.
• H. Zhou and C. Lin, Retiming for Wire Pipelining in System-On-Chip. IEEE Transactions on Computer-Aided Design, 23(9), pp. 1338-1345, Sept. 2004.
• Q. Zhu, H. Zhou, T. Jing, X. Hong, and Y. Yang, Spanning Graph Based Non-Rectilinear Steiner Tree Algorithms. IEEE Transactions on Computer-Aided Design, 24(7), pp. 1066-1075, July 2005.
• C. Lin and H. Zhou, Wire Retiming as Fixpoint Computation. IEEE Transactions on VLSI, 13(12), pp. 1340-1348, Dec. 2005.
• D. Sinha and H. Zhou, Gate-Size Optimization under Timing Constraints for Coupling-Noise Reduction. IEEE Transactions on Computer-Aided Design, 25(6), pp. 1064-1074, Jun. 2006.
• R. Chen and H. Zhou, Statistical Timing Verification for Transparently Latched Circuits. IEEE Transactions on Computer-Aided Design, 25(9), pp. 1847-1855, Sep. 2006.
• C. Lin and H. Zhou, Optimal Wire Retiming Without Binary Search. IEEE Transactions on Computer-Aided Design, 25(9), pp. 1577-1588, Sep. 2006.
• D. Sinha, N. Shenoy, and H. Zhou, Statistical Timing Yield Optimization by Gate Sizing. IEEE Transactions on VLSI Systems, 14(10), pp. 1140-1146, Oct. 2006.
• C. Lin, J. Wang, and H. Zhou, Clustering for Processing Rate Optimization. IEEE Transactions on VLSI Systems, 14(11), pp. 1264-1275, Nov. 2006.
• R. Chen and H. Zhou, An Efficient Data Structure for Max-Plus Merge in Dynamic Programming. IEEE Transactions on Computer-Aided Design, 25(12), pp. 3004-3009, Dec. 2006.
• D. Sinha and H. Zhou, Statistical timing analysis with coupling. IEEE Transactions on Computer-Aided-Design, 25(12), pp. 2965-2975, Dec. 2006.
• A. Mallik, D. Sinha, P. Banerjee, and H. Zhou, Low Power Optimization by Smart Bit-Width Allocation in a SystemC Based ASIC Design Environment. IEEE Transactions on Computer-Aided Design, 26(3), pp. 447-455, March 2007.
• C. Lin and H. Zhou. Trade-off Between Latch and Flop for Min-Period Sequential Circuit Designs with Crosstalk. IEEE Transactions on Computer-Aided Design, 26(7), pp. 1222-1232, July 2007.
• J. Wang and H. Zhou. Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. IEEE Transactions on Computer-Aided Design, 26(8), pp. 1445-1453, August 2007.
• D. Sinha, H. Zhou, and N. Shenoy. Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Transactions on Computer-Aided Design, 26(8), pp. 1522-1533, August 2007.
• Z. Gu, J. Wang, R. P. Dick, and H. Zhou. Unified Incremental Physical-Level and High-Level Synthesis. IEEE Transactions on Computer-Aided Design, 26(9), pp. 1576-1588, September 2007.
• R. Chen and H. Zhou. An Efficient Algorithm for Buffer Insertion in General Circuits Based on Network Flow. IEEE Tranactions on Computer-Aided Design, 26(11), pp. 2069-2073, November 2007.
• H. Zhou. A New Efficient Retiming Algorithm Derived by Formal Manipulation. ACM Transactions on Design Automation of Eletronic Systems, 13(1), January 2008.
• C.-W. Sham, F. Y. Young, and H. Zhou. Optimizing wirelength and routability by searching alternative packings in floorplanning. ACM Tranactions Design Automation of Electronic Systems, 13(1), January 2008.
• R. Chen and H. Zhou. Fast Estimation of Timing Yield Bounds for Process Variations. IEEE Transactions on VLSI Systems, 16(3), March 2008.
• J. Long, H. Zhou, and S. Ogrenci Memik. EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm. IEEE Transactions on Computer-Aided Design, 27(12), pp. 2169-2182, December 2008.
• D. Khalil, D. Sinha, H. Zhou, and Y. Ismail. A Timing-Dependent Power Estimation Framework Considering Coupling. IEEE Transactions on VLSI Systems, 17(6), pp. 843-847, June 2009.
• J. Wang, D. Das, and H. Zhou. Gate Sizing by Lagrangian Relaxation Revisited. IEEE Transactions on Computer-Aided Design, 28(7), pp. 1071-1084, July 2009.
• D. Das, K. Killpack, C. Kashyap, A. Jas, and H. Zhou. Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering. IEEE Transactions on Computer-Aided Design. Accepted for Publication, 2009.
• D. Das, A. Shebaita, H. Zhou, Y. Ismail, and K. Killpack. FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis. IEEE Transactions on VLSI Systems. Accepted for Publication, 2009

Refereed conference papers

• H. Zhou and D.F. Wong, An Optimal Algorithm for River Routing with Crosstalk Constraints. IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, 1996.
• C.-P. Chen, H. Zhou, and D.F. Wong, Optimal Non-Uniform Wire-Sizing under the Elmore Delay Model. IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, 1996.
• H. Zhou and D.F. Wong, Crosstalk Constrained Maze Routing Based on Lagrangian Relaxation. IEEE International Conference on Computer Design, Austin, TX, 1997.
• H. Zhou and D.F. Wong, An Exact Gate Decomposition Algorithm for Low-Power Technology Mapping. IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, 1997.
• H. Zhou and D.F. Wong, Global Routing with Crosstalk Constraints. ACM/IEEE Design Automation Conference, San Francisco, CA, 1998.
• A. Goel, K. Sajid, H. Zhou, A. Aziz, and V. Singhal, BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. International Conference on Computer Aided Verification: CAV '98.
• H. Zhou, D.F. Wong, I-Min Liu, and A. Aziz, Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. ACM/IEEE Design Automation Conference, New Orleans, LA, 1999.
• I-M. Liu, A. Aziz, D. F. Wong, and H. Zhou, An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. IEEE International Conference on Computer Design, Austin, TX, 1999.
• H.-M. Chen, H. Zhou, F. Y. Young, D. F. Wong, H. H. Yang, and N. Sherwani, Integrated Floorplanning and Interconnect Planning. IEEE International Conference on Computer Aided Design, San Jose, CA, 1999.
• H. Zhou and A. Aziz, Buffer Minimization in Pass Transistor Logic. ACM International Symposium on Physical Design, San Diego, CA, 2000.
• H. Zhou and D.F. Wong, Optimal Low Power XOR Gate Decomposition. ACM/IEEE Design Automation Conference, Los Angeles, CA, 2000.
• H. Zhou, N. Shenoy, and W. Nicholls, Efficient Minimum Spanning Tree Construction without Delaunay Triangulation. Asia and South Pacific Design Automation Conference, Yokohama, Janan, 2001.
• H. Zhou, N. Shenoy, and W. Nicholls, Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. ACM/IEEE Design Automation Conference, Las Vegas, NV, 2001.
• S. H. Batterywala, N. Shenoy, W. Nicholls, and H. Zhou, Track Assignment: A Desirable Intermediate Step Between Global Routing and Detailed Routing. IEEE International Conference on Computer Aided Design, San Jose, CA, 2002.
• C. W. Sham, F. Y. Young, and H. Zhou, Interconnect-Driven Floorplanning by Searching Alternative Packings. Asia and South Pacific Design Automation Conference, Kitakyushu, Japan, 2003.
• H. Zhou, Timing Verification with Crosstalk for Transparently Latched Circuits. DATE '03: Design Automation & Test in Europe, Munich, Germany, 2003.
• H. Zhou, Efficient Steiner Tree Construction Based on Spanning Graphs. ACM International Symposium on Physical Design, Monterey, CA, 2003.
• C. Lin and H. Zhou, Retiming for Wire Pipelining in System-On-Chip. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2003. (Best paper award nominee)
• Q. Zhu, H. Zhou, T. Jing, X. Hong, and Y. Yang, Efficient Octilinear Steiner Tree Construction Based on Spanning Graphs. Asia and South Pacific Design Automation Conference, Yokohama, Japan, 2004.
• C. Lin and H. Zhou, Wire Retiming for System-On-Chip by Fixpoint Computation. DATE '04: Design Automation & Test in Europe, Paris, France, 2004.
• D. Sinha, H. Zhou, and C.C.N. Chu, Optimal Gate Sizing for Coupling-Noise Reduction. ACM International Symposium on Physical Design, Phoenix, AZ, 2004.
• J. Wang and H. Zhou, Minimal Period Retiming under Process Variations. ACM Great Lakes Symposium on VLSI, Boston, MA, 2004.
• R. Chen and H. Zhou, A Flexible Data Structure for Efficient Buffer Insertion. IEEE International Conference on Computer Design, San Jose, CA, 2004.
• H. Zhou and J. Wang, ACG--Adjacent Constraint Graph for General Floorplans. IEEE International Conference on Computer Design, San Jose, CA, 2004.
• R. Chen and H. Zhou, Clock Schedule Verification Under Process Variations. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2004.
• R. Chen and H. Zhou, Timing Macromodeling of IP Blocks with Crosstalk. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2004.
• C. Lin and H. Zhou, Optimal Wire Retiming Without Binary Search. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2004.
• D. Sinha and H. Zhou, Gate Sizing for Crosstalk Reduction under Timing Constraints by Lagrangian Relaxation. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2004.
• D. Sinha and H. Zhou, Yield Driven Gate Sizing for Coupling-Noise Reduction under Uncertainty. Asia and South Pacific Design Automation Conference, Shanghai, China, 2005.
• J. Wang and H. Zhou, Interconnect Estimation Without Packing via ACG Floorplans. Asia and South Pacific Design Automation Conference, Shanghai, China, 2005.
• H. Zhou, Deriving a New Efficient Algorithm for Min-Period Retiming. Asia and South Pacific Design Automation Conference, Shanghai, China, 2005.
• M. Pan, C. C.-N. Chu and H. Zhou, Timing Yield Estimation Using Statistical Static Timing Analysis. IEEE International Symposium on Circuits and Systems, Kobe, Japan, 2005.
• X. Tang, H. Zhou, and P. Banerjee, Leakage Power Optimization with Dual-Vth Library in High-Level Synthesis. ACM/IEEE Design Automation Conference, Anaheim, CA, 2005.
• Z. Gu, J. Wang, R. P. Dick, and H. Zhou, Incremental Exploration of the Combined Physical and Behavioral Design Space. ACM/IEEE Design Automation Conference, Anaheim, CA, 2005.
• R. Chen and H. Zhou, Efficient Algorithms for Buffer Insertion in General Circuits Based on Network Flow. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2005.
• C. Lin, J. Wang, and H. Zhou, Clustering for Processing Rate Optimization. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2005.
• C. Lin and H. Zhou, Trade-off Between Latch and Flop for Min-Period Sequential Circuit Designs with Crosstalk. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2005.
• D. Sinha, N. Shenoy, and H. Zhou, Statistical Gate Sizing for Timing Yield Optimization. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2005.
• D. Sinha and H Zhou, A Unified Framework for Statistical Timing Analysis with Coupling and Multiple Input Switching. IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, 2005.
• N. Liveris, H. Zhou, and P. Banerjee, An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. IEEE Asian Test Symposium (ATS '05), Kolkata, India, 2005.
• A. Mallik, D. Sinha, P. Banerjee, and H. Zhou, Smart Bit-Width Allocation for Low Power Optimization in a SystemC Based ASIC Design Environment. DATE '06: Design Automation and Test in Europe, Munich, Germany, 2006.
• D. Sinha, H. Zhou, and N. Shenoy, Advances in Computation of the Maximum of a Set of Random Variables. International Symposium on Quality Electronic Design (ISQED), San Jose, CA, 2006.
• J. Wang, P. Wu, and H. Zhou, Processing Rate Optimization by Sequential System Floorplanning. International Symposium on Quality Electronic Design (ISQED), San Jose, CA, 2006.
• C. Lin and H. Zhou, An Efficient Retiming Algorithm Under Setup and Hold Constraints. ACM/IEEE Design Automation Conference, San Francisco, CA, 2006.
• J. Wang and H. Zhou, Optimal Jumper Insertion for Antenna Avoidance under Ratio Upper-Bound. ACM/IEEE Design Automation Conference, San Francisco, CA, 2006.
• D. Das, A. Shebaita, H. Zhou, Y. Ismail, and K. Killpack. FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. IEEE International Conference on Computer Design, San Jose, CA, 2006.
• D. Sinha, D. Khalil, Y. Ismail, and H. Zhou, A Timing Dependent Power Estimation Framework Considering Coupling. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2006.
• C. Lin, H. Zhou, and C. Chu, A Revisit to Floorplan Optimization by Lagrangian Relaxation. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2006. (Best paper award nominee)
• S. Ozdemir, D. Sinha, G. Memik, J. Adams, H. Zhou. Yield-Aware Cache Architectures. MICRO-39: IEEE/ACM International Symposium on Microarchitecture, Orlando, FL, 2006.
• R. Chen and H. Zhou. Fast Buffer Insertion for Yield Optimization Under Process Variations. ACM Asia South-Pacific Design Automation Conference, Yokohama, Japan, 2007.
• R. Chen and H. Zhou. New Block-based Statistical Timing Analysis Approaches without Moment Matching. ACM Asia South-Pacific Design Automation Conference, Yokohama, Japan, 2007.
• N. Liveris, C. Lin, J. Wang, H. Zhou, and P. Banerjee. Retiming for Synchronous Data Flow Graphs. ACM Asia South-Pacific Design Automation Conference, Yokohama, Japan, 2007.
• C. Lin and H. Zhou. Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains. ACM Asia South-Pacific Design Automation Conference, Yokohama, Japan, 2007.
• D. Sinha, J. Luo, S. Rajagopalan, S. Batterywala, N. Shenoy and H. Zhou. Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. International Conference on VLSI Design and Embedded Systems, Bangalore, India, 2007.
• D. Das, A. Shebaita, Y. Ismail, H. Zhou, and K. Killpack. Nostra-XTalk: a Predictive Framework for Accurate Static Timing Analysis in UDSM VLSI Circuits. ACM Great Lakes Symposium on VLSI, Stresa, Italy, 2007.
• J. Wang, M.-Y. Kao, and H. Zhou. Address Generation for Nanowire Decoders. ACM Great Lakes Symposium on VLSI, Stresa, Italy, 2007.
• C. Lin, A. Xie, and H. Zhou. Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow. DATE'07: Design, Automation, and Test in Europe, Nice, France, 2007.
• R. Chen and H. Zhou. Fast Min-Cost Buffer Insertion Under Process Variations. ACM/IEEE Design Automation Conference, San Diego, CA, 2007.
• J. Wang, D. Das, and H. Zhou. Gate Sizing by Lagrangian Relaxation Revisited. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2007.
• P. Zhou, Y. Ma, Z. Li, R. Dick, L. Shang, H. Zhou, X. Hong, and Q. Zhou. 3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-Dimentional Integrated Circuits. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2007.
• R. Chen and H. Zhou. Timing Budgeting Under Arbitrary Process Variations. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2007.
• N. Liveris, H. Zhou, and P. Banerjee. A Dynamic-Programming Algorithm for Reducing the Energy Consumption of Pipelined System-Level Streaming Applications. ACM Asia and South Pacific Design Automation Conference, Seoul, Korea, 2008.
• D. Das, K. Killpack, C. Kashyap, A. Jas, and H. Zhou. Pessimism Reduction in Coupling Aware Static Timing Analysis Using Timing and Logic Filtering. ACM Asia and South Pacific Design Automation Conference, Seoul, Korea, 2008. (Best paper award nominee)
• J. Long, H. Zhou, and S. Ogrenci Memik. An O(nlogn) Edge-Based Algorithm for Obstacle-Avoiding Rectilinear Steiner Tree Construction. ACM International Symposium on Physical Design, Portland, OR, 2008.
• J. Wang and H. Zhou. An Efficient Incremental Algorithm for Min-Area Retiming. ACM/IEEE Design Automation Conference, Anaheim, CA, 2008.
• N. Liveris, H. Zhou, R. Dick, and P. Banerjee. State Space Abstraction for Parameterized Self-Stabilizing Embedded Systems. International Conference on Embedded Software (EMSOFT), Atlanta, GA, 2008.
• J. Wang and H. Zhou. Linear Constraint Graph for Floorplan Optimization with Soft Blocks. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2008.
• J. Wang and H. Zhou. Exploring Adjacency in Floorplanning. ACM Asia South-Pacific Design Automation Conference, Yokohama, Japan, 2009.
• J. Wang and H. Zhou. Risk Aversion Min-Period Retiming under Process Variations. ACM Asia South-Pacific Design Automation Conference, Yokohama, Japan, 2009.
• N. Liveris, H. Zhou, and P. Banerjee. Complete-k-Distinguishability for Retiming and Resynthesis Equivalence Checking without Restricting Synthesis. ACM Asia South-Pacific Design Automation Conference, Yokohama, Japan, 2009.
• D. Das, W. Scott, S. Nazarian, H. Zhou. An Efficient Current-Based Logic Cell Model for Crosstalk Delay Analysis. International Symposium on Quality of Electronic Designs (ISQED), San Jose, CA, 2009.
• C. Feng, H. Zhou, C. Yan, J. Tao, and X. Zeng. Provably Good and Practically Efficient Algorithms for CMP Dummy Fill. ACM/IEEE Design Automation Conference, San Francisco, CA, 2009. (Best paper award nominee)
• Y. Lu, L. Shang, H. Zhou, H. Zhu, F. Yang, and X. Zeng. Statistical Reliability Analysis Under Process Variation and Aging Effects. ACM/IEEE Design Automation Conference, San Francisco, CA, 2009.
• Y. Lu, H. Zhou, L. Shang, and X. Zeng. Multicore Parallel Min-Cost Flow Algorithm for CAD Applications. ACM/IEEE Design Automation Conference, San Francisco, CA, 2009.
• Y. Zhao, S. Vemuri, J. Chen, Y. Chen, H. Zhou, and Z. Fu. Exception Triggered DoS Attacks on Wireless Networks. IEEE/IFIP International Conference on Dependable Systems and Networks (DSN-DCCS), 2009.
• M. Gong, H. Zhou, J. Tao, and X. Zeng. Binning Optimization Based on SSTA for Transparently-Latched Circuits. IEEE/ACM International Conference on Computer-Aided Design, San Jose, CA, 2009
• H. Zhou. Retiming and Resynthesis With Sweep Are Complete for Sequential Transformations. Formal Methods in Computer Aided Design (FMCAD), Austin, TX, 2009.

Refereed Workshop Papers

• H. Zhou, V. Singhal, and A. Aziz, How Powerful is Retiming? International Workshop on Logic Synthesis, Lake Tahoe, CA, 1998.
• I.-M. Liu, T.-H. Liu, H. Zhou, and A. Aziz, Simultaneous PTL Buffer Insertion and Sizing for Minimizing Elmore Delay. International Workshop on Logic Synthesis, Lake Tahoe, CA, 1998.
• H. Zhou, Clock Schedule Verification with Crosstalk. TAU 2002: ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems. Monterey, CA, 2002.
• H. Zhou, A New Efficient Retiming Algorithm Derived by Formal Manipulation. International Workshop on Logic Synthesis, Temecula, CA, 2004.
• C. Lin and H. Zhou, An Efficient Retiming Algorithm Under Setup and Hold Constraints. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, San Jose, CA, 2006.
• C. Lin, H. Zhou, and A. Xie, Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, San Jose, CA, 2006.
• P. Narayana, R. Chen, Y. Zhao, Y. Chen, Z. Fu, and H. Zhou. Automatic Vulnerability Checking of IEEE 802.16 WiMAX Protocols through TLA+. Second Workshop on Secure Network Protocols, Santa Barbara, CA, 2006.