Thermal-Aware High-Performance DRAM Architectures in Multicore Technologies

Seda O. Memik, Gokhan Memik

Department of Electrical Engineering and Computer Science

Northwestern University

ABSTRACT

Environment Protection Agency estimates that by 2011 data centers nationwide would consume electricity amounting to the equivalent output of about 30 power plants. Clearly, improving the power and thermal behavior of these systems has a direct impact on their energy efficiency and reliable operation. DRAM memories constitute a significant fraction of the power consumed in computers. In addition, in the dawning era of multi-/many-core processors, the performance of a system is largely dependant on its main memory efficiency. This project investigates ways to operate DRAMs at full bandwidth utilization while spending the minimum power per unit of data communicated and maintaining lower operating temperatures. Specifically, this work aims at answering three fundamental questions: a) how can we enhance processor architectures to balance the activity on different DRAM chips to protect chips under thermal stress, b) how can we enhance the DRAM systems to reduce their power consumption and peak operating temperatures, and c) how can we enhance the operating systems to improve the thermal behavior of DRAM systems?

Summary

Techniques developed in this project will improve the thermal behavior of DRAM systems and hence will reduce the cost of thermal management and decrease the system energy consumption. Furthermore, these improvements will enable new generations of high-performance processors. This, in turn, will enhance the computational capabilities of future computing systems and enable progress in various fields. Finally, projects derived from this work will be integrated into courses contributing to the training of an engineering workforce for an energy-efficient and sustainable society.

Technological advances in microprocessor architectures enable high performance with an underlying assumption on a matching increase in utilization of the memory systems. Particularly, Chip Multi-Processors (CMPs) are leading to significant rises in computational capacity. In order to satisfy the increasing bandwidth needs, designers increase the densities and number of devices of DRAM memory modules. However, increasing memory densities and data rates lead to higher power consumption and operating temperatures in DRAM systems. As a result of these trends, DRAM temperature control has become a practical and pressing issue. Existing high-performance DRAM systems achieve thermal control by trading off performance through throttling of the memory controller. Similar approaches are applied to processor core temperature management (e.g., DVFS). These approaches to thermal management are limited in scope and are mostly geared towards reactive approaches to thermal emergencies as opposed to preventive measures. Furthermore, they consider the DRAM as a single entity and are overly conservative. The main argument of the proposed project is that specialized solutions need to be developed to manage the temperature of DRAM structures. Specifically, the PIs propose to develop preventive architectural techniques and operating system-level methods that address the unique challenges and thermal characteristics of DRAM systems. The main questions to be investigated are:

1. How can we enhance processor architectures to balance the activity on different DRAM chips by redistributing the load to protect chips under thermal stress?

2. How can we enhance the DRAM systems to reduce their power consumption (hence, their peak operating temperatures) and improve their overall efficiency?

3. How can we enhance the operating systems to improve the thermal behavior of the DRAM systems?

To attack these problems, we develop architectural optimizations and run-time systems for balancing the memory traffic among different chips in a DRAM system and improving the access efficiency of the DRAM system. Specifically, we will develop

1. A temperature-aware cache replacement policy to improve the DRAM thermal behavior,

2. Enhancements to the memory controller for improving the page hit rate and hence, the power efficiency of DRAM accesses,

3. A memory controller design for streaming applications to improve the DRAM efficiency,

4. An analysis and optimization framework for determining architectural configurations of shared resources in the multicore system for improving the DRAM utilization,

5. A page allocation scheme that minimizes the variation of accesses among different DRAM chips and thereby optimize the overall DIMM temperature, and

6. A system-level thermal model for DIMMs.

This work is supported by

National Science Foundation Grant #0916746 (Program Officer: Sankar Basu)