Northwestern University

Electrical Engineering and Computer Science Department

We have explored new algorithms for reducing the execution-time and energy consumption of system-level designs. Moreover, we have proposed methods to apply well-known synthesis operations, such that the result of synthesis can be efficiently verified.

System-level Synthesis and its Impact on Verification

Research Interests

We have worked on abstraction techniques that enable the usage of automated verification methods, i.e., model checking, for the verification of distributed systems. Our work has targeted a class of distributed systems called self-stabilizing systems that can recover from any transient fault without human intervention.

Verification of Distributed Systems

We have explored power-efficient alternatives for bus architectures. Our work targeted the AMBA protocol.

Interface synthesis for SoCs

We have explored the complexity of sequential equivalence checking of hardware systems. We have proposed novel methods to perform synthesis, so that without reduction in the optimization power of the synthesis operations, the result is still verifiable.

Verification of Sequential Circuits