Course Description

This is a new seminar course which will explore advanced topics in two broad areas that will have a significant influence in computer systems design over the next decade: power related issues (energy/temperature) and reliability. The main learning vehicles will be readings of classic and recent research papers on both topics, followed by in-class discussions and critiques. Students will be expected to participate in all in-class sessions and occassionally lead a discussion. In addition, students will be required to write short (less than one-page) critical analyses of the research papers.

This course is geared to graduate students in computer engineering and systems (architecture, VLSI/CAD, operating systems, programming languages/compiler design). There is no formal list of prerequisites, but students are expected to have a basic understanding of computer architecture principles.

Course Syllabus

Reading Schedule

• Power: A First-Class Architectural Design Constraint. Trevor Mudge. IEEE Copmuter 2001. [pdf]
• Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. David Brooks et. al. IEEE Computer 2000. [pdf]

• David Brooks, Vivek Tiwari, and Margaret Martonosi. "Wattch: A Framework for Architectural-Level Power Analysis and Optimizations," 27th International Symposium on Computer Architecture (ISCA), Vancouver, British Columbia, June 2000. [pdf]
• Integrated analysis of power and performance for pipelined microprocessors Zyuban, V.; Brooks, D.; Viji Srinivasan; Gschwind, M.; Pradip Bose; Strenski, P.N.; Emma, P.G.; Computers, IEEE Transactions on Volume 53, Issue 8, Aug. 2004 Page(s):1004 - 1016 [pdf]

• Reducing power with dynamic critical path information Seng, J.S.; Tune, E.S.; Tullsen, D.M.; Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International Symposium on 1-5 Dec. 2001 Page(s):114 - 123 [pdf]
• The Filter Cache: An Energy Efficient Memory Structure Johnson Kin, Munish Gupta, William H. Mangione-Smith International Symposium on Microarchitecture MICRO-30 [pdf]
• Pipeline gating: speculation control for energy reduction Srilatha Manne, Artur Klauser, Dirk Grunwald Proceedings of the 25th international symposium on Computer architecture (ISCA-25) [pdf]

• Stefanos Kaxiras, Zhigang Hu, and Margaret Martonosi, "Cache Decay: Exploiting Generational Behaviour to Reduce Cache Leakage Power," the 28th International Symposium on Computer Architecture. June, 2001. [pdf]
• N.S. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J.S. Hu, M.J. Irwin, M. Kandemir, and V. Narayanan, "Leakage Current: Moore's Law Meets Static Power," Computer, vol. 36, no. 12, Dec. 2003. [pdf]
• S. Dropsho, V. Kursun, D.H. Albonesi, S. Dwarkadas, and E.G. Friedman, "Managing Static Leakage Energy in Microprocessor Functional Units," the 35th International Symposium on Microarchitecture, pp. 321-332, November 2002. [pdf]

• Focus Paper: K. Skadron, M.R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, ``Temperature-Aware Computer Systems: Opportunities and Challenges.'' IEEE Micro, 23(6), Nov-Dec. 2003 [pdf]
• Supplemental Paper: S. Gunther, F. Binns, D. Carmean, and J. Hall, ``Managing the Impact of Increasing Microprocessor Power Consumption'' Intel Technology Journal 2001 Q1

• Focus Paper (Summary Required By Class Time): Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Toan Pham, Rajeev Rao, Conrad Ziesler, David Blaauw, Todd Austin, Trevor Mudge, and Krisztin Flautner, ``Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation'', in the 36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003 [pdf]

• Focus Paper (Summary Required By Class Time): Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction, Rakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen, In 36th International Symposium on Microarchitecture, December, 2003. [pdf]
• Secondary Discussion Paper: Heat-and-run: Leveraging SMT and CMP to manage power density through the operating system. Michael Powell, Mohamed Gomaa, and T. N. Vijaykumar In Proceedings of the 11th International Conference on architectural support for programming languages and operating systems (ASPLOS), pages 260-270, October 2004 [pdf]
• Supplemental Paper (Optional): Mitigating Amdahl's Law through EPI Throttling Murali Annavaram, Ed Grochowski, John Shen June 2005 Proceedings of the 32nd Annual International Symposium on Computer Architecture ISCA '05 [pdf]

• Focus Paper: Power and performance evaluation of globally asynchronous locally synchronous processors Anoop Iyer, Diana Marculescu, May 2002, ACM SIGARCH Computer Architecture News, Volume 30 Issue 2 [pdf]
• Focus Paper: G. Semeraro, G. Magklis, R. Balasubramonian, D.H. Albonesi, S. Dwarkadas, and M.L. Energy Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency 8th International Symposium on High-Performance Computer Architecture, Feb 2002 [ps]
• Supplemental Paper (Optional): Q.Wu, P. Juang, M. Martonosi, and D.W. Formal Online Methods for Voltage/Frequency Control in Multiple Clock Domain Microprocessors. ASPLOS 2004. [pdf]

• Focus Paper: R. Joseph, D. Brooks, and M. Control Techniques to Eliminate Voltage Emergencies in High Performance The International Symposium on High Performance Computer Architecture (HPCA), February 2003. [pdf]
• Secondary Discussion Paper: Exploiting Resonant Behavior to Reduce Inductive Noise Michael D. Powell, T. N. Vijaykumar March 2004 ACM SIGARCH Computer Architecture News , Proceedings of the 31st Annual International Symposium on Computer Architecture 04, Volume 32 Issue 2 [pdf]
• Supplemental Paper (Optional): E. Grochowski, D. Ayers, and V. Microarchitectural Simulation and Control of di/dtinduced Power Supply The International Symposium on High Performance Computer Architecture (HPCA), February 2002. [pdf]

• Focus Paper (Summary): Shubhendu S. Mukherjee, Christopher Weaver, Joel Emer, Steven K. Reinhardt, and Todd Austin, A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor, in the 36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003. [pdf]

• Focus Paper: Nicholas J. Wang, Justin Quek, Todd M. Rafacz, and Sanjay J. Patel, Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline, Proceedings of the 2004 International Conference on Dependable Systems and Networks, Florence, Italy, June 2004 [pdf]

• Focus Paper (Summary): Transient-Fault Recovery for Chip Multiprocessors Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, and Irith Pomeranz In Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), pages 98-109, June 2003. [pdf]
• Opportunistic Transient-Fault Detection Mohamed Gomaa and T. N. Vijaykumar In Proceedings of the 32nd Annual International Symposium on Computer Architecture (ISCA), pages 172-183, June 2005. [pdf]
• Transient-Fault Recovery via Simultaneous Multithreading T. N. Vijaykumar, Irith Pomeranz, and Karl Cheng In Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA), pages 87-98, May 2002. [pdf]

• Focus Paper: SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery, Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood, International Symposium on Computer Architecture (ISCA), May 2002. [pdf]

• Focus Paper (Summary): Rescue: A Microarchitecture for Testability and Defect Tolerance Ethan Schuchman and T. N. Vijaykumar In Proceedings of the 32nd Annual International Symposium on Computer Architecture (ISCA), pages 160-171, June 2005. [pdf]

• Focus Paper: Fred A. Bower, Daniel J. Sorin, and Sule Ozev. ``A Mechanism for Online Diagnosis of Hard Faults in Microprocessors.'' To appear in 38th Annual International Symposium on Microarchitecture (MICRO), November 2005 [pdf]
• Fred A. Bower, Paul G. Shealy, Sule Ozev, and Daniel J. Sorin. ``Tolerating Hard Faults in Microprocessor Array Structures.'' International Conference on Dependable Systems and Networks (DSN), June 2004. [pdf]
• A Fault Tolerant Approach to Microprocesor Design. Chris Weaver and Todd Austin. International Conference on Dependable Systems and Networks (DSN), July 2001. [pdf]

• Focus Paper (Summary): The Case for Lifetime Reliability-Aware Microprocessors, Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, and Jude A. Rivers, Proceedings of 31st International Symposium on Computer Architecture (ISCA '04) June 2004. [pdf]
• Exploiting Structural Duplication for Lifetime Reliability Enhancement, Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers, To appear in the Proceedings of the 32nd International Symposium on Computer Architecture (ISCA'05) June 2005. [pdf]

• Focus Paper (Summary): NanoFabrics: Spatial Computing Using Molecular Electronics (2001) Seth Copen Goldstein, Mihai Budiu Proceedings of the 28th International Symposium on Computer Architecture 2001 [pdf]

• Focus Paper: A Case for Clumsy Packet Processors A. Mallik and G. Memik In Proc. of IEEE/ACM International Symposium on Microarchitecture (MICRO-37), Portland, OR, Dec. 2004 [pdf]