
---------- Begin Simulation Statistics ----------
host_inst_rate                                  32388                       # Simulator instruction rate (inst/s)
host_mem_usage                                 192928                       # Number of bytes of host memory used
host_seconds                                 24118.89                       # Real time elapsed on the host
host_tick_rate                                 298517                       # Simulator tick rate (ticks/s)
sim_freq                                   4000000000                       # Frequency of simulated ticks
sim_insts                                   781158668                       # Number of instructions simulated
sim_seconds                                  1.799973                       # Number of seconds simulated
sim_ticks                                  7199893257                       # Number of ticks simulated
system.cpu.COM:IPB                           3.124504                       # Committed instructions per branch
system.cpu.COM:IPC                           0.108496                       # Committed instructions per cycle
system.cpu.COM:branches                     250010432                       # Number of branches committed
system.cpu.COM:bw_lim_avg                <err: div-0>                       # Avg number not committed in cycles BW limited
system.cpu.COM:bw_lim_events                        0                       # number cycles where commit BW limit reached
system.cpu.COM:bw_lim_rate                     0.0000                       # Average number not committed due to BW (over all cycles)
system.cpu.COM:bw_lim_stdev_0_mean       <err: div-0>                       # standard deviation of bw_lim_avg value
system.cpu.COM:bw_lim_stdev_0_stdev      <err: div-0>                       # standard deviation of bw_lim_avg value
**Ignore: system.cpu.COM:bw_lim_stdev_0_TOT       0.0000                       # standard deviation of bw_lim_avg value
system.cpu.COM:bw_limited                           0                       # number of insts not committed due to BW limits
system.cpu.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu.COM:committed_per_cycle.samples    137873601                      
system.cpu.COM:committed_per_cycle.min_value            0                      
                               0       356928     25.89%           
                               1      6521455    473.00%           
                               2      6656054    482.76%           
                               3     15959840   1157.57%           
                               4     22993762   1667.74%           
                               5       754491     54.72%           
                               6     22290008   1616.70%           
                               7     14558766   1055.95%           
                               8     47782297   3465.66%           
system.cpu.COM:committed_per_cycle.max_value            8                      
system.cpu.COM:committed_per_cycle.end_dist

system.cpu.COM:count                        781158668                       # Number of instructions committed
system.cpu.COM:loads                         10485438                       # Number of loads committed
system.cpu.COM:membars                         267027                       # Number of memory barriers committed
system.cpu.COM:refs                          17903844                       # Number of memory references committed
system.cpu.COM:stores                         7418406                       # Number of stores committed
system.cpu.COM:swp_count                       211704                       # Number of s/w prefetches committed
system.cpu.DDQ:count                      21434235834                       # cum count of instructions
system.cpu.DDQ:rate                                 3                       # average number of instructions
system.cpu.DIS:chain_creation.start_dist
     Inst has no outstanding IDEPS            0      0.00%            # Reason that chain head was created
      IDEP chain reached max depth            0      0.00%            # Reason that chain head was created
                    Inst is a load            0      0.00%            # Reason that chain head was created
  Chain has multiple chained IDEPS            0      0.00%            # Reason that chain head was created
system.cpu.DIS:chain_creation.end_dist
system.cpu.DIS:chain_head_frac                      0                       # fraction of insts that are chain heads
system.cpu.DIS:chain_heads                          0                       # number insts that are chain heads
system.cpu.DIS:chains_insuf                         0                       # number of times thread had insuf chains
system.cpu.DIS:chains_insuf_rate                    0                       # rate that thread had insuf chains
system.cpu.DIS:count                        812324051                       # cumulative count of dispatched insts
system.cpu.DIS:insufficient_chains                  0                       # Number of instances where dispatch stopped
system.cpu.DIS:mod_n_stall_avg_free          no value                       # avg free slots per cycle
system.cpu.DIS:mod_n_stall_frac                     0                       # avg stalls per cycle
system.cpu.DIS:mod_n_stall_free                     0                       # free slots when dispatch stalled due to mod-n
system.cpu.DIS:mod_n_stalls                         0                       # cycles where dispatch stalled due to mod-n
system.cpu.DIS:one_rdy_insts                        0                       # number of 2-op insts w/ one rdy op
system.cpu.DIS:one_rdy_ratio                 no value                       # fraction of 2-op insts w/ one ready op
system.cpu.DIS:op_count                     837535463                       # number of operations dispatched
system.cpu.DIS:op_rate                       0.116326                       # dispatched operations per cycle
system.cpu.DIS:rate                          0.112824                       # dispatched_insts per cycle
system.cpu.DIS:second_choice_clust                  0                       # Number of instructions dispatched to second-choice cluster
system.cpu.DIS:second_choice_stall                  0                       # Number of instructions stalled when first choice not available
system.cpu.DIS:serialize_stall_cycles         7148610                       # count of cycles dispatch stalled for serializing inst
system.cpu.DIS:serializing_insts               464106                       # count of serializing insts dispatched
system.cpu.DIS:two_input_insts                      0                       # Number of two input instructions queued
system.cpu.DIS:two_input_ratio                      0                       # fraction of all insts having 2 inputs
system.cpu.FETCH:branch_count               266934688                       # Number of branches fetched
system.cpu.FETCH:branch_rate                 0.037075                       # Number of branch fetches per cycle
system.cpu.FETCH:chance_pct                         1                       # Percentage of all fetch chances
system.cpu.FETCH:chances                    145992410                       # Number of fetch opportunities
system.cpu.FETCH:choice                     145992410                       # Number of times we fetched from our first choice
system.cpu.FETCH:count                      896034769                       # Number of instructions fetched
system.cpu.FETCH:decisions                  145992410                       # number of times the fetch stage chose between threads
system.cpu.FETCH:idle_cycles               7053900848                       # number of cycles where fetch stage was idle
system.cpu.FETCH:idle_icache_blocked_cycles            0                       # number of cycles where fetch was idle due to icache blocked
system.cpu.FETCH:idle_rate                      97.97                       # percent of cycles fetch stage was idle
system.cpu.FETCH:prio_changes                       0                       # Number of times priorities were changed
system.cpu.FETCH:rate                        0.124451                       # Number of inst fetches per cycle
system.cpu.FETCH:rate_dist.start_dist                          # Number of instructions fetched each cycle (Total)
system.cpu.FETCH:rate_dist.samples          145992410                      
system.cpu.FETCH:rate_dist.min_value                0                      
                               0       196709     13.47%           
                               1       347751     23.82%           
                               2       628624     43.06%           
                               3      2968917    203.36%           
                               4       988347     67.70%           
                               5       408479     27.98%           
                               6    121581296   8327.92%           
                               7       938836     64.31%           
                               8     17933451   1228.38%           
system.cpu.FETCH:rate_dist.max_value                8                      
system.cpu.FETCH:rate_dist.end_dist

system.cpu.FETCH:rate_dist_0.start_dist                        # Number of instructions fetched each cycle (Thread 0)
system.cpu.FETCH:rate_dist_0.samples        145992410                      
system.cpu.FETCH:rate_dist_0.min_value              0                      
                               0       196709     13.47%           
                               1       347751     23.82%           
                               2       628624     43.06%           
                               3      2968917    203.36%           
                               4       988347     67.70%           
                               5       408479     27.98%           
                               6    121581296   8327.92%           
                               7       938836     64.31%           
                               8     17933451   1228.38%           
system.cpu.FETCH:rate_dist_0.max_value              8                      
system.cpu.FETCH:rate_dist_0.end_dist

system.cpu.IFQ:count                       5370236211                       # cumulative IFQ occupancy
system.cpu.IFQ:full_count                   159466415                       # cumulative IFQ full count
system.cpu.IFQ:full_rate                     2.214844                       # fraction of time (cycle's) IFQ was full
system.cpu.IFQ:latency                       6.610953                       # avg IFQ occupant latency (cycle's)
system.cpu.IFQ:occupancy                     0.745877                       # avg IFQ occupancy (inst's)
system.cpu.IFQ:qfull_iq_occ                3495781829                       # Number of insts in IQ when fetch-queue full
system.cpu.IFQ:qfull_iq_occ_dist_0.start_dist                     # Number of insts in IQ when fetch-queue full
system.cpu.IFQ:qfull_iq_occ_dist_0.samples     34963479                      
system.cpu.IFQ:qfull_iq_occ_dist_0.min_value            0                      
                               0      5081776   1453.45%           
                              10       358941    102.66%           
                              20       413497    118.27%           
                              30       700541    200.36%           
                              40       701234    200.56%           
                              50       294344     84.19%           
                              60       654573    187.22%           
                              70       190644     54.53%           
                              80        94566     27.05%           
                              90      4079377   1166.75%           
                             100       615365    176.00%           
                             110        59423     17.00%           
                             120     20688848   5917.27%           
                             130        20944      5.99%           
                             140        38226     10.93%           
                             150         7468      2.14%           
                             160        20355      5.82%           
                             170        72770     20.81%           
                             180       215631     61.67%           
                             190         7153      2.05%           
                             200         4246      1.21%           
                             210         1936      0.55%           
                             220         4574      1.31%           
                             230        14058      4.02%           
                             240         5094      1.46%           
                             250       617895    176.73%           
                             260            0      0.00%           
system.cpu.IFQ:qfull_iq_occ_dist_0.max_value          256                      
system.cpu.IFQ:qfull_iq_occ_dist_0.end_dist

system.cpu.IFQ:qfull_rob_occ               6739823539                       # Number of insts in ROB when fetch-queue full
system.cpu.IFQ:qfull_rob_occ_dist_0.start_dist                     # Number of insts in ROB when fetch-queue full
system.cpu.IFQ:qfull_rob_occ_dist_0.samples     34963479                      
system.cpu.IFQ:qfull_rob_occ_dist_0.min_value            1                      
                               0       621996    177.90%           
                              10       834255    238.61%           
                              20       628586    179.78%           
                              30       204435     58.47%           
                              40       156964     44.89%           
                              50        90077     25.76%           
                              60       161793     46.27%           
                              70       526331    150.54%           
                              80       484683    138.63%           
                              90       327602     93.70%           
                             100      4051396   1158.75%           
                             110       300622     85.98%           
                             120       291227     83.29%           
                             130       571685    163.51%           
                             140       213363     61.02%           
                             150       172919     49.46%           
                             160        91152     26.07%           
                             170        47407     13.56%           
                             180       235144     67.25%           
                             190     20624967   5899.00%           
                             200       278424     79.63%           
                             210        66538     19.03%           
                             220        54186     15.50%           
                             230        39198     11.21%           
                             240        26573      7.60%           
                             250       211420     60.47%           
                             260        21554      6.16%           
                             270        17809      5.09%           
                             280        18897      5.40%           
                             290        12677      3.63%           
                             300        24232      6.93%           
                             310        27766      7.94%           
                             320        29971      8.57%           
                             330        11124      3.18%           
                             340        11241      3.22%           
                             350        16396      4.69%           
                             360        35739     10.22%           
                             370        16850      4.82%           
                             380       291803     83.46%           
                             390       173985     49.76%           
                             400        15014      4.29%           
                             410        26381      7.55%           
                             420        11527      3.30%           
                             430        13282      3.80%           
                             440        16990      4.86%           
                             450        14581      4.17%           
                             460         9603      2.75%           
                             470         4784      1.37%           
                             480         2330      0.67%           
                             490         3598      1.03%           
                             500         8329      2.38%           
                             510      2814073    804.86%           
system.cpu.IFQ:qfull_rob_occ_dist_0.max_value          512                      
system.cpu.IFQ:qfull_rob_occ_dist_0.end_dist

system.cpu.IQ:cap_events                            0                       # number of cycles where IQ cap was active
system.cpu.IQ:cap_inst                              0                       # number of instructions held up by IQ cap
system.cpu.IQ:residence:(null).start_dist                      # cycles from dispatch to issue
system.cpu.IQ:residence:(null).samples           6962                      
system.cpu.IQ:residence:(null).min_value            1                      
                               0         6743   9685.44%   9685.44%
                               2          210    301.64%   9987.07%
                               4            5      7.18%   9994.25%
                               6            3      4.31%   9998.56%
                               8            0      0.00%   9998.56%
                              10            0      0.00%   9998.56%
                              12            1      1.44%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu.IQ:residence:(null).max_value           13                      
system.cpu.IQ:residence:(null).end_dist

system.cpu.IQ:residence:IntAlu.start_dist                      # cycles from dispatch to issue
system.cpu.IQ:residence:IntAlu.samples      770279760                      
system.cpu.IQ:residence:IntAlu.min_value            1                      
                               0     11141531    144.64%    144.64%
                               2      7445929     96.67%    241.31%
                               4      5146800     66.82%    308.13%
                               6      3997906     51.90%    360.03%
                               8      2682230     34.82%    394.85%
                              10      2086319     27.09%    421.93%
                              12      1731018     22.47%    444.41%
                              14      1484578     19.27%    463.68%
                              16      1216666     15.80%    479.47%
                              18      1026809     13.33%    492.81%
                              20       860737     11.17%    503.98%
                              22       831739     10.80%    514.78%
                              24       785812     10.20%    524.98%
                              26       595775      7.73%    532.71%
                              28       581917      7.55%    540.27%
                              30       660597      8.58%    548.84%
                              32       470013      6.10%    554.95%
                              34       370130      4.81%    559.75%
                              36       300922      3.91%    563.66%
                              38       282873      3.67%    567.33%
                              40     67326719    874.06%   1441.39%
                              42    526032159   6829.11%   8270.49%
                              44    126858759   1646.92%   9917.41%
                              46       109956      1.43%   9918.84%
                              48        97712      1.27%   9920.10%
                              50        97498      1.27%   9921.37%
                              52       213458      2.77%   9924.14%
                              54       174289      2.26%   9926.40%
                              56       116602      1.51%   9927.92%
                              58        67337      0.87%   9928.79%
                              60        60870      0.79%   9929.58%
                              62       180156      2.34%   9931.92%
                              64       142017      1.84%   9933.77%
                              66        91337      1.19%   9934.95%
                              68       112668      1.46%   9936.41%
                              70        99769      1.30%   9937.71%
                              72        80006      1.04%   9938.75%
                              74        69862      0.91%   9939.65%
                              76        53659      0.70%   9940.35%
                              78        57859      0.75%   9941.10%
                              80        36667      0.48%   9941.58%
                              82        34460      0.45%   9942.03%
                              84        24008      0.31%   9942.34%
                              86        30064      0.39%   9942.73%
                              88        27350      0.36%   9943.08%
                              90        23973      0.31%   9943.39%
                              92        26698      0.35%   9943.74%
                              94        29222      0.38%   9944.12%
                              96        25374      0.33%   9944.45%
                              98        26568      0.34%   9944.79%
system.cpu.IQ:residence:IntAlu.overflows      4252383                      
system.cpu.IQ:residence:IntAlu.max_value        13139                      
system.cpu.IQ:residence:IntAlu.end_dist

system.cpu.IQ:residence:IntMult.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:IntMult.samples         69630                      
system.cpu.IQ:residence:IntMult.min_value            1                      
                               0         1860    267.13%    267.13%
                               2         1118    160.56%    427.69%
                               4         8488   1219.01%   1646.70%
                               6         4717    677.44%   2324.14%
                               8         4644    666.95%   2991.10%
                              10         7085   1017.52%   4008.62%
                              12         4986    716.07%   4724.69%
                              14         3054    438.60%   5163.29%
                              16         2016    289.53%   5452.82%
                              18         1408    202.21%   5655.03%
                              20          229     32.89%   5687.92%
                              22          707    101.54%   5789.46%
                              24         3106    446.07%   6235.53%
                              26          527     75.69%   6311.22%
                              28         2101    301.74%   6612.95%
                              30          198     28.44%   6641.39%
                              32           77     11.06%   6652.45%
                              34         1812    260.23%   6912.68%
                              36           99     14.22%   6926.90%
                              38         1294    185.84%   7112.74%
                              40          330     47.39%   7160.13%
                              42          388     55.72%   7215.86%
                              44         1281    183.97%   7399.83%
                              46          120     17.23%   7417.06%
                              48          147     21.11%   7438.17%
                              50          578     83.01%   7521.18%
                              52           85     12.21%   7533.39%
                              54          513     73.68%   7607.07%
                              56           79     11.35%   7618.41%
                              58          529     75.97%   7694.38%
                              60           60      8.62%   7703.00%
                              62           47      6.75%   7709.75%
                              64          487     69.94%   7779.69%
                              66          418     60.03%   7839.72%
                              68           66      9.48%   7849.20%
                              70          402     57.73%   7906.94%
                              72         9144   1313.23%   9220.16%
                              74          160     22.98%   9243.14%
                              76          107     15.37%   9258.51%
                              78           41      5.89%   9264.40%
                              80           22      3.16%   9267.56%
                              82          113     16.23%   9283.79%
                              84           15      2.15%   9285.94%
                              86          146     20.97%   9306.91%
                              88            7      1.01%   9307.91%
                              90          237     34.04%   9341.95%
                              92           18      2.59%   9344.54%
                              94           12      1.72%   9346.26%
                              96            9      1.29%   9347.55%
                              98           15      2.15%   9349.71%
system.cpu.IQ:residence:IntMult.overflows         4528                      
system.cpu.IQ:residence:IntMult.max_value          513                      
system.cpu.IQ:residence:IntMult.end_dist

system.cpu.IQ:residence:IntDiv.start_dist                      # cycles from dispatch to issue
system.cpu.IQ:residence:IntDiv.samples              0                      
system.cpu.IQ:residence:IntDiv.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.IQ:residence:IntDiv.max_value            0                      
system.cpu.IQ:residence:IntDiv.end_dist

system.cpu.IQ:residence:FloatAdd.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:FloatAdd.samples         9257                      
system.cpu.IQ:residence:FloatAdd.min_value            1                      
                               0          988   1067.30%   1067.30%
                               2          869    938.75%   2006.05%
                               4         2086   2253.43%   4259.48%
                               6         2584   2791.40%   7050.88%
                               8            9      9.72%   7060.60%
                              10            1      1.08%   7061.68%
                              12            1      1.08%   7062.76%
                              14            2      2.16%   7064.92%
                              16           28     30.25%   7095.17%
                              18           30     32.41%   7127.58%
                              20            2      2.16%   7129.74%
                              22            0      0.00%   7129.74%
                              24         2609   2818.41%   9948.15%
                              26           11     11.88%   9960.03%
                              28            0      0.00%   9960.03%
                              30            0      0.00%   9960.03%
                              32            1      1.08%   9961.11%
                              34            0      0.00%   9961.11%
                              36            0      0.00%   9961.11%
                              38            0      0.00%   9961.11%
                              40            0      0.00%   9961.11%
                              42            0      0.00%   9961.11%
                              44            0      0.00%   9961.11%
                              46            0      0.00%   9961.11%
                              48            0      0.00%   9961.11%
                              50            0      0.00%   9961.11%
                              52            0      0.00%   9961.11%
                              54            0      0.00%   9961.11%
                              56            0      0.00%   9961.11%
                              58            0      0.00%   9961.11%
                              60            0      0.00%   9961.11%
                              62            0      0.00%   9961.11%
                              64            3      3.24%   9964.35%
                              66           26     28.09%   9992.44%
                              68            0      0.00%   9992.44%
                              70            0      0.00%   9992.44%
                              72            2      2.16%   9994.60%
                              74            0      0.00%   9994.60%
                              76            0      0.00%   9994.60%
                              78            0      0.00%   9994.60%
                              80            0      0.00%   9994.60%
                              82            0      0.00%   9994.60%
                              84            1      1.08%   9995.68%
                              86            0      0.00%   9995.68%
                              88            0      0.00%   9995.68%
                              90            0      0.00%   9995.68%
                              92            0      0.00%   9995.68%
                              94            0      0.00%   9995.68%
                              96            0      0.00%   9995.68%
                              98            0      0.00%   9995.68%
system.cpu.IQ:residence:FloatAdd.overflows            4                      
system.cpu.IQ:residence:FloatAdd.max_value          145                      
system.cpu.IQ:residence:FloatAdd.end_dist

system.cpu.IQ:residence:FloatCmp.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:FloatCmp.samples            0                      
system.cpu.IQ:residence:FloatCmp.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.IQ:residence:FloatCmp.max_value            0                      
system.cpu.IQ:residence:FloatCmp.end_dist

system.cpu.IQ:residence:FloatCvt.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:FloatCvt.samples            0                      
system.cpu.IQ:residence:FloatCvt.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.IQ:residence:FloatCvt.max_value            0                      
system.cpu.IQ:residence:FloatCvt.end_dist

system.cpu.IQ:residence:FloatMult.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:FloatMult.samples            0                      
system.cpu.IQ:residence:FloatMult.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.IQ:residence:FloatMult.max_value            0                      
system.cpu.IQ:residence:FloatMult.end_dist

system.cpu.IQ:residence:FloatDiv.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:FloatDiv.samples           62                      
system.cpu.IQ:residence:FloatDiv.min_value            1                      
                               0            1    161.29%    161.29%
                               2            1    161.29%    322.58%
                               4            0      0.00%    322.58%
                               6           58   9354.84%   9677.42%
                               8            0      0.00%   9677.42%
                              10            0      0.00%   9677.42%
                              12            0      0.00%   9677.42%
                              14            0      0.00%   9677.42%
                              16            0      0.00%   9677.42%
                              18            0      0.00%   9677.42%
                              20            0      0.00%   9677.42%
                              22            1    161.29%   9838.71%
                              24            0      0.00%   9838.71%
                              26            0      0.00%   9838.71%
                              28            0      0.00%   9838.71%
                              30            0      0.00%   9838.71%
                              32            0      0.00%   9838.71%
                              34            0      0.00%   9838.71%
                              36            0      0.00%   9838.71%
                              38            0      0.00%   9838.71%
                              40            0      0.00%   9838.71%
                              42            0      0.00%   9838.71%
                              44            0      0.00%   9838.71%
                              46            0      0.00%   9838.71%
                              48            0      0.00%   9838.71%
                              50            0      0.00%   9838.71%
                              52            0      0.00%   9838.71%
                              54            0      0.00%   9838.71%
                              56            0      0.00%   9838.71%
                              58            0      0.00%   9838.71%
                              60            0      0.00%   9838.71%
                              62            0      0.00%   9838.71%
                              64            0      0.00%   9838.71%
                              66            0      0.00%   9838.71%
                              68            0      0.00%   9838.71%
                              70            0      0.00%   9838.71%
                              72            0      0.00%   9838.71%
                              74            1    161.29%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu.IQ:residence:FloatDiv.max_value           74                      
system.cpu.IQ:residence:FloatDiv.end_dist

system.cpu.IQ:residence:FloatSqrt.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:FloatSqrt.samples            0                      
system.cpu.IQ:residence:FloatSqrt.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.IQ:residence:FloatSqrt.max_value            0                      
system.cpu.IQ:residence:FloatSqrt.end_dist

system.cpu.IQ:residence:MemRead.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:MemRead.samples      25583395                      
system.cpu.IQ:residence:MemRead.min_value            1                      
                               0      4827740   1887.06%   1887.06%
                               2      6333879   2475.78%   4362.84%
                               4      2414213    943.66%   5306.50%
                               6      1793367    700.99%   6007.49%
                               8      1224107    478.48%   6485.97%
                              10      1005951    393.20%   6879.17%
                              12       699771    273.53%   7152.70%
                              14       611968    239.21%   7391.90%
                              16       540238    211.17%   7603.07%
                              18       408239    159.57%   7762.64%
                              20       306180    119.68%   7882.32%
                              22       294984    115.30%   7997.62%
                              24       306616    119.85%   8117.47%
                              26       297538    116.30%   8233.77%
                              28       258056    100.87%   8334.64%
                              30       240775     94.11%   8428.76%
                              32       174914     68.37%   8497.13%
                              34       205043     80.15%   8577.27%
                              36       136301     53.28%   8630.55%
                              38       125027     48.87%   8679.42%
                              40        80585     31.50%   8710.92%
                              42        56769     22.19%   8733.11%
                              44        56072     21.92%   8755.03%
                              46        52654     20.58%   8775.61%
                              48        52179     20.40%   8796.00%
                              50        91355     35.71%   8831.71%
                              52        38545     15.07%   8846.78%
                              54        97905     38.27%   8885.05%
                              56        40000     15.64%   8900.68%
                              58        27653     10.81%   8911.49%
                              60        64831     25.34%   8936.83%
                              62        45276     17.70%   8954.53%
                              64       116056     45.36%   8999.90%
                              66        40727     15.92%   9015.81%
                              68        44937     17.56%   9033.38%
                              70        54914     21.46%   9054.84%
                              72        30924     12.09%   9066.93%
                              74        22457      8.78%   9075.71%
                              76        14871      5.81%   9081.52%
                              78        18709      7.31%   9088.84%
                              80        34771     13.59%   9102.43%
                              82        18113      7.08%   9109.51%
                              84        12846      5.02%   9114.53%
                              86        17753      6.94%   9121.47%
                              88        15612      6.10%   9127.57%
                              90        13070      5.11%   9132.68%
                              92        13225      5.17%   9137.85%
                              94        16638      6.50%   9144.35%
                              96        15972      6.24%   9150.59%
                              98        12192      4.77%   9155.36%
system.cpu.IQ:residence:MemRead.overflows      2160877                      
system.cpu.IQ:residence:MemRead.max_value        17495                      
system.cpu.IQ:residence:MemRead.end_dist

system.cpu.IQ:residence:MemWrite.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:MemWrite.samples     16444285                      
system.cpu.IQ:residence:MemWrite.min_value            1                      
                               0      2508144   1525.24%   1525.24%
                               2      4595744   2794.74%   4319.97%
                               4      1844301   1121.55%   5441.52%
                               6      1359192    826.54%   6268.06%
                               8       859101    522.43%   6790.49%
                              10       835697    508.20%   7298.69%
                              12       674810    410.36%   7709.05%
                              14       523224    318.18%   8027.23%
                              16       288290    175.31%   8202.55%
                              18       218438    132.84%   8335.38%
                              20       184740    112.34%   8447.73%
                              22       211103    128.37%   8576.10%
                              24       217805    132.45%   8708.55%
                              26       163465     99.41%   8807.96%
                              28       151778     92.30%   8900.25%
                              30       173221    105.34%   9005.59%
                              32       128917     78.40%   9083.99%
                              34        90693     55.15%   9139.14%
                              36        74100     45.06%   9184.20%
                              38        59750     36.33%   9220.54%
                              40        54635     33.22%   9253.76%
                              42        41531     25.26%   9279.02%
                              44        28940     17.60%   9296.62%
                              46        28131     17.11%   9313.72%
                              48        20935     12.73%   9326.45%
                              50        23445     14.26%   9340.71%
                              52        84923     51.64%   9392.35%
                              54        83760     50.94%   9443.29%
                              56        31764     19.32%   9462.60%
                              58        40647     24.72%   9487.32%
                              60        46029     27.99%   9515.31%
                              62        44512     27.07%   9542.38%
                              64       180043    109.49%   9651.87%
                              66        26980     16.41%   9668.28%
                              68        20044     12.19%   9680.46%
                              70        20194     12.28%   9692.74%
                              72        13322      8.10%   9700.85%
                              74        18602     11.31%   9712.16%
                              76        17821     10.84%   9723.00%
                              78        28649     17.42%   9740.42%
                              80        27493     16.72%   9757.14%
                              82         7090      4.31%   9761.45%
                              84         6834      4.16%   9765.60%
                              86         5680      3.45%   9769.06%
                              88         4422      2.69%   9771.75%
                              90         5677      3.45%   9775.20%
                              92         5072      3.08%   9778.28%
                              94         6607      4.02%   9782.30%
                              96         6345      3.86%   9786.16%
                              98         5153      3.13%   9789.29%
system.cpu.IQ:residence:MemWrite.overflows       346492                      
system.cpu.IQ:residence:MemWrite.max_value        17503                      
system.cpu.IQ:residence:MemWrite.end_dist

system.cpu.IQ:residence:IprAccess.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:IprAccess.samples      1237369                      
system.cpu.IQ:residence:IprAccess.min_value            1                      
                               0       301670   2438.00%   2438.00%
                               2        46402    375.01%   2813.00%
                               4       241373   1950.70%   4763.70%
                               6       250184   2021.90%   6785.60%
                               8        38016    307.23%   7092.83%
                              10       201535   1628.74%   8721.57%
                              12        28536    230.62%   8952.19%
                              14        23256    187.95%   9140.14%
                              16        11311     91.41%   9231.55%
                              18        16770    135.53%   9367.08%
                              20        15022    121.40%   9488.48%
                              22         7536     60.90%   9549.38%
                              24        13427    108.51%   9657.90%
                              26        12200     98.60%   9756.49%
                              28         4772     38.57%   9795.06%
                              30         1558     12.59%   9807.65%
                              32         2454     19.83%   9827.48%
                              34         1424     11.51%   9838.99%
                              36         1973     15.95%   9854.93%
                              38          984      7.95%   9862.89%
                              40         1972     15.94%   9878.82%
                              42         1401     11.32%   9890.15%
                              44         1224      9.89%   9900.04%
                              46         1575     12.73%   9912.77%
                              48         1820     14.71%   9927.48%
                              50          590      4.77%   9932.24%
                              52          744      6.01%   9938.26%
                              54          663      5.36%   9943.61%
                              56          492      3.98%   9947.59%
                              58          327      2.64%   9950.23%
                              60          605      4.89%   9955.12%
                              62          349      2.82%   9957.94%
                              64          510      4.12%   9962.06%
                              66          725      5.86%   9967.92%
                              68          469      3.79%   9971.71%
                              70          155      1.25%   9972.97%
                              72          287      2.32%   9975.29%
                              74          286      2.31%   9977.60%
                              76          235      1.90%   9979.50%
                              78          115      0.93%   9980.43%
                              80          210      1.70%   9982.12%
                              82          143      1.16%   9983.28%
                              84          140      1.13%   9984.41%
                              86           78      0.63%   9985.04%
                              88           99      0.80%   9985.84%
                              90           89      0.72%   9986.56%
                              92           57      0.46%   9987.02%
                              94           75      0.61%   9987.63%
                              96           54      0.44%   9988.06%
                              98           61      0.49%   9988.56%
system.cpu.IQ:residence:IprAccess.overflows         1416                      
system.cpu.IQ:residence:IprAccess.max_value          360                      
system.cpu.IQ:residence:IprAccess.end_dist

system.cpu.IQ:residence:InstPrefetch.start_dist                     # cycles from dispatch to issue
system.cpu.IQ:residence:InstPrefetch.samples            0                      
system.cpu.IQ:residence:InstPrefetch.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.IQ:residence:InstPrefetch.max_value            0                      
system.cpu.IQ:residence:InstPrefetch.end_dist

system.cpu.ISSUE:(null)_delay.start_dist                       # cycles from operands ready to issue
system.cpu.ISSUE:(null)_delay.samples            6962                      
system.cpu.ISSUE:(null)_delay.min_value             1                      
                               0         6743   9685.44%   9685.44%
                               2          210    301.64%   9987.07%
                               4            5      7.18%   9994.25%
                               6            3      4.31%   9998.56%
                               8            0      0.00%   9998.56%
                              10            0      0.00%   9998.56%
                              12            1      1.44%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu.ISSUE:(null)_delay.max_value            13                      
system.cpu.ISSUE:(null)_delay.end_dist

system.cpu.ISSUE:IntAlu_delay.start_dist                       # cycles from operands ready to issue
system.cpu.ISSUE:IntAlu_delay.samples       770279760                      
system.cpu.ISSUE:IntAlu_delay.min_value             0                      
                               0    526319025   6832.83%   6832.83%
                               2      2540759     32.98%   6865.81%
                               4       482756      6.27%   6872.08%
                               6       227296      2.95%   6875.03%
                               8       146054      1.90%   6876.93%
                              10        76585      0.99%   6877.92%
                              12        99254      1.29%   6879.21%
                              14        55942      0.73%   6879.94%
                              16        61731      0.80%   6880.74%
                              18        50105      0.65%   6881.39%
                              20        33241      0.43%   6881.82%
                              22        29040      0.38%   6882.20%
                              24        26759      0.35%   6882.55%
                              26        26530      0.34%   6882.89%
                              28        25841      0.34%   6883.23%
                              30        26099      0.34%   6883.56%
                              32        24786      0.32%   6883.89%
                              34        24578      0.32%   6884.21%
                              36        24603      0.32%   6884.52%
                              38        24930      0.32%   6884.85%
                              40     64788706    841.11%   7725.95%
                              42    175165140   2274.05%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu.ISSUE:IntAlu_delay.max_value            43                      
system.cpu.ISSUE:IntAlu_delay.end_dist

system.cpu.ISSUE:IntMult_delay.start_dist                      # cycles from operands ready to issue
system.cpu.ISSUE:IntMult_delay.samples          69630                      
system.cpu.ISSUE:IntMult_delay.min_value            0                      
                               0        69593   9994.69%   9994.69%
                               2           32      4.60%   9999.28%
                               4            4      0.57%   9999.86%
                               6            1      0.14%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu.ISSUE:IntMult_delay.max_value            6                      
system.cpu.ISSUE:IntMult_delay.end_dist

system.cpu.ISSUE:IntDiv_delay.start_dist                       # cycles from operands ready to issue
system.cpu.ISSUE:IntDiv_delay.samples               0                      
system.cpu.ISSUE:IntDiv_delay.min_value             0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.ISSUE:IntDiv_delay.max_value             0                      
system.cpu.ISSUE:IntDiv_delay.end_dist

system.cpu.ISSUE:FloatAdd_delay.start_dist                     # cycles from operands ready to issue
system.cpu.ISSUE:FloatAdd_delay.samples          9257                      
system.cpu.ISSUE:FloatAdd_delay.min_value            0                      
                               0         5638   6090.53%   6090.53%
                               2          869    938.75%   7029.28%
                               4         1940   2095.71%   9124.99%
                               6          801    865.29%   9990.28%
                               8            9      9.72%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu.ISSUE:FloatAdd_delay.max_value            9                      
system.cpu.ISSUE:FloatAdd_delay.end_dist

system.cpu.ISSUE:FloatCmp_delay.start_dist                     # cycles from operands ready to issue
system.cpu.ISSUE:FloatCmp_delay.samples             0                      
system.cpu.ISSUE:FloatCmp_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.ISSUE:FloatCmp_delay.max_value            0                      
system.cpu.ISSUE:FloatCmp_delay.end_dist

system.cpu.ISSUE:FloatCvt_delay.start_dist                     # cycles from operands ready to issue
system.cpu.ISSUE:FloatCvt_delay.samples             0                      
system.cpu.ISSUE:FloatCvt_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.ISSUE:FloatCvt_delay.max_value            0                      
system.cpu.ISSUE:FloatCvt_delay.end_dist

system.cpu.ISSUE:FloatMult_delay.start_dist                     # cycles from operands ready to issue
system.cpu.ISSUE:FloatMult_delay.samples            0                      
system.cpu.ISSUE:FloatMult_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.ISSUE:FloatMult_delay.max_value            0                      
system.cpu.ISSUE:FloatMult_delay.end_dist

system.cpu.ISSUE:FloatDiv_delay.start_dist                     # cycles from operands ready to issue
system.cpu.ISSUE:FloatDiv_delay.samples            62                      
system.cpu.ISSUE:FloatDiv_delay.min_value            0                      
                               0           62  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu.ISSUE:FloatDiv_delay.max_value            1                      
system.cpu.ISSUE:FloatDiv_delay.end_dist

system.cpu.ISSUE:FloatSqrt_delay.start_dist                     # cycles from operands ready to issue
system.cpu.ISSUE:FloatSqrt_delay.samples            0                      
system.cpu.ISSUE:FloatSqrt_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.ISSUE:FloatSqrt_delay.max_value            0                      
system.cpu.ISSUE:FloatSqrt_delay.end_dist

system.cpu.ISSUE:MemRead_delay.start_dist                      # cycles from operands ready to issue
system.cpu.ISSUE:MemRead_delay.samples       25583395                      
system.cpu.ISSUE:MemRead_delay.min_value            0                      
                               0     23268099   9095.00%   9095.00%
                               2      1599928    625.38%   9720.38%
                               4       383137    149.76%   9870.14%
                               6       143071     55.92%   9926.06%
                               8        85147     33.28%   9959.34%
                              10        39833     15.57%   9974.91%
                              12        20000      7.82%   9982.73%
                              14        14219      5.56%   9988.29%
                              16         6280      2.45%   9990.74%
                              18         2911      1.14%   9991.88%
                              20         1234      0.48%   9992.36%
                              22         1935      0.76%   9993.12%
                              24         1232      0.48%   9993.60%
                              26          524      0.20%   9993.81%
                              28         1565      0.61%   9994.42%
                              30         1179      0.46%   9994.88%
                              32          961      0.38%   9995.25%
                              34         1341      0.52%   9995.78%
                              36          920      0.36%   9996.14%
                              38          836      0.33%   9996.47%
                              40          870      0.34%   9996.81%
                              42          602      0.24%   9997.04%
                              44          327      0.13%   9997.17%
                              46          127      0.05%   9997.22%
                              48          106      0.04%   9997.26%
                              50           81      0.03%   9997.29%
                              52           44      0.02%   9997.31%
                              54           42      0.02%   9997.32%
                              56           40      0.02%   9997.34%
                              58           32      0.01%   9997.35%
                              60           34      0.01%   9997.37%
                              62           37      0.01%   9997.38%
                              64           79      0.03%   9997.41%
                              66           69      0.03%   9997.44%
                              68           48      0.02%   9997.46%
                              70           31      0.01%   9997.47%
                              72           55      0.02%   9997.49%
                              74           78      0.03%   9997.52%
                              76          117      0.05%   9997.57%
                              78          284      0.11%   9997.68%
                              80          414      0.16%   9997.84%
                              82          444      0.17%   9998.01%
                              84          283      0.11%   9998.12%
                              86          273      0.11%   9998.23%
                              88          242      0.09%   9998.33%
                              90           53      0.02%   9998.35%
                              92           95      0.04%   9998.38%
                              94          274      0.11%   9998.49%
                              96          103      0.04%   9998.53%
                              98          913      0.36%   9998.89%
system.cpu.ISSUE:MemRead_delay.overflows         2846                      
system.cpu.ISSUE:MemRead_delay.max_value          949                      
system.cpu.ISSUE:MemRead_delay.end_dist

system.cpu.ISSUE:MemWrite_delay.start_dist                     # cycles from operands ready to issue
system.cpu.ISSUE:MemWrite_delay.samples      16444285                      
system.cpu.ISSUE:MemWrite_delay.min_value            0                      
                               0     15208532   9248.52%   9248.52%
                               2       922225    560.82%   9809.34%
                               4       208178    126.60%   9935.94%
                               6        66164     40.24%   9976.17%
                               8        21787     13.25%   9989.42%
                              10         6991      4.25%   9993.67%
                              12         3998      2.43%   9996.10%
                              14         1606      0.98%   9997.08%
                              16         3111      1.89%   9998.97%
                              18         1115      0.68%   9999.65%
                              20           56      0.03%   9999.68%
                              22           68      0.04%   9999.72%
                              24           72      0.04%   9999.77%
                              26           40      0.02%   9999.79%
                              28           23      0.01%   9999.81%
                              30           13      0.01%   9999.81%
                              32           24      0.01%   9999.83%
                              34           33      0.02%   9999.85%
                              36           14      0.01%   9999.86%
                              38            2      0.00%   9999.86%
                              40            9      0.01%   9999.86%
                              42            5      0.00%   9999.87%
                              44           11      0.01%   9999.87%
                              46            4      0.00%   9999.88%
                              48            3      0.00%   9999.88%
                              50            3      0.00%   9999.88%
                              52            0      0.00%   9999.88%
                              54            0      0.00%   9999.88%
                              56            1      0.00%   9999.88%
                              58            2      0.00%   9999.88%
                              60            2      0.00%   9999.88%
                              62            1      0.00%   9999.88%
                              64            1      0.00%   9999.88%
                              66            1      0.00%   9999.88%
                              68            3      0.00%   9999.89%
                              70            0      0.00%   9999.89%
                              72            0      0.00%   9999.89%
                              74            2      0.00%   9999.89%
                              76            0      0.00%   9999.89%
                              78            5      0.00%   9999.89%
                              80            0      0.00%   9999.89%
                              82            3      0.00%   9999.89%
                              84            1      0.00%   9999.89%
                              86            9      0.01%   9999.90%
                              88            2      0.00%   9999.90%
                              90            2      0.00%   9999.90%
                              92            8      0.00%   9999.91%
                              94            9      0.01%   9999.91%
                              96            2      0.00%   9999.91%
                              98            0      0.00%   9999.91%
system.cpu.ISSUE:MemWrite_delay.overflows          144                      
system.cpu.ISSUE:MemWrite_delay.max_value          948                      
system.cpu.ISSUE:MemWrite_delay.end_dist

system.cpu.ISSUE:IprAccess_delay.start_dist                     # cycles from operands ready to issue
system.cpu.ISSUE:IprAccess_delay.samples      1237369                      
system.cpu.ISSUE:IprAccess_delay.min_value            0                      
                               0       384804   3109.86%   3109.86%
                               2       251677   2033.97%   5143.83%
                               4       253334   2047.36%   7191.19%
                               6        57216    462.40%   7653.59%
                               8        38440    310.66%   7964.25%
                              10       183882   1486.07%   9450.32%
                              12        25916    209.44%   9659.76%
                              14         7367     59.54%   9719.30%
                              16         6653     53.77%   9773.07%
                              18         4226     34.15%   9807.22%
                              20         8583     69.36%   9876.58%
                              22         4402     35.58%   9912.16%
                              24         3001     24.25%   9936.41%
                              26         7445     60.17%   9996.58%
                              28           95      0.77%   9997.35%
                              30           78      0.63%   9997.98%
                              32           87      0.70%   9998.68%
                              34           77      0.62%   9999.30%
                              36            3      0.02%   9999.33%
                              38            7      0.06%   9999.39%
                              40           76      0.61%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu.ISSUE:IprAccess_delay.max_value           41                      
system.cpu.ISSUE:IprAccess_delay.end_dist

system.cpu.ISSUE:InstPrefetch_delay.start_dist                     # cycles from operands ready to issue
system.cpu.ISSUE:InstPrefetch_delay.samples            0                      
system.cpu.ISSUE:InstPrefetch_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu.ISSUE:InstPrefetch_delay.max_value            0                      
system.cpu.ISSUE:InstPrefetch_delay.end_dist

system.cpu.ISSUE:FU_type_0                  813093438                       # Type of FU issued
system.cpu.ISSUE:FU_type_0.start_dist
                          (null)         6962      0.00%            # Type of FU issued
                          IntAlu    791969350     97.40%            # Type of FU issued
                         IntMult        69630      0.01%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd         9257      0.00%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv           62      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead     12376480      1.52%            # Type of FU issued
                        MemWrite      7424328      0.91%            # Type of FU issued
                       IprAccess      1237369      0.15%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu.ISSUE:FU_type_0.end_dist
system.cpu.ISSUE:IQ_0:fu_full.start_dist
                          (null)            0      0.00%           
                          IntAlu   9807863591     99.92%           
                         IntMult            0      0.00%           
                          IntDiv            0      0.00%           
                        FloatAdd            0      0.00%           
                        FloatCmp            0      0.00%           
                        FloatCvt            0      0.00%           
                       FloatMult            0      0.00%           
                        FloatDiv            0      0.00%           
                       FloatSqrt            0      0.00%           
                         MemRead      2170189      0.02%           
                        MemWrite       291525      0.00%           
                       IprAccess      5065012      0.05%           
                    InstPrefetch            0      0.00%           
system.cpu.ISSUE:IQ_0:fu_full.end_dist
system.cpu.ISSUE:MSIPC                       0.001656                       # Misspec issue rate
system.cpu.ISSUE:addr_loads                    136752                       # number of invalid-address loads
system.cpu.ISSUE:addr_swpfs                      4779                       # number of invalid-address SW prefetches
system.cpu.ISSUE:branches                   253307738                       # Number of branches issued
system.cpu.ISSUE:count                      793082065                       # number of insts issued
system.cpu.ISSUE:fu_busy_cnt               9815390317                       # FU busy when requested
system.cpu.ISSUE:fu_busy_rate               12.376261                       # FU busy rate (busy events/executed inst)
system.cpu.ISSUE:fu_full.start_dist
                          (null)            0      0.00%            # attempts to use FU when none available
                          IntAlu   9807863591     99.92%            # attempts to use FU when none available
                         IntMult            0      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead      2170189      0.02%            # attempts to use FU when none available
                        MemWrite       291525      0.00%            # attempts to use FU when none available
                       IprAccess      5065012      0.05%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu.ISSUE:fu_full.end_dist
system.cpu.ISSUE:issued_per_cycle           147304044                       # Number of insts issued each cycle
system.cpu.ISSUE:issued_per_cycle.start_dist
                               0      2612615      1.77%            # Number of insts issued each cycle
                               1      6458362      4.38%            # Number of insts issued each cycle
                               2      3452969      2.34%            # Number of insts issued each cycle
                               3      2966575      2.01%            # Number of insts issued each cycle
                               4      1793304      1.22%            # Number of insts issued each cycle
                               5      2405349      1.63%            # Number of insts issued each cycle
                               6    123444898     83.80%            # Number of insts issued each cycle
                               7      1862430      1.26%            # Number of insts issued each cycle
                               8      2307542      1.57%            # Number of insts issued each cycle
system.cpu.ISSUE:issued_per_cycle.end_dist
system.cpu.ISSUE:loads                       13206915                       # number of load insts issued
system.cpu.ISSUE:lsq_inv_rate                       0                       # Early LSQ issues per cycle
system.cpu.ISSUE:lsq_invert                         0                       # Number of times LSQ instruction issued early
system.cpu.ISSUE:misspec_cnt                 11923397                       # Number of misspeculated insts issued
system.cpu.ISSUE:nop                         11177450                       # number of nop insts issued
system.cpu.ISSUE:op_count                   813630720                       # number of insts issued
system.cpu.ISSUE:op_rate                     0.113006                       # Operation issue rate
system.cpu.ISSUE:rate                        0.110152                       # Inst issue rate
system.cpu.ISSUE:refs                        21689590                       # number of memory reference insts issued
system.cpu.ISSUE:stores                       8482675                       # Number of stores issued
system.cpu.ISSUE:swp                           218124                       # number of swp insts issued
system.cpu.ISSUE:unissued_cause.start_dist
                          (null)            0      0.00%            # Reason ready instruction not issued
                          IntAlu   9807863591     99.92%            # Reason ready instruction not issued
                         IntMult            0      0.00%            # Reason ready instruction not issued
                          IntDiv            0      0.00%            # Reason ready instruction not issued
                        FloatAdd            0      0.00%            # Reason ready instruction not issued
                        FloatCmp            0      0.00%            # Reason ready instruction not issued
                        FloatCvt            0      0.00%            # Reason ready instruction not issued
                       FloatMult            0      0.00%            # Reason ready instruction not issued
                        FloatDiv            0      0.00%            # Reason ready instruction not issued
                       FloatSqrt            0      0.00%            # Reason ready instruction not issued
                         MemRead      2170189      0.02%            # Reason ready instruction not issued
                        MemWrite          697      0.00%            # Reason ready instruction not issued
                       IprAccess      5065012      0.05%            # Reason ready instruction not issued
                    InstPrefetch            0      0.00%            # Reason ready instruction not issued
                  DCache_Blocked       228682      0.00%            # Reason ready instruction not issued
                       Too_Young            0      0.00%            # Reason ready instruction not issued
system.cpu.ISSUE:unissued_cause.end_dist
system.cpu.LSQ:RQ:rdy_inst                   24423158                       # Number of ready instructions (cum)
system.cpu.LSQ:RQ:rdy_inst_dist_0_mean       0.003392                       # standard deviation of ready rate
system.cpu.LSQ:RQ:rdy_inst_dist_0_stdev      0.123085                       # standard deviation of ready rate
**Ignore: system.cpu.LSQ:RQ:rdy_inst_dist_0_TOT   7199893258                       # standard deviation of ready rate
system.cpu.LSQ:RQ:rdy_rate                   0.003392                       # Number of ready insts per cycle
system.cpu.LSQ:RQ:rdy_x_count                20402392                       # number of insts that become ready (cum)
system.cpu.LSQ:RQ:rdy_x_max                        32                       # largest number of insts that become ready
system.cpu.LSQ:RQ:rdy_x_rate                 0.002834                       # number of insts that become ready per cycle
system.cpu.LSQ:avg_residency                 1.572245                       # Average IQ residency
system.cpu.LSQ:blocked_loads                 47048956                       # number of ready loads not issued due to memory disambiguation
system.cpu.LSQ:cum_num_insts               1246919707                       # Total occupancy
system.cpu.LSQ:current_count                        0                       # Occupancy this cycle
system.cpu.LSQ:empty_count                 7144254473                       # Number of empty cycles
system.cpu.LSQ:empty_rate                   99.227228                       # Fraction of cycles empty
system.cpu.LSQ:forw_loads                         334                       # number of loads forwarded via LSQ
system.cpu.LSQ:full_count                           0                       # Number of full cycles
system.cpu.LSQ:full_rate                            0                       # Fraction of cycles full
system.cpu.LSQ:occ_dist_0.start_dist                           # IQ Occupancy per cycle
system.cpu.LSQ:occ_dist_0.samples          7199893258                      
system.cpu.LSQ:occ_dist_0.min_value                 0                      
                               0   7147664264              9927.46%
                               2      4500148              9933.71%
                               4      3258243              9938.23%
                               6      2143418              9941.21%
                               8      1893388              9943.84%
                              10      1220078              9945.54%
                              12      1005707              9946.93%
                              14       956239              9948.26%
                              16       870814              9949.47%
                              18       615798              9950.33%
                              20       530567              9951.06%
                              22       498559              9951.75%
                              24       480483              9952.42%
                              26       495621              9953.11%
                              28       785525              9954.20%
                              30       883025              9955.43%
                              32     32091381             10000.00%
system.cpu.LSQ:occ_dist_0.max_value                32                      
system.cpu.LSQ:occ_dist_0.end_dist

system.cpu.LSQ:occ_rate                      0.173186                       # Average occupancy
system.cpu.LSQ:peak_occupancy                      32                       # Peak IQ occupancy
system.cpu.REG:fp:full                              0                       # number of cycles where there were no FP registers
system.cpu.REG:fp:occ                         4113489                       # Cumulative count of FP register usage
system.cpu.REG:fp:occ_rate                          0                       # Average FP register usage
system.cpu.REG:int:full                             0                       # number of cycles where there were no INT registers
system.cpu.REG:int:occ                    28423860936                       # Cumulative count of INT register usage
system.cpu.REG:int:occ_rate                         4                       # Average INT register usage
system.cpu.ROB:cap_events                           0                       # number of cycles where ROB cap was active
system.cpu.ROB:cap_inst                             0                       # number of instructions held up by ROB cap
system.cpu.ROB:current_count                        0                       # Current ROB occupancy
system.cpu.ROB:full_count                     3196408                       # number of cycles where ROB was full
system.cpu.ROB:full_rate                     0.000444                       # ROB full per cycle
system.cpu.ROB:occ_dist_0.start_dist                           # ROB Occupancy per cycle
system.cpu.ROB:occ_dist_0.samples          7199893258                      
system.cpu.ROB:occ_dist_0.min_value                 0                      
                               0   7012109058              9739.18%
                               2      2333009              9742.43%
                               4      1261618              9744.18%
                               6      1809486              9746.69%
                               8      2505642              9750.17%
                              10      1556377              9752.33%
                              12      1648581              9754.62%
                              14      1214797              9756.31%
                              16       958961              9757.64%
                              18      1028187              9759.07%
                              20      1094102              9760.59%
                              22       929019              9761.88%
                              24       618932              9762.74%
                              26       547594              9763.50%
                              28       866988              9764.70%
                              30       611923              9765.55%
                              32       429796              9766.15%
                              34       439507              9766.76%
                              36       503866              9767.46%
                              38       457828              9768.10%
                              40       344297              9768.57%
                              42       402182              9769.13%
                              44       368425              9769.65%
                              46       386495              9770.18%
                              48       318291              9770.62%
                              50       360554              9771.12%
                              52       324593              9771.58%
                              54       296338              9771.99%
                              56       243450              9772.33%
                              58       253979              9772.68%
                              60       297519              9773.09%
                              62       279391              9773.48%
                              64       251228              9773.83%
                              66       255051              9774.18%
                              68       264508              9774.55%
                              70       291941              9774.96%
                              72       306571              9775.38%
                              74       298000              9775.80%
                              76       341806              9776.27%
                              78       360884              9776.77%
                              80       316156              9777.21%
                              82       375337              9777.73%
                              84       383359              9778.26%
                              86       227043              9778.58%
                              88       244786              9778.92%
                              90       199407              9779.20%
                              92       185246              9779.45%
                              94       182640              9779.71%
                              96       298420              9780.12%
                              98       207064              9780.41%
                             100      3709136              9785.56%
                             102       356924              9786.06%
                             104       405572              9786.62%
                             106       406167              9787.18%
                             108       193516              9787.45%
                             110       169100              9787.69%
                             112       188880              9787.95%
                             114       257887              9788.31%
                             116       134709              9788.50%
                             118       121452              9788.66%
                             120        95210              9788.80%
                             122       114996              9788.96%
                             124       125102              9789.13%
                             126       135003              9789.32%
                             128       253030              9789.67%
                             130       123241              9789.84%
                             132       625559              9790.71%
                             134       116852              9790.87%
                             136       118230              9791.04%
                             138        94947              9791.17%
                             140        99137              9791.30%
                             142        99082              9791.44%
                             144        99278              9791.58%
                             146       167493              9791.81%
                             148        84868              9791.93%
                             150        81617              9792.04%
                             152       130054              9792.22%
                             154       175203              9792.47%
                             156        95430              9792.60%
                             158        77060              9792.71%
                             160        90340              9792.83%
                             162        68993              9792.93%
                             164        84274              9793.05%
                             166        88690              9793.17%
                             168        58983              9793.25%
                             170        50919              9793.32%
                             172        41811              9793.38%
                             174        43331              9793.44%
                             176        70255              9793.54%
                             178        44984              9793.60%
                             180        43898              9793.66%
                             182        46842              9793.73%
                             184        47564              9793.79%
                             186        46085              9793.86%
                             188       225024              9794.17%
                             190       431372              9794.77%
                             192     20346823              9823.03%
                             194        62941              9823.12%
                             196        51964              9823.19%
                             198        50219              9823.26%
                             200       294718              9823.67%
                             202        38986              9823.72%
                             204        65771              9823.81%
                             206        47430              9823.88%
                             208        38128              9823.93%
                             210        44380              9823.99%
                             212        64611              9824.08%
                             214        33756              9824.13%
                             216        48660              9824.20%
                             218        35270              9824.25%
                             220        44251              9824.31%
                             222        37480              9824.36%
                             224        40246              9824.42%
                             226        28693              9824.45%
                             228        46527              9824.52%
                             230        41614              9824.58%
                             232        23844              9824.61%
                             234        31088              9824.65%
                             236        34207              9824.70%
                             238        31139              9824.74%
                             240        23533              9824.78%
                             242        18628              9824.80%
                             244        19723              9824.83%
                             246        33827              9824.88%
                             248        20452              9824.91%
                             250        17430              9824.93%
                             252        41669              9824.99%
                             254        23983              9825.02%
                             256        83170              9825.14%
                             258       127779              9825.31%
                             260        27971              9825.35%
                             262        12191              9825.37%
                             264        18761              9825.40%
                             266        16939              9825.42%
                             268        22872              9825.45%
                             270     30582021              9867.93%
                             272     54021604              9942.96%
                             274     29015469              9983.26%
                             276      4019056              9988.84%
                             278      2373341              9992.14%
                             280        21360              9992.17%
                             282        18855              9992.19%
                             284        21631              9992.22%
                             286        39175              9992.28%
                             288        36033              9992.33%
                             290        16356              9992.35%
                             292        14217              9992.37%
                             294        18239              9992.39%
                             296        14123              9992.41%
                             298        15046              9992.43%
                             300        22859              9992.47%
                             302        12913              9992.48%
                             304        25045              9992.52%
                             306        12936              9992.54%
                             308        11098              9992.55%
                             310        11138              9992.57%
                             312        14382              9992.59%
                             314        11067              9992.60%
                             316        31122              9992.65%
                             318        12090              9992.66%
                             320        27644              9992.70%
                             322        13224              9992.72%
                             324        19552              9992.75%
                             326        11312              9992.76%
                             328        14148              9992.78%
                             330        11775              9992.80%
                             332        11806              9992.82%
                             334        14439              9992.84%
                             336        12471              9992.85%
                             338        11357              9992.87%
                             340        13095              9992.89%
                             342        15015              9992.91%
                             344        15014              9992.93%
                             346        21769              9992.96%
                             348        20319              9992.99%
                             350        28918              9993.03%
                             352        38826              9993.08%
                             354        26019              9993.12%
                             356        30807              9993.16%
                             358        26022              9993.20%
                             360        42972              9993.26%
                             362        20829              9993.28%
                             364        25765              9993.32%
                             366        13847              9993.34%
                             368        28119              9993.38%
                             370        23999              9993.41%
                             372        37261              9993.46%
                             374        43175              9993.52%
                             376        29732              9993.57%
                             378        16559              9993.59%
                             380        35649              9993.64%
                             382        58846              9993.72%
                             384        37698              9993.77%
                             386       276201              9994.16%
                             388        25512              9994.19%
                             390        33811              9994.24%
                             392        19923              9994.27%
                             394        17388              9994.29%
                             396        27990              9994.33%
                             398       168229              9994.56%
                             400        18576              9994.59%
                             402         7640              9994.60%
                             404        13654              9994.62%
                             406        13274              9994.64%
                             408         9575              9994.65%
                             410         9008              9994.66%
                             412        15918              9994.68%
                             414        15360              9994.71%
                             416        18136              9994.73%
                             418        19900              9994.76%
                             420        13877              9994.78%
                             422         7271              9994.79%
                             424        16482              9994.81%
                             426        11185              9994.83%
                             428         6816              9994.84%
                             430         8132              9994.85%
                             432         7849              9994.86%
                             434        11029              9994.87%
                             436         8079              9994.88%
                             438         8349              9994.90%
                             440         8013              9994.91%
                             442        10205              9994.92%
                             444         6491              9994.93%
                             446        20631              9994.96%
                             448        17397              9994.98%
                             450        20561              9995.01%
                             452         8053              9995.02%
                             454         5820              9995.03%
                             456        17622              9995.06%
                             458        11157              9995.07%
                             460        10997              9995.09%
                             462         6098              9995.09%
                             464         8726              9995.11%
                             466         6701              9995.12%
                             468         9064              9995.13%
                             470         5744              9995.14%
                             472         4980              9995.14%
                             474         2636              9995.15%
                             476         4266              9995.15%
                             478         4564              9995.16%
                             480         4165              9995.17%
                             482         3549              9995.17%
                             484         5450              9995.18%
                             486         5289              9995.18%
                             488         5124              9995.19%
                             490         6278              9995.20%
                             492         7671              9995.21%
                             494         8228              9995.22%
                             496        14833              9995.24%
                             498        23243              9995.28%
                             500        22161              9995.31%
                             502        22989              9995.34%
                             504        35352              9995.39%
                             506        29131              9995.43%
                             508        23093              9995.46%
                             510        64146              9995.55%
                             512      3204501             10000.00%
system.cpu.ROB:occ_dist_0.max_value               512                      
system.cpu.ROB:occ_dist_0.end_dist

system.cpu.ROB:occ_rate                      5.811441                       # ROB occupancy rate
system.cpu.ROB:occupancy                  41841758349                       # system.cpu.ROB occupancy (cumulative)
system.cpu.SB:RQ:rdy_inst                     8554512                       # Number of ready instructions (cum)
system.cpu.SB:RQ:rdy_inst_dist_0_mean        0.001188                       # standard deviation of ready rate
system.cpu.SB:RQ:rdy_inst_dist_0_stdev       0.067612                       # standard deviation of ready rate
**Ignore: system.cpu.SB:RQ:rdy_inst_dist_0_TOT   7199893258                       # standard deviation of ready rate
system.cpu.SB:RQ:rdy_rate                    0.001188                       # Number of ready insts per cycle
system.cpu.SB:RQ:rdy_x_count                  7416769                       # number of insts that become ready (cum)
system.cpu.SB:RQ:rdy_x_max                         16                       # largest number of insts that become ready
system.cpu.SB:RQ:rdy_x_rate                  0.001030                       # number of insts that become ready per cycle
system.cpu.SB:full_count                      3651437                       # store buffer full events (cumulative)
system.cpu.SB:full_rate                      0.000507                       # store buffer full rate
system.cpu.SB:occ_rate                       0.026532                       # store buffer occupancy rate
system.cpu.SB:occupancy                     191025949                       # store buffer occupancy (cumulative)
system.cpu.SB:write_barrier_pending_cycles        40419                       # number of cycles write barriers were pending
system.cpu.SB:write_barriers                     6788                       # number of write barrier operations
system.cpu.WB:consumers                     565705283                       # num instructions consuming a value
system.cpu.WB:count                         811155948                       # cumulative count of insts written-back
system.cpu.WB:fanout                         0.973200                       # average fanout of values written-back
system.cpu.WB:penalized                             0                       # number of instrctions required to write to 'other' IQ
system.cpu.WB:penalized_rate                        0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.WB:pred_error.start_dist                            # error in predicted writeback times
system.cpu.WB:pred_error.samples            811155948                      
system.cpu.WB:pred_error.min_value                145                      
                             -10            0      0.00%      0.00%
                              -9            0      0.00%      0.00%
                              -8            0      0.00%      0.00%
                              -7            0      0.00%      0.00%
                              -6            0      0.00%      0.00%
                              -5            0      0.00%      0.00%
                              -4            0      0.00%      0.00%
                              -3            0      0.00%      0.00%
                              -2            0      0.00%      0.00%
                              -1            0      0.00%      0.00%
                               0            0      0.00%      0.00%
                               1            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               3            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               5            0      0.00%      0.00%
                               6            0      0.00%      0.00%
                               7            0      0.00%      0.00%
                               8            0      0.00%      0.00%
                               9            0      0.00%      0.00%
                              10            0      0.00%      0.00%
                              11            0      0.00%      0.00%
                              12            0      0.00%      0.00%
                              13            0      0.00%      0.00%
                              14            0      0.00%      0.00%
                              15            0      0.00%      0.00%
                              16            0      0.00%      0.00%
                              17            0      0.00%      0.00%
                              18            0      0.00%      0.00%
                              19            0      0.00%      0.00%
                              20            0      0.00%      0.00%
                              21            0      0.00%      0.00%
                              22            0      0.00%      0.00%
                              23            0      0.00%      0.00%
                              24            0      0.00%      0.00%
                              25            0      0.00%      0.00%
                              26            0      0.00%      0.00%
                              27            0      0.00%      0.00%
                              28            0      0.00%      0.00%
                              29            0      0.00%      0.00%
                              30            0      0.00%      0.00%
                              31            0      0.00%      0.00%
                              32            0      0.00%      0.00%
                              33            0      0.00%      0.00%
                              34            0      0.00%      0.00%
                              35            0      0.00%      0.00%
                              36            0      0.00%      0.00%
                              37            0      0.00%      0.00%
                              38            0      0.00%      0.00%
                              39            0      0.00%      0.00%
                              40            0      0.00%      0.00%
                              41            0      0.00%      0.00%
                              42            0      0.00%      0.00%
                              43            0      0.00%      0.00%
                              44            0      0.00%      0.00%
                              45            0      0.00%      0.00%
                              46            0      0.00%      0.00%
                              47            0      0.00%      0.00%
                              48            0      0.00%      0.00%
                              49            0      0.00%      0.00%
                              50            0      0.00%      0.00%
                              51            0      0.00%      0.00%
                              52            0      0.00%      0.00%
                              53            0      0.00%      0.00%
                              54            0      0.00%      0.00%
                              55            0      0.00%      0.00%
                              56            0      0.00%      0.00%
                              57            0      0.00%      0.00%
                              58            0      0.00%      0.00%
                              59            0      0.00%      0.00%
                              60            0      0.00%      0.00%
                              61            0      0.00%      0.00%
                              62            0      0.00%      0.00%
                              63            0      0.00%      0.00%
                              64            0      0.00%      0.00%
                              65            0      0.00%      0.00%
                              66            0      0.00%      0.00%
                              67            0      0.00%      0.00%
                              68            0      0.00%      0.00%
                              69            0      0.00%      0.00%
                              70            0      0.00%      0.00%
                              71            0      0.00%      0.00%
                              72            0      0.00%      0.00%
                              73            0      0.00%      0.00%
                              74            0      0.00%      0.00%
                              75            0      0.00%      0.00%
                              76            0      0.00%      0.00%
                              77            0      0.00%      0.00%
                              78            0      0.00%      0.00%
                              79            0      0.00%      0.00%
                              80            0      0.00%      0.00%
                              81            0      0.00%      0.00%
                              82            0      0.00%      0.00%
                              83            0      0.00%      0.00%
                              84            0      0.00%      0.00%
                              85            0      0.00%      0.00%
                              86            0      0.00%      0.00%
                              87            0      0.00%      0.00%
                              88            0      0.00%      0.00%
                              89            0      0.00%      0.00%
                              90            0      0.00%      0.00%
                              91            0      0.00%      0.00%
                              92            0      0.00%      0.00%
                              93            0      0.00%      0.00%
                              94            0      0.00%      0.00%
                              95            0      0.00%      0.00%
                              96            0      0.00%      0.00%
                              97            0      0.00%      0.00%
                              98            0      0.00%      0.00%
                              99            0      0.00%      0.00%
                             100            0      0.00%      0.00%
system.cpu.WB:pred_error.overflows          811155948                      
system.cpu.WB:pred_error.max_value         7199893255                      
system.cpu.WB:pred_error.end_dist

system.cpu.WB:producers                     550544651                       # num instructions producing a value
system.cpu.WB:rate                           0.112662                       # insts written-back per cycle
system.cpu.branch_pred.btb_accuracy          0.999976                       # fraction of BTB targets correct
system.cpu.branch_pred.btb_correct          245581402                       # num correct BTB predictions
system.cpu.branch_pred.btb_hit_rate          0.975615                       # BTB hit ratio
system.cpu.branch_pred.btb_hits             251689028                       # Number of BTB hits
system.cpu.branch_pred.btb_lookups          257979839                       # Number of BTB lookups
system.cpu.branch_pred.cond_correct         247478993                       # num correct dir predictions
system.cpu.branch_pred.cond_predicted       247720789                       # num committed conditional branches
system.cpu.branch_pred.dir_accuracy          0.999024                       # fraction of predictions correct
system.cpu.branch_pred.lookup_rate           0.038659                       # Rate of bpred lookups
system.cpu.branch_pred.lookups              278341004                       # num BP lookups
system.cpu.branch_pred.ras_accuracy          0.914475                       # fraction of RAS targets correct
system.cpu.branch_pred.ras_correct             804409                       # num correct RAS predictions
system.cpu.branch_pred.used_btb             245587402                       # num committed branches using target from BTB
system.cpu.branch_pred.used_ras                879640                       # num returns predicted using RAS
system.cpu.dcache.avg_blocked_cycles_no_mshrs     9.653284                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles_no_targets    50.659655                       # average number of cycles each access was blocked
system.cpu.dcache.avg_refs                   9.483730                       # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs               5131                       # number of cycles access was blocked
system.cpu.dcache.blocked_no_targets             1854                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs        49531                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_targets        93923                       # number of cycles access was blocked
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.demand_accesses            19140555                       # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency    57.534103                       # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency    49.008646                       # average overall mshr miss latency
system.cpu.dcache.demand_hits                14737432                       # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency       253329733                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate           0.230042                       # miss rate for demand accesses
system.cpu.dcache.demand_misses               4403123                       # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits            3026156                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency     67483288                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate      0.071940                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses          1376967                       # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.overall_accesses           19353264                       # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency    56.720401                       # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency    47.118326                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency   147.014287                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_hits               14768187                       # number of overall hits
system.cpu.dcache.overall_miss_latency      260067408                       # number of overall miss cycles
system.cpu.dcache.overall_miss_rate          0.236915                       # miss rate for overall accesses
system.cpu.dcache.overall_misses              4585077                       # number of overall misses
system.cpu.dcache.overall_mshr_hits           3027860                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency     73373458                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate     0.080463                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses         1557217                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency      2438673                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses        16588                       # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.dcache.read_accesses              11733438                       # number of read accesses(hits+misses)
system.cpu.dcache.read_avg_miss_latency     38.747277                       # average read miss latency
system.cpu.dcache.read_avg_mshr_miss_latency    42.693095                       # average read mshr miss latency
system.cpu.dcache.read_avg_mshr_uncacheable_latency    92.612168                       # average read mshr uncacheable latency
system.cpu.dcache.read_hits                   9654573                       # number of read hits
system.cpu.dcache.read_miss_latency          80550357                       # number of read miss cycles
system.cpu.dcache.read_miss_rate             0.177174                       # miss rate for read accesses
system.cpu.dcache.read_misses                 2078865                       # number of read misses
system.cpu.dcache.read_mshr_hits              1056839                       # number of read MSHR hits
system.cpu.dcache.read_mshr_miss_latency     43633453                       # number of read MSHR miss cycles
system.cpu.dcache.read_mshr_miss_rate        0.087104                       # mshr miss rate for read accesses
system.cpu.dcache.read_mshr_misses            1022026                       # number of read MSHR misses
system.cpu.dcache.read_mshr_uncacheable          6936                       # number of read MSHR uncacheable
system.cpu.dcache.read_mshr_uncacheable_latency       642358                       # number of read MSHR uncacheable cycles
system.cpu.dcache.replacements                1556701                       # number of replacements
system.cpu.dcache.sampled_refs                1557213                       # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.swpf_accesses                212709                       # number of swpf accesses(hits+misses)
system.cpu.dcache.swpf_avg_miss_latency     37.029551                       # average swpf miss latency
system.cpu.dcache.swpf_avg_mshr_miss_latency    32.677781                       # average swpf mshr miss latency
system.cpu.dcache.swpf_hits                     30755                       # number of swpf hits
system.cpu.dcache.swpf_miss_latency           6737675                       # number of swpf miss cycles
system.cpu.dcache.swpf_miss_rate             0.855413                       # miss rate for swpf accesses
system.cpu.dcache.swpf_misses                  181954                       # number of swpf misses
system.cpu.dcache.swpf_mshr_hits                 1704                       # number of swpf MSHR hits
system.cpu.dcache.swpf_mshr_miss_latency      5890170                       # number of swpf MSHR miss cycles
system.cpu.dcache.swpf_mshr_miss_rate        0.847402                       # mshr miss rate for swpf accesses
system.cpu.dcache.swpf_mshr_misses             180250                       # number of swpf MSHR misses
system.cpu.dcache.tagsinuse                511.995974                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 14768187                       # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle                  67351                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.write_accesses              7407117                       # number of write accesses(hits+misses)
system.cpu.dcache.write_avg_miss_latency    74.337434                       # average write miss latency
system.cpu.dcache.write_avg_mshr_miss_latency    67.193801                       # average write mshr miss latency
system.cpu.dcache.write_avg_mshr_uncacheable_latency   186.108061                       # average write mshr uncacheable latency
system.cpu.dcache.write_hits                  5082859                       # number of write hits
system.cpu.dcache.write_miss_latency        172779376                       # number of write miss cycles
system.cpu.dcache.write_miss_rate            0.313787                       # miss rate for write accesses
system.cpu.dcache.write_misses                2324258                       # number of write misses
system.cpu.dcache.write_mshr_hits             1969317                       # number of write MSHR hits
system.cpu.dcache.write_mshr_miss_latency     23849835                       # number of write MSHR miss cycles
system.cpu.dcache.write_mshr_miss_rate       0.047919                       # mshr miss rate for write accesses
system.cpu.dcache.write_mshr_misses            354941                       # number of write MSHR misses
system.cpu.dcache.write_mshr_uncacheable         9652                       # number of write MSHR uncacheable
system.cpu.dcache.write_mshr_uncacheable_latency      1796315                       # number of write MSHR uncacheable cycles
system.cpu.dcache.writebacks                   565309                       # number of writebacks
system.cpu.dtb.accesses                       6080475                       # DTB accesses
system.cpu.dtb.acv                             338402                       # DTB access violations
system.cpu.dtb.hits                          33506635                       # DTB hits
system.cpu.dtb.misses                         2642777                       # DTB misses
system.cpu.dtb.read_accesses                  4110061                       # DTB read accesses
system.cpu.dtb.read_acv                        142110                       # DTB read access violations
system.cpu.dtb.read_hits                     20552261                       # DTB read hits
system.cpu.dtb.read_misses                    1670366                       # DTB read misses
system.cpu.dtb.write_accesses                 1970414                       # DTB write accesses
system.cpu.dtb.write_acv                       196292                       # DTB write access violations
system.cpu.dtb.write_hits                    12954374                       # DTB write hits
system.cpu.dtb.write_misses                    972411                       # DTB write misses
system.cpu.floss.fetch_0.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
system.cpu.floss.fetch_0.end_dist
system.cpu.floss.icache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu.floss.icache_0.end_dist
system.cpu.floss.iq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
system.cpu.floss.iq_full_0.end_dist
system.cpu.floss.iq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu.floss.iq_full_dcache_0.end_dist
system.cpu.floss.iq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu.floss.iq_full_deps_0.end_dist
system.cpu.floss.iq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu.floss.iq_full_fu_0.end_dist
system.cpu.floss.lsq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
system.cpu.floss.lsq_full_0.end_dist
system.cpu.floss.lsq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu.floss.lsq_full_dcache_0.end_dist
system.cpu.floss.lsq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu.floss.lsq_full_deps_0.end_dist
system.cpu.floss.lsq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu.floss.lsq_full_fu_0.end_dist
system.cpu.floss.qfull_0.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
system.cpu.floss.qfull_0.end_dist
system.cpu.floss.rob_full_0.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
system.cpu.floss.rob_full_0.end_dist
system.cpu.floss.rob_full_dcache_0.start_dist
Hit                                                 0                      
Miss                                                0                      
TLB miss                                            0                      
Bad address                                         0                      
MSHRs full                                          0                      
MSHR targets full                                   0                      
Miss pending                                        0                      
Not issued                                          0                      
Not predicted                                       0                      
Canceled                                            0                      
Dropped                                             0                      
Filtered                                            0                      
No result                                           0                      
Success                                             0                      
Blocked hard prefetch                               0                      
Blocked prefetch                                    0                      
Blocked all                                         0                      
system.cpu.floss.rob_full_dcache_0.end_dist
system.cpu.floss.rob_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu.floss.rob_full_fu_0.end_dist
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.icache.avg_refs                 540.710023                       # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.demand_accesses           573911028                       # number of demand (read+write) accesses
system.cpu.icache.demand_avg_miss_latency    17.445150                       # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency    21.400584                       # average overall mshr miss latency
system.cpu.icache.demand_hits               572731952                       # number of demand (read+write) hits
system.cpu.icache.demand_miss_latency        20569158                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate           0.002054                       # miss rate for demand accesses
system.cpu.icache.demand_misses               1179076                       # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits              40270                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency     24371113                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate      0.001984                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses          1138806                       # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.overall_accesses          573911028                       # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency    17.445150                       # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency    21.400584                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu.icache.overall_hits              572731952                       # number of overall hits
system.cpu.icache.overall_miss_latency       20569158                       # number of overall miss cycles
system.cpu.icache.overall_miss_rate          0.002054                       # miss rate for overall accesses
system.cpu.icache.overall_misses              1179076                       # number of overall misses
system.cpu.icache.overall_mshr_hits             40270                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency     24371113                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate     0.001984                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses         1138806                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.icache.read_accesses             573911028                       # number of read accesses(hits+misses)
system.cpu.icache.read_avg_miss_latency     17.445150                       # average read miss latency
system.cpu.icache.read_avg_mshr_miss_latency    21.400584                       # average read mshr miss latency
system.cpu.icache.read_hits                 572731952                       # number of read hits
system.cpu.icache.read_miss_latency          20569158                       # number of read miss cycles
system.cpu.icache.read_miss_rate             0.002054                       # miss rate for read accesses
system.cpu.icache.read_misses                 1179076                       # number of read misses
system.cpu.icache.read_mshr_hits                40270                       # number of read MSHR hits
system.cpu.icache.read_mshr_miss_latency     24371113                       # number of read MSHR miss cycles
system.cpu.icache.read_mshr_miss_rate        0.001984                       # mshr miss rate for read accesses
system.cpu.icache.read_mshr_misses            1138806                       # number of read MSHR misses
system.cpu.icache.replacements                1058710                       # number of replacements
system.cpu.icache.sampled_refs                1059222                       # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu.icache.tagsinuse                511.612696                       # Cycle average of tags in use
system.cpu.icache.total_refs                572731952                       # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle               26050794                       # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks                        0                       # number of writebacks
system.cpu.iq:RQ:rdy_inst                 10616591848                       # Number of ready instructions (cum)
system.cpu.iq:RQ:rdy_inst_dist_0_mean        1.474549                       # standard deviation of ready rate
system.cpu.iq:RQ:rdy_inst_dist_0_stdev      11.215503                       # standard deviation of ready rate
**Ignore: system.cpu.iq:RQ:rdy_inst_dist_0_TOT   7199893258                       # standard deviation of ready rate
system.cpu.iq:RQ:rdy_rate                    1.474549                       # Number of ready insts per cycle
system.cpu.iq:RQ:rdy_x_count                796531846                       # number of insts that become ready (cum)
system.cpu.iq:RQ:rdy_x_max                        128                       # largest number of insts that become ready
system.cpu.iq:RQ:rdy_x_rate                  0.110631                       # number of insts that become ready per cycle
system.cpu.iq:avg_residency                 44.385912                       # Average IQ residency
system.cpu.iq:cum_num_insts               35201671110                       # Total occupancy
system.cpu.iq:current_count                         0                       # Occupancy this cycle
system.cpu.iq:empty_count                  7018305508                       # Number of empty cycles
system.cpu.iq:empty_rate                    97.477911                       # Fraction of cycles empty
system.cpu.iq:full_count                    121231562                       # Number of full cycles
system.cpu.iq:full_rate                      1.683797                       # Fraction of cycles full
system.cpu.iq:occ_dist_0.start_dist                            # IQ Occupancy per cycle
system.cpu.iq:occ_dist_0.samples           7199893258                      
system.cpu.iq:occ_dist_0.min_value                  0                      
                               0   7021223012              9751.84%
                               2      3500696              9756.71%
                               4      2904741              9760.74%
                               6      2131125              9763.70%
                               8      2673119              9767.41%
                              10      1570650              9769.59%
                              12      1290224              9771.39%
                              14       998260              9772.77%
                              16       808422              9773.90%
                              18       764569              9774.96%
                              20       758099              9776.01%
                              22       777764              9777.09%
                              24       631612              9777.97%
                              26       575004              9778.77%
                              28       612634              9779.62%
                              30       564150              9780.40%
                              32       585211              9781.21%
                              34       592908              9782.04%
                              36       565950              9782.82%
                              38       525054              9783.55%
                              40       489243              9784.23%
                              42       388016              9784.77%
                              44       656556              9785.68%
                              46       322717              9786.13%
                              48       337258              9786.60%
                              50       293094              9787.01%
                              52       296946              9787.42%
                              54       218581              9787.72%
                              56       266966              9788.09%
                              58       211259              9788.39%
                              60       275754              9788.77%
                              62       360490              9789.27%
                              64       271102              9789.65%
                              66       404050              9790.21%
                              68       292563              9790.61%
                              70       165951              9790.84%
                              72       187386              9791.11%
                              74       213048              9791.40%
                              76       128264              9791.58%
                              78        91609              9791.71%
                              80        95302              9791.84%
                              82        91357              9791.97%
                              84       101492              9792.11%
                              86        77029              9792.21%
                              88       257595              9792.57%
                              90       298894              9792.99%
                              92       260640              9793.35%
                              94       336852              9793.82%
                              96      3371712              9798.50%
                              98       315162              9798.94%
                             100       100147              9799.08%
                             102        81005              9799.19%
                             104        86336              9799.31%
                             106       543125              9800.06%
                             108       104008              9800.21%
                             110        73501              9800.31%
                             112        84620              9800.43%
                             114        76631              9800.53%
                             116        67434              9800.63%
                             118        70244              9800.72%
                             120        81731              9800.84%
                             122       155809              9801.05%
                             124       388155              9801.59%
                             126       383796              9802.13%
                             128     19963526              9829.85%
                             130       203662              9830.14%
                             132        20050              9830.17%
                             134        23464              9830.20%
                             136        30188              9830.24%
                             138        32656              9830.28%
                             140        34521              9830.33%
                             142        46059              9830.40%
                             144        29965              9830.44%
                             146        33041              9830.48%
                             148        33773              9830.53%
                             150        33552              9830.58%
                             152        22485              9830.61%
                             154        15889              9830.63%
                             156        16249              9830.65%
                             158        11112              9830.67%
                             160        10978              9830.68%
                             162        12133              9830.70%
                             164        22358              9830.73%
                             166        12949              9830.75%
                             168        10186              9830.76%
                             170        25405              9830.80%
                             172         8805              9830.81%
                             174        41437              9830.87%
                             176        27764              9830.91%
                             178        24127              9830.94%
                             180       230867              9831.26%
                             182         9162              9831.27%
                             184         9176              9831.29%
                             186        12578              9831.31%
                             188         8410              9831.32%
                             190         8070              9831.33%
                             192        10057              9831.34%
                             194         6667              9831.35%
                             196         8246              9831.36%
                             198         7124              9831.37%
                             200         7024              9831.38%
                             202         6410              9831.39%
                             204         5035              9831.40%
                             206         7165              9831.41%
                             208         4682              9831.41%
                             210         5134              9831.42%
                             212         5967              9831.43%
                             214         4083              9831.44%
                             216         6970              9831.45%
                             218         4261              9831.45%
                             220         4642              9831.46%
                             222         6248              9831.47%
                             224         5159              9831.47%
                             226         8085              9831.48%
                             228         5714              9831.49%
                             230         4735              9831.50%
                             232         6998              9831.51%
                             234         9026              9831.52%
                             236        13971              9831.54%
                             238         5064              9831.55%
                             240         6224              9831.56%
                             242         6970              9831.57%
                             244         7366              9831.58%
                             246         7474              9831.59%
                             248         4763              9831.59%
                             250         4158              9831.60%
                             252         6649              9831.61%
                             254         3515              9831.61%
                             256    121236441             10000.00%
system.cpu.iq:occ_dist_0.max_value                256                      
system.cpu.iq:occ_dist_0.end_dist

system.cpu.iq:occ_rate                       4.889193                       # Average occupancy
system.cpu.iq:peak_occupancy                      256                       # Peak IQ occupancy
system.cpu.itb.accesses                      15215798                       # ITB accesses
system.cpu.itb.acv                              53341                       # ITB acv
system.cpu.itb.hits                          15059463                       # ITB hits
system.cpu.itb.misses                          156335                       # ITB misses
system.cpu.kern.callpal                        227049                       # number of callpals executed
system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal_wrfen                       1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal_wrvptptr                    1      0.00%      0.00% # number of callpals executed
system.cpu.kern.callpal_swpctx                   5048      2.22%      2.23% # number of callpals executed
system.cpu.kern.callpal_tbi                        28      0.01%      2.24% # number of callpals executed
system.cpu.kern.callpal_wrent                       7      0.00%      2.24% # number of callpals executed
system.cpu.kern.callpal_swpipl                 210158     92.56%     94.80% # number of callpals executed
system.cpu.kern.callpal_rdps                     4802      2.11%     96.92% # number of callpals executed
system.cpu.kern.callpal_wrkgp                       1      0.00%     96.92% # number of callpals executed
system.cpu.kern.callpal_wrusp                       8      0.00%     96.92% # number of callpals executed
system.cpu.kern.callpal_rdusp                      12      0.01%     96.93% # number of callpals executed
system.cpu.kern.callpal_whami                       1      0.00%     96.93% # number of callpals executed
system.cpu.kern.callpal_rti                      5999      2.64%     99.57% # number of callpals executed
system.cpu.kern.callpal_callsys                   667      0.29%     99.86% # number of callpals executed
system.cpu.kern.callpal_imb                       314      0.14%    100.00% # number of callpals executed
system.cpu.kern.faults                          24629                       # number of faults
system.cpu.kern.faults_interrupt                 2118      8.60%      8.60% # number of faults
system.cpu.kern.faults_dtb_miss_single          11737     47.66%     56.25% # number of faults
system.cpu.kern.faults_dtb_miss_double           3399     13.80%     70.06% # number of faults
system.cpu.kern.faults_dfault                     171      0.69%     70.75% # number of faults
system.cpu.kern.faults_dfault                     242      0.98%     71.73% # number of faults
system.cpu.kern.faults_itbmiss                   6723     27.30%     99.03% # number of faults
system.cpu.kern.faults_iaccvio                    239      0.97%    100.00% # number of faults
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.hwrei                     251680                       # number of hwrei instructions executed
system.cpu.kern.inst.ivlb                           0                       # number of ivlb instructions executed
system.cpu.kern.inst.ivle                           0                       # number of ivle instructions executed
system.cpu.kern.inst.quiesce                     1819                       # number of quiesce instructions executed
system.cpu.kern.ipl_count                      218276                       # number of times we switched to this ipl
system.cpu.kern.ipl_count_0                     92027     42.16%     42.16% # number of times we switched to this ipl
system.cpu.kern.ipl_count_21                      280      0.13%     42.29% # number of times we switched to this ipl
system.cpu.kern.ipl_count_22                     5674      2.60%     44.89% # number of times we switched to this ipl
system.cpu.kern.ipl_count_31                   120295     55.11%    100.00% # number of times we switched to this ipl
system.cpu.kern.ipl_good                       190394                       # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_0                      90302     47.43%     47.43% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_21                       280      0.15%     47.58% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_22                      5674      2.98%     50.56% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good_31                     94138     49.44%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_ticks                  7199891186                       # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_0                7147587803     99.27%     99.27% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_21                   119041      0.00%     99.28% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_22                   899245      0.01%     99.29% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks_31                 51285097      0.71%    100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_used                     0.872263                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_0                   0.981256                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_21                         1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_22                         1                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used_31                  0.782560                       # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_good_kernel                 2513                      
system.cpu.kern.mode_good_user                   2166                      
system.cpu.kern.mode_good_idle                    105                      
system.cpu.kern.mode_good_interrupt               242                      
system.cpu.kern.mode_switch_kernel              11648                       # number of protection mode switches
system.cpu.kern.mode_switch_user                 2166                       # number of protection mode switches
system.cpu.kern.mode_switch_idle                 5602                       # number of protection mode switches
system.cpu.kern.mode_switch_interrupt             242                       # number of protection mode switches
system.cpu.kern.mode_switch_good             0.255672                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_kernel      0.215745                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_user               1                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_idle        0.018743                       # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good_interrupt            1                       # fraction of useful protection mode switches
system.cpu.kern.mode_ticks_kernel           168168870      2.34%      2.34% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_user               6343290      0.09%      2.42% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_idle            7024324290     97.56%     99.99% # number of ticks spent at the given mode
system.cpu.kern.mode_ticks_interrupt          1054736      0.01%    100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context                     5049                       # number of times the context was actually changed
system.cpu.kern.syscall                           475                       # number of syscalls executed
system.cpu.kern.syscall_fork                       10      2.11%      2.11% # number of syscalls executed
system.cpu.kern.syscall_read                       33      6.95%      9.05% # number of syscalls executed
system.cpu.kern.syscall_write                       7      1.47%     10.53% # number of syscalls executed
system.cpu.kern.syscall_close                      49     10.32%     20.84% # number of syscalls executed
system.cpu.kern.syscall_chdir                       1      0.21%     21.05% # number of syscalls executed
system.cpu.kern.syscall_chmod                       1      0.21%     21.26% # number of syscalls executed
system.cpu.kern.syscall_obreak                     44      9.26%     30.53% # number of syscalls executed
system.cpu.kern.syscall_lseek                      13      2.74%     33.26% # number of syscalls executed
system.cpu.kern.syscall_getpid                     10      2.11%     35.37% # number of syscalls executed
system.cpu.kern.syscall_setuid                      4      0.84%     36.21% # number of syscalls executed
system.cpu.kern.syscall_getuid                      8      1.68%     37.89% # number of syscalls executed
system.cpu.kern.syscall_access                      4      0.84%     38.74% # number of syscalls executed
system.cpu.kern.syscall_dup                         4      0.84%     39.58% # number of syscalls executed
system.cpu.kern.syscall_open                       68     14.32%     53.89% # number of syscalls executed
system.cpu.kern.syscall_getgid                      8      1.68%     55.58% # number of syscalls executed
system.cpu.kern.syscall_sigprocmask                14      2.95%     58.53% # number of syscalls executed
system.cpu.kern.syscall_ioctl                      16      3.37%     61.89% # number of syscalls executed
system.cpu.kern.syscall_readlink                    2      0.42%     62.32% # number of syscalls executed
system.cpu.kern.syscall_execve                      8      1.68%     64.00% # number of syscalls executed
system.cpu.kern.syscall_pre_F64_stat               31      6.53%     70.53% # number of syscalls executed
system.cpu.kern.syscall_pre_F64_lstat               1      0.21%     70.74% # number of syscalls executed
system.cpu.kern.syscall_mmap                       55     11.58%     82.32% # number of syscalls executed
system.cpu.kern.syscall_munmap                      6      1.26%     83.58% # number of syscalls executed
system.cpu.kern.syscall_mprotect                   14      2.95%     86.53% # number of syscalls executed
system.cpu.kern.syscall_gethostname                 2      0.42%     86.95% # number of syscalls executed
system.cpu.kern.syscall_dup2                        4      0.84%     87.79% # number of syscalls executed
system.cpu.kern.syscall_pre_F64_fstat              28      5.89%     93.68% # number of syscalls executed
system.cpu.kern.syscall_fcntl                      14      2.95%     96.63% # number of syscalls executed
system.cpu.kern.syscall_socket                      3      0.63%     97.26% # number of syscalls executed
system.cpu.kern.syscall_connect                     3      0.63%     97.89% # number of syscalls executed
system.cpu.kern.syscall_setgid                      4      0.84%     98.74% # number of syscalls executed
system.cpu.kern.syscall_getrlimit                   3      0.63%     99.37% # number of syscalls executed
system.cpu.kern.syscall_setsid                      3      0.63%    100.00% # number of syscalls executed
system.cpu.l2.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l2.avg_refs                       3.697134                       # Average number of references to valid blocks.
system.cpu.l2.blocked_no_mshrs                      0                       # number of cycles access was blocked
system.cpu.l2.blocked_no_targets                    0                       # number of cycles access was blocked
system.cpu.l2.blocked_cycles_no_mshrs               0                       # number of cycles access was blocked
system.cpu.l2.blocked_cycles_no_targets             0                       # number of cycles access was blocked
system.cpu.l2.cache_copies                          0                       # number of cache copies performed
system.cpu.l2.demand_accesses                 2616440                       # number of demand (read+write) accesses
system.cpu.l2.demand_avg_miss_latency       90.880827                       # average overall miss latency
system.cpu.l2.demand_avg_mshr_miss_latency    74.612303                       # average overall mshr miss latency
system.cpu.l2.demand_hits                     1939240                       # number of demand (read+write) hits
system.cpu.l2.demand_miss_latency            61544496                       # number of demand (read+write) miss cycles
system.cpu.l2.demand_miss_rate               0.258825                       # miss rate for demand accesses
system.cpu.l2.demand_misses                    677200                       # number of demand (read+write) misses
system.cpu.l2.demand_mshr_hits                      3                       # number of demand (read+write) MSHR hits
system.cpu.l2.demand_mshr_miss_latency       50527228                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2.demand_mshr_miss_rate          0.258824                       # mshr miss rate for demand accesses
system.cpu.l2.demand_mshr_misses               677197                       # number of demand (read+write) MSHR misses
system.cpu.l2.fast_writes                           0                       # number of fast writes performed
system.cpu.l2.mshr_cap_events                       0                       # number of times MSHR cap was activated
system.cpu.l2.no_allocate_misses                    0                       # Number of misses that were no-allocate
system.cpu.l2.overall_accesses                3181749                       # number of overall (read+write) accesses
system.cpu.l2.overall_avg_miss_latency      90.709508                       # average overall miss latency
system.cpu.l2.overall_avg_mshr_miss_latency    74.612303                       # average overall mshr miss latency
system.cpu.l2.overall_avg_mshr_uncacheable_latency   128.021642                       # average overall mshr uncacheable latency
system.cpu.l2.overall_hits                    2503270                       # number of overall hits
system.cpu.l2.overall_miss_latency           61544496                       # number of overall miss cycles
system.cpu.l2.overall_miss_rate              0.213241                       # miss rate for overall accesses
system.cpu.l2.overall_misses                   678479                       # number of overall misses
system.cpu.l2.overall_mshr_hits                     3                       # number of overall MSHR hits
system.cpu.l2.overall_mshr_miss_latency      50527228                       # number of overall MSHR miss cycles
system.cpu.l2.overall_mshr_miss_rate         0.212838                       # mshr miss rate for overall accesses
system.cpu.l2.overall_mshr_misses              677197                       # number of overall MSHR misses
system.cpu.l2.overall_mshr_uncacheable_latency      2123623                       # number of overall MSHR uncacheable cycles
system.cpu.l2.overall_mshr_uncacheable_misses        16588                       # number of overall MSHR uncacheable misses
system.cpu.l2.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.l2.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.l2.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.l2.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.l2.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.l2.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.l2.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.l2.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.l2.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2.read_accesses                   2616440                       # number of read accesses(hits+misses)
system.cpu.l2.read_avg_miss_latency         90.880827                       # average read miss latency
system.cpu.l2.read_avg_mshr_miss_latency    74.612303                       # average read mshr miss latency
system.cpu.l2.read_avg_mshr_uncacheable_latency    73.619089                       # average read mshr uncacheable latency
system.cpu.l2.read_hits                       1939240                       # number of read hits
system.cpu.l2.read_miss_latency              61544496                       # number of read miss cycles
system.cpu.l2.read_miss_rate                 0.258825                       # miss rate for read accesses
system.cpu.l2.read_misses                      677200                       # number of read misses
system.cpu.l2.read_mshr_hits                        3                       # number of read MSHR hits
system.cpu.l2.read_mshr_miss_latency         50527228                       # number of read MSHR miss cycles
system.cpu.l2.read_mshr_miss_rate            0.258824                       # mshr miss rate for read accesses
system.cpu.l2.read_mshr_misses                 677197                       # number of read MSHR misses
system.cpu.l2.read_mshr_uncacheable              6936                       # number of read MSHR uncacheable
system.cpu.l2.read_mshr_uncacheable_latency       510622                       # number of read MSHR uncacheable cycles
system.cpu.l2.replacements                     672988                       # number of replacements
system.cpu.l2.sampled_refs                     677084                       # Sample count of references to valid blocks.
system.cpu.l2.soft_prefetch_mshr_full               0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l2.tagsinuse                   4095.885253                       # Cycle average of tags in use
system.cpu.l2.total_refs                      2503270                       # Total number of references to valid blocks.
system.cpu.l2.warmup_cycle                     761681                       # Cycle when the warmup percentage was hit.
system.cpu.l2.write_avg_mshr_uncacheable_latency   167.115727                       # average write mshr uncacheable latency
system.cpu.l2.write_mshr_uncacheable             9652                       # number of write MSHR uncacheable
system.cpu.l2.write_mshr_uncacheable_latency      1613001                       # number of write MSHR uncacheable cycles
system.cpu.l2.writeback_accesses               565309                       # number of writeback accesses(hits+misses)
system.cpu.l2.writeback_hits                   564030                       # number of writeback hits
system.cpu.l2.writeback_miss_rate            0.002262                       # miss rate for writeback accesses
system.cpu.l2.writeback_misses                   1279                       # number of writeback misses
system.cpu.l2.writeback_mshr_miss_rate       0.002262                       # mshr miss rate for writeback accesses
system.cpu.l2.writeback_mshr_misses              1279                       # number of writeback MSHR misses
system.cpu.l2.writebacks                       247993                       # number of writebacks
system.cpu.l3.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l3.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu.l3.avg_refs                       1.922879                       # Average number of references to valid blocks.
system.cpu.l3.blocked_no_mshrs                      0                       # number of cycles access was blocked
system.cpu.l3.blocked_no_targets                    0                       # number of cycles access was blocked
system.cpu.l3.blocked_cycles_no_mshrs               0                       # number of cycles access was blocked
system.cpu.l3.blocked_cycles_no_targets             0                       # number of cycles access was blocked
system.cpu.l3.cache_copies                          0                       # number of cache copies performed
system.cpu.l3.demand_accesses                  677197                       # number of demand (read+write) accesses
system.cpu.l3.demand_avg_miss_latency      111.787652                       # average overall miss latency
system.cpu.l3.demand_avg_mshr_miss_latency    74.190979                       # average overall mshr miss latency
system.cpu.l3.demand_hits                      360057                       # number of demand (read+write) hits
system.cpu.l3.demand_miss_latency            35452336                       # number of demand (read+write) miss cycles
system.cpu.l3.demand_miss_rate               0.468313                       # miss rate for demand accesses
system.cpu.l3.demand_misses                    317140                       # number of demand (read+write) misses
system.cpu.l3.demand_mshr_hits                      0                       # number of demand (read+write) MSHR hits
system.cpu.l3.demand_mshr_miss_latency       23528927                       # number of demand (read+write) MSHR miss cycles
system.cpu.l3.demand_mshr_miss_rate          0.468313                       # mshr miss rate for demand accesses
system.cpu.l3.demand_mshr_misses               317140                       # number of demand (read+write) MSHR misses
system.cpu.l3.fast_writes                           0                       # number of fast writes performed
system.cpu.l3.mshr_cap_events                       0                       # number of times MSHR cap was activated
system.cpu.l3.no_allocate_misses                    0                       # Number of misses that were no-allocate
system.cpu.l3.overall_accesses                 926469                       # number of overall (read+write) accesses
system.cpu.l3.overall_avg_miss_latency     111.749597                       # average overall miss latency
system.cpu.l3.overall_avg_mshr_miss_latency    74.190979                       # average overall mshr miss latency
system.cpu.l3.overall_avg_mshr_uncacheable_latency    87.149445                       # average overall mshr uncacheable latency
system.cpu.l3.overall_hits                     609221                       # number of overall hits
system.cpu.l3.overall_miss_latency           35452336                       # number of overall miss cycles
system.cpu.l3.overall_miss_rate              0.342427                       # miss rate for overall accesses
system.cpu.l3.overall_misses                   317248                       # number of overall misses
system.cpu.l3.overall_mshr_hits                     0                       # number of overall MSHR hits
system.cpu.l3.overall_mshr_miss_latency      23528927                       # number of overall MSHR miss cycles
system.cpu.l3.overall_mshr_miss_rate         0.342310                       # mshr miss rate for overall accesses
system.cpu.l3.overall_mshr_misses              317140                       # number of overall MSHR misses
system.cpu.l3.overall_mshr_uncacheable_latency      1445635                       # number of overall MSHR uncacheable cycles
system.cpu.l3.overall_mshr_uncacheable_misses        16588                       # number of overall MSHR uncacheable misses
system.cpu.l3.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu.l3.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu.l3.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu.l3.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu.l3.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu.l3.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu.l3.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu.l3.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu.l3.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l3.read_accesses                    677197                       # number of read accesses(hits+misses)
system.cpu.l3.read_avg_miss_latency        111.787652                       # average read miss latency
system.cpu.l3.read_avg_mshr_miss_latency    74.190979                       # average read mshr miss latency
system.cpu.l3.read_avg_mshr_uncacheable_latency    32.723183                       # average read mshr uncacheable latency
system.cpu.l3.read_hits                        360057                       # number of read hits
system.cpu.l3.read_miss_latency              35452336                       # number of read miss cycles
system.cpu.l3.read_miss_rate                 0.468313                       # miss rate for read accesses
system.cpu.l3.read_misses                      317140                       # number of read misses
system.cpu.l3.read_mshr_miss_latency         23528927                       # number of read MSHR miss cycles
system.cpu.l3.read_mshr_miss_rate            0.468313                       # mshr miss rate for read accesses
system.cpu.l3.read_mshr_misses                 317140                       # number of read MSHR misses
system.cpu.l3.read_mshr_uncacheable              6936                       # number of read MSHR uncacheable
system.cpu.l3.read_mshr_uncacheable_latency       226968                       # number of read MSHR uncacheable cycles
system.cpu.l3.replacements                     284170                       # number of replacements
system.cpu.l3.sampled_refs                     316348                       # Sample count of references to valid blocks.
system.cpu.l3.soft_prefetch_mshr_full               0                       # number of mshr full events for SW prefetching instrutions
system.cpu.l3.tagsinuse                  32754.065341                       # Cycle average of tags in use
system.cpu.l3.total_refs                       608299                       # Total number of references to valid blocks.
system.cpu.l3.warmup_cycle                    5890021                       # Cycle when the warmup percentage was hit.
system.cpu.l3.write_avg_mshr_uncacheable_latency   126.260568                       # average write mshr uncacheable latency
system.cpu.l3.write_mshr_uncacheable             9652                       # number of write MSHR uncacheable
system.cpu.l3.write_mshr_uncacheable_latency      1218667                       # number of write MSHR uncacheable cycles
system.cpu.l3.writeback_accesses               249272                       # number of writeback accesses(hits+misses)
system.cpu.l3.writeback_hits                   249164                       # number of writeback hits
system.cpu.l3.writeback_miss_rate            0.000433                       # miss rate for writeback accesses
system.cpu.l3.writeback_misses                    108                       # number of writeback misses
system.cpu.l3.writeback_mshr_miss_rate       0.000433                       # mshr miss rate for writeback accesses
system.cpu.l3.writeback_mshr_misses               108                       # number of writeback MSHR misses
system.cpu.l3.writebacks                       137889                       # number of writebacks
system.cpu.numCycles                       7199893258                       # number of cpu cycles simulated
system.cpu.toL2Bus.addr_idle_cycles        7196638323                       # number of cycles bus was idle
system.cpu.toL2Bus.addr_idle_fraction        0.999548                       # fraction of time addr bus was idle
system.cpu.toL2Bus.addr_queued               3.720510                       # average queueing delay seen by bus request
system.cpu.toL2Bus.addr_queued_cycles        12081913                       # total number of queued cycles for all requests
system.cpu.toL2Bus.addr_requests              3247381                       # number of transmissions on bus
system.cpu.toL2Bus.bus_blocked                    314                       # number of times bus was blocked
system.cpu.toL2Bus.bus_blocked_cycles           84038                       # number of cycles bus was blocked
system.cpu.toL2Bus.bus_blocked_fraction      0.000012                       # fraction of time bus was blocked
system.cpu.toL2Bus.data_idle_cycles        7196694896                       # number of cycles bus was idle
system.cpu.toL2Bus.data_idle_fraction        0.999556                       # fraction of time data bus was idle
system.cpu.toL2Bus.data_queued               1.023612                       # average queueing delay seen by bus request
system.cpu.toL2Bus.data_queued_cycles         2685317                       # total number of queued cycles for all requests
system.cpu.toL2Bus.data_requests              2623375                       # number of transmissions on bus
system.cpu.toL2Bus.null_grants                  66687                       # number of null grants (wasted cycles)
system.cpu.toL3Bus.addr_idle_cycles        7198901014                       # number of cycles bus was idle
system.cpu.toL3Bus.addr_idle_fraction        0.999862                       # fraction of time addr bus was idle
system.cpu.toL3Bus.addr_queued               9.898436                       # average queueing delay seen by bus request
system.cpu.toL3Bus.addr_queued_cycles         9820248                       # total number of queued cycles for all requests
system.cpu.toL3Bus.addr_requests               992101                       # number of transmissions on bus
system.cpu.toL3Bus.bus_blocked                    191                       # number of times bus was blocked
system.cpu.toL3Bus.bus_blocked_cycles           74529                       # number of cycles bus was blocked
system.cpu.toL3Bus.bus_blocked_fraction      0.000010                       # fraction of time bus was blocked
system.cpu.toL3Bus.data_idle_cycles        7198950166                       # number of cycles bus was idle
system.cpu.toL3Bus.data_idle_fraction        0.999869                       # fraction of time data bus was idle
system.cpu.toL3Bus.data_queued               1.056472                       # average queueing delay seen by bus request
system.cpu.toL3Bus.data_queued_cycles          722766                       # total number of queued cycles for all requests
system.cpu.toL3Bus.data_requests               684132                       # number of transmissions on bus
system.cpu.toL3Bus.null_grants                      0                       # number of null grants (wasted cycles)
system.cpuinst_class_dist.start_dist
                   All ops ready            0      0.00%            # Operand status at dispatch
                One op not ready            0      0.00%            # Operand status at dispatch
           None rdy, mult chains            0      0.00%            # Operand status at dispatch
           None rdy, one chained            0      0.00%            # Operand status at dispatch
        None rdy, all self-timed            0      0.00%            # Operand status at dispatch
system.cpuinst_class_dist.end_dist
system.kern.fnCalls                                 0                       # all fn calls being tracked
system.ram.accesses                            494699                       # total number of accesses
system.ram.bytes_requested                          0                       # total number of bytes requested
system.ram.bytes_sent                               0                       # total number of bytes sent
system.ram.compressed_responses                     0                       # total number of accesses that are compressed
system.toMemBus.addr_idle_cycles           7199321954                       # number of cycles bus was idle
system.toMemBus.addr_idle_fraction           0.999921                       # fraction of time addr bus was idle
system.toMemBus.addr_queued                 33.558497                       # average queueing delay seen by bus request
system.toMemBus.addr_queued_cycles           18803866                       # total number of queued cycles for all requests
system.toMemBus.addr_requests                  560331                       # number of transmissions on bus
system.toMemBus.bus_blocked                         0                       # number of times bus was blocked
system.toMemBus.bus_blocked_cycles                  0                       # number of cycles bus was blocked
system.toMemBus.bus_blocked_fraction                0                       # fraction of time bus was blocked
system.toMemBus.data_idle_cycles           7197886927                       # number of cycles bus was idle
system.toMemBus.data_idle_fraction           0.999721                       # fraction of time data bus was idle
system.toMemBus.data_queued                  7.311816                       # average queueing delay seen by bus request
system.toMemBus.data_queued_cycles            2370827                       # total number of queued cycles for all requests
system.toMemBus.data_requests                  324246                       # number of transmissions on bus
system.toMemBus.null_grants                         0                       # number of null grants (wasted cycles)
system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk    <err: div-0>                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.dma.avg_large_transaction_latency <err: div-0>                       # The average latency of large transactions.
system.tsunami.ethernet.dma.avg_small_transaction_latency <err: div-0>                       # The average latency of small transactions.
system.tsunami.ethernet.dma.avg_transaction_latency <err: div-0>                       # The average latency of all transactions.
system.tsunami.ethernet.dma.bytes_transfered            0                       # Total bytes sent
system.tsunami.ethernet.dma.large_transaction_latency            0                       # The total cycle latency of all large transactions.
system.tsunami.ethernet.dma.large_transactions            0                       # Total number of transactions greater than the block size.
system.tsunami.ethernet.dma.packets_sent            0                       # number of packets sent(blocks)
system.tsunami.ethernet.dma.requests                0                       # Total number of dma requests made
system.tsunami.ethernet.dma.round_trip_latency <err: div-0>                       # Average Round-Trip latency
system.tsunami.ethernet.dma.small_transaction_latency            0                       # The total cycle latency of all small transactions.
system.tsunami.ethernet.dma.small_transactions            0                       # Total number of transactions less than the block size.
system.tsunami.ethernet.dma.total_cycle_latency            0                       # sum of all latencies
system.tsunami.ethernet.dma.transaction_latency            0                       # The total cycle latency of all transactions.
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # number of total RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # number of total RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # number of total RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # number of total RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # number of total Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # number of total TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # number of total TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # number of total TxOk written to ISR
system.tsunami.ide.dma.avg_large_transaction_latency   527.914894                       # The average latency of large transactions.
system.tsunami.ide.dma.avg_small_transaction_latency    44.012987                       # The average latency of small transactions.
system.tsunami.ide.dma.avg_transaction_latency   387.309434                       # The average latency of all transactions.
system.tsunami.ide.dma.bytes_transfered       2531440                       # Total bytes sent
system.tsunami.ide.dma.large_transaction_latency       198496                       # The total cycle latency of all large transactions.
system.tsunami.ide.dma.large_transactions          376                       # Total number of transactions greater than the block size.
system.tsunami.ide.dma.packets_sent             39562                       # number of packets sent(blocks)
system.tsunami.ide.dma.requests                   530                       # Total number of dma requests made
system.tsunami.ide.dma.round_trip_latency   285.797027                       # Average Round-Trip latency
system.tsunami.ide.dma.small_transaction_latency         6778                       # The total cycle latency of all small transactions.
system.tsunami.ide.dma.small_transactions          154                       # Total number of transactions less than the block size.
system.tsunami.ide.dma.total_cycle_latency     11306702                       # sum of all latencies
system.tsunami.ide.dma.transaction_latency       205274                       # The total cycle latency of all transactions.

---------- End Simulation Statistics   ----------
