
---------- Begin Simulation Statistics ----------
host_inst_rate                                  21857                       # Simulator instruction rate (inst/s)
host_mem_usage                                 200828                       # Number of bytes of host memory used
host_seconds                                 42182.65                       # Real time elapsed on the host
host_tick_rate                                 174301                       # Simulator tick rate (ticks/s)
sim_freq                                   4000000000                       # Frequency of simulated ticks
sim_insts                                   921968140                       # Number of instructions simulated
sim_seconds                                  1.838117                       # Number of seconds simulated
sim_ticks                                  7352469841                       # Number of ticks simulated
system.cpu0.COM:IPB                          3.098876                       # Committed instructions per branch
system.cpu0.COM:IPC                          0.104435                       # Committed instructions per cycle
system.cpu0.COM:branches                    247785752                       # Number of branches committed
system.cpu0.COM:bw_lim_avg               <err: div-0>                       # Avg number not committed in cycles BW limited
system.cpu0.COM:bw_lim_events                       0                       # number cycles where commit BW limit reached
system.cpu0.COM:bw_lim_rate                    0.0000                       # Average number not committed due to BW (over all cycles)
system.cpu0.COM:bw_lim_stdev_0_mean      <err: div-0>                       # standard deviation of bw_lim_avg value
system.cpu0.COM:bw_lim_stdev_0_stdev     <err: div-0>                       # standard deviation of bw_lim_avg value
**Ignore: system.cpu0.COM:bw_lim_stdev_0_TOT       0.0000                       # standard deviation of bw_lim_avg value
system.cpu0.COM:bw_limited                          0                       # number of insts not committed due to BW limits
system.cpu0.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu0.COM:committed_per_cycle.samples    134211800                      
system.cpu0.COM:committed_per_cycle.min_value            0                      
                               0       271423     20.22%           
                               1      5328814    397.05%           
                               2      2182786    162.64%           
                               3     11966576    891.62%           
                               4     30307720   2258.20%           
                               5       578824     43.13%           
                               6     29682627   2211.63%           
                               7     10893697    811.68%           
                               8     42999333   3203.84%           
system.cpu0.COM:committed_per_cycle.max_value            8                      
system.cpu0.COM:committed_per_cycle.end_dist

system.cpu0.COM:count                       767857289                       # Number of instructions committed
system.cpu0.COM:loads                         8265223                       # Number of loads committed
system.cpu0.COM:membars                        201523                       # Number of memory barriers committed
system.cpu0.COM:refs                         13949106                       # Number of memory references committed
system.cpu0.COM:stores                        5683883                       # Number of stores committed
system.cpu0.COM:swp_count                      208130                       # Number of s/w prefetches committed
system.cpu0.DDQ:count                     20743817435                       # cum count of instructions
system.cpu0.DDQ:rate                                3                       # average number of instructions
system.cpu0.DIS:chain_creation.start_dist
     Inst has no outstanding IDEPS            0      0.00%            # Reason that chain head was created
      IDEP chain reached max depth            0      0.00%            # Reason that chain head was created
                    Inst is a load            0      0.00%            # Reason that chain head was created
  Chain has multiple chained IDEPS            0      0.00%            # Reason that chain head was created
system.cpu0.DIS:chain_creation.end_dist
system.cpu0.DIS:chain_head_frac                     0                       # fraction of insts that are chain heads
system.cpu0.DIS:chain_heads                         0                       # number insts that are chain heads
system.cpu0.DIS:chains_insuf                        0                       # number of times thread had insuf chains
system.cpu0.DIS:chains_insuf_rate                   0                       # rate that thread had insuf chains
system.cpu0.DIS:count                       788090890                       # cumulative count of dispatched insts
system.cpu0.DIS:insufficient_chains                 0                       # Number of instances where dispatch stopped
system.cpu0.DIS:mod_n_stall_avg_free         no value                       # avg free slots per cycle
system.cpu0.DIS:mod_n_stall_frac                    0                       # avg stalls per cycle
system.cpu0.DIS:mod_n_stall_free                    0                       # free slots when dispatch stalled due to mod-n
system.cpu0.DIS:mod_n_stalls                        0                       # cycles where dispatch stalled due to mod-n
system.cpu0.DIS:one_rdy_insts                       0                       # number of 2-op insts w/ one rdy op
system.cpu0.DIS:one_rdy_ratio                no value                       # fraction of 2-op insts w/ one ready op
system.cpu0.DIS:op_count                    807080530                       # number of operations dispatched
system.cpu0.DIS:op_rate                      0.109770                       # dispatched operations per cycle
system.cpu0.DIS:rate                         0.107187                       # dispatched_insts per cycle
system.cpu0.DIS:second_choice_clust                 0                       # Number of instructions dispatched to second-choice cluster
system.cpu0.DIS:second_choice_stall                 0                       # Number of instructions stalled when first choice not available
system.cpu0.DIS:serialize_stall_cycles        5326566                       # count of cycles dispatch stalled for serializing inst
system.cpu0.DIS:serializing_insts              350329                       # count of serializing insts dispatched
system.cpu0.DIS:two_input_insts                     0                       # Number of two input instructions queued
system.cpu0.DIS:two_input_ratio                     0                       # fraction of all insts having 2 inputs
system.cpu0.FETCH:branch_count              264700516                       # Number of branches fetched
system.cpu0.FETCH:branch_rate                0.036002                       # Number of branch fetches per cycle
system.cpu0.FETCH:chance_pct                        1                       # Percentage of all fetch chances
system.cpu0.FETCH:chances                   141165384                       # Number of fetch opportunities
system.cpu0.FETCH:choice                    141165384                       # Number of times we fetched from our first choice
system.cpu0.FETCH:count                     852275587                       # Number of instructions fetched
system.cpu0.FETCH:decisions                 141165384                       # number of times the fetch stage chose between threads
system.cpu0.FETCH:idle_cycles              7211304458                       # number of cycles where fetch stage was idle
system.cpu0.FETCH:idle_icache_blocked_cycles            0                       # number of cycles where fetch was idle due to icache blocked
system.cpu0.FETCH:idle_rate                     98.08                       # percent of cycles fetch stage was idle
system.cpu0.FETCH:prio_changes                      0                       # Number of times priorities were changed
system.cpu0.FETCH:rate                       0.115917                       # Number of inst fetches per cycle
system.cpu0.FETCH:rate_dist.start_dist                         # Number of instructions fetched each cycle (Total)
system.cpu0.FETCH:rate_dist.samples         141165384                      
system.cpu0.FETCH:rate_dist.min_value               0                      
                               0       123053      8.72%           
                               1      1594816    112.98%           
                               2       682663     48.36%           
                               3      2504050    177.38%           
                               4       882695     62.53%           
                               5       468297     33.17%           
                               6    121373350   8597.95%           
                               7       600750     42.56%           
                               8     12935710    916.35%           
system.cpu0.FETCH:rate_dist.max_value               8                      
system.cpu0.FETCH:rate_dist.end_dist

system.cpu0.FETCH:rate_dist_0.start_dist                       # Number of instructions fetched each cycle (Thread 0)
system.cpu0.FETCH:rate_dist_0.samples       141165384                      
system.cpu0.FETCH:rate_dist_0.min_value             0                      
                               0       123053      8.72%           
                               1      1594816    112.98%           
                               2       682663     48.36%           
                               3      2504050    177.38%           
                               4       882695     62.53%           
                               5       468297     33.17%           
                               6    121373350   8597.95%           
                               7       600750     42.56%           
                               8     12935710    916.35%           
system.cpu0.FETCH:rate_dist_0.max_value             8                      
system.cpu0.FETCH:rate_dist_0.end_dist

system.cpu0.IFQ:count                      5281763072                       # cumulative IFQ occupancy
system.cpu0.IFQ:full_count                  158931583                       # cumulative IFQ full count
system.cpu0.IFQ:full_rate                    2.161608                       # fraction of time (cycle's) IFQ was full
system.cpu0.IFQ:latency                      6.701972                       # avg IFQ occupant latency (cycle's)
system.cpu0.IFQ:occupancy                    0.718366                       # avg IFQ occupancy (inst's)
system.cpu0.IFQ:qfull_iq_occ               1722366222                       # Number of insts in IQ when fetch-queue full
system.cpu0.IFQ:qfull_iq_occ_dist_0.start_dist                     # Number of insts in IQ when fetch-queue full
system.cpu0.IFQ:qfull_iq_occ_dist_0.samples     33210878                      
system.cpu0.IFQ:qfull_iq_occ_dist_0.min_value            0                      
                               0      4963851   1494.65%           
                              10       708406    213.31%           
                              20       508383    153.08%           
                              30       635673    191.41%           
                              40       772473    232.60%           
                              50       355138    106.93%           
                              60     25266954   7608.04%           
system.cpu0.IFQ:qfull_iq_occ_dist_0.max_value           64                      
system.cpu0.IFQ:qfull_iq_occ_dist_0.end_dist

system.cpu0.IFQ:qfull_rob_occ              3094796875                       # Number of insts in ROB when fetch-queue full
system.cpu0.IFQ:qfull_rob_occ_dist_0.start_dist                     # Number of insts in ROB when fetch-queue full
system.cpu0.IFQ:qfull_rob_occ_dist_0.samples     33210878                      
system.cpu0.IFQ:qfull_rob_occ_dist_0.min_value            1                      
                               0       417906    125.83%           
                              10       650609    195.90%           
                              20       508806    153.20%           
                              30       182722     55.02%           
                              40       123109     37.07%           
                              50        92217     27.77%           
                              60      3096696    932.43%           
                              70      1335461    402.12%           
                              80       570694    171.84%           
                              90     20713923   6237.09%           
                             100       400791    120.68%           
                             110       536821    161.64%           
                             120      4581123   1379.40%           
                             130            0      0.00%           
system.cpu0.IFQ:qfull_rob_occ_dist_0.max_value          128                      
system.cpu0.IFQ:qfull_rob_occ_dist_0.end_dist

system.cpu0.IQ:cap_events                           0                       # number of cycles where IQ cap was active
system.cpu0.IQ:cap_inst                             0                       # number of instructions held up by IQ cap
system.cpu0.IQ:residence:(null).start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:(null).samples          4226                      
system.cpu0.IQ:residence:(null).min_value            1                      
                               0         4112   9730.24%   9730.24%
                               2          113    267.39%   9997.63%
                               4            0      0.00%   9997.63%
                               6            0      0.00%   9997.63%
                               8            1      2.37%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu0.IQ:residence:(null).max_value            9                      
system.cpu0.IQ:residence:(null).end_dist

system.cpu0.IQ:residence:IntAlu.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:IntAlu.samples     758931823                      
system.cpu0.IQ:residence:IntAlu.min_value            1                      
                               0      9308384    122.65%    122.65%
                               2      6319773     83.27%    205.92%
                               4      4436558     58.46%    264.38%
                               6      3105418     40.92%    305.30%
                               8     64322210    847.54%   1152.84%
                              10    535807670   7060.02%   8212.86%
                              12    125526462   1653.99%   9866.85%
                              14      1175710     15.49%   9882.34%
                              16       942688     12.42%   9894.76%
                              18       646913      8.52%   9903.28%
                              20       473480      6.24%   9909.52%
                              22       367379      4.84%   9914.36%
                              24       361571      4.76%   9919.13%
                              26       317558      4.18%   9923.31%
                              28       270551      3.56%   9926.88%
                              30       255756      3.37%   9930.25%
                              32       242645      3.20%   9933.44%
                              34       232135      3.06%   9936.50%
                              36       154619      2.04%   9938.54%
                              38       150767      1.99%   9940.53%
                              40       150333      1.98%   9942.51%
                              42        79706      1.05%   9943.56%
                              44       120611      1.59%   9945.15%
                              46        49274      0.65%   9945.80%
                              48        55562      0.73%   9946.53%
                              50       108305      1.43%   9947.96%
                              52       136190      1.79%   9949.75%
                              54       207245      2.73%   9952.48%
                              56        45211      0.60%   9953.08%
                              58        41550      0.55%   9953.62%
                              60        37865      0.50%   9954.12%
                              62       144135      1.90%   9956.02%
                              64       125157      1.65%   9957.67%
                              66        43822      0.58%   9958.25%
                              68        42364      0.56%   9958.81%
                              70        60239      0.79%   9959.60%
                              72        43641      0.58%   9960.18%
                              74        30563      0.40%   9960.58%
                              76        23834      0.31%   9960.89%
                              78        44438      0.59%   9961.48%
                              80        22578      0.30%   9961.78%
                              82        31051      0.41%   9962.18%
                              84        30835      0.41%   9962.59%
                              86        27215      0.36%   9962.95%
                              88        25694      0.34%   9963.29%
                              90        15681      0.21%   9963.50%
                              92        13895      0.18%   9963.68%
                              94        27634      0.36%   9964.04%
                              96        38631      0.51%   9964.55%
                              98        10266      0.14%   9964.69%
system.cpu0.IQ:residence:IntAlu.overflows      2680051                      
system.cpu0.IQ:residence:IntAlu.max_value        13139                      
system.cpu0.IQ:residence:IntAlu.end_dist

system.cpu0.IQ:residence:IntMult.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:IntMult.samples        60757                      
system.cpu0.IQ:residence:IntMult.min_value            1                      
                               0          992    163.27%    163.27%
                               2         2622    431.56%    594.83%
                               4         5984    984.91%   1579.74%
                               6         4830    794.97%   2374.71%
                               8         4078    671.20%   3045.90%
                              10         6325   1041.03%   4086.94%
                              12         4180    687.99%   4774.92%
                              14         1692    278.49%   5053.41%
                              16          308     50.69%   5104.10%
                              18         1505    247.71%   5351.81%
                              20          661    108.79%   5460.61%
                              22          859    141.38%   5601.99%
                              24         2932    482.58%   6084.57%
                              26          549     90.36%   6174.93%
                              28         1232    202.77%   6377.70%
                              30          809    133.15%   6510.85%
                              32          112     18.43%   6529.29%
                              34          546     89.87%   6619.15%
                              36         1165    191.75%   6810.90%
                              38           84     13.83%   6824.73%
                              40        13007   2140.82%   8965.55%
                              42          339     55.80%   9021.35%
                              44          448     73.74%   9095.08%
                              46           69     11.36%   9106.44%
                              48          119     19.59%   9126.03%
                              50           46      7.57%   9133.60%
                              52           10      1.65%   9135.24%
                              54           54      8.89%   9144.13%
                              56           77     12.67%   9156.80%
                              58          156     25.68%   9182.48%
                              60          186     30.61%   9213.09%
                              62           12      1.98%   9215.07%
                              64           94     15.47%   9230.54%
                              66           23      3.79%   9234.33%
                              68           24      3.95%   9238.28%
                              70           50      8.23%   9246.51%
                              72           20      3.29%   9249.80%
                              74           18      2.96%   9252.76%
                              76           11      1.81%   9254.57%
                              78           19      3.13%   9257.70%
                              80           13      2.14%   9259.84%
                              82           78     12.84%   9272.68%
                              84           25      4.11%   9276.79%
                              86           59      9.71%   9286.50%
                              88            7      1.15%   9287.65%
                              90           23      3.79%   9291.44%
                              92           12      1.98%   9293.41%
                              94           21      3.46%   9296.87%
                              96           16      2.63%   9299.50%
                              98            8      1.32%   9300.82%
system.cpu0.IQ:residence:IntMult.overflows         4248                      
system.cpu0.IQ:residence:IntMult.max_value          496                      
system.cpu0.IQ:residence:IntMult.end_dist

system.cpu0.IQ:residence:IntDiv.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:IntDiv.samples             0                      
system.cpu0.IQ:residence:IntDiv.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.IQ:residence:IntDiv.max_value            0                      
system.cpu0.IQ:residence:IntDiv.end_dist

system.cpu0.IQ:residence:FloatAdd.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:FloatAdd.samples         6447                      
system.cpu0.IQ:residence:FloatAdd.min_value            1                      
                               0         1051   1630.22%   1630.22%
                               2          809   1254.85%   2885.06%
                               4         1139   1766.71%   4651.78%
                               6         1457   2259.97%   6911.74%
                               8            1      1.55%   6913.29%
                              10            2      3.10%   6916.40%
                              12            1      1.55%   6917.95%
                              14            1      1.55%   6919.50%
                              16           29     44.98%   6964.48%
                              18           31     48.08%   7012.56%
                              20            4      6.20%   7018.77%
                              22            2      3.10%   7021.87%
                              24         1860   2885.06%   9906.93%
                              26           12     18.61%   9925.55%
                              28            0      0.00%   9925.55%
                              30            0      0.00%   9925.55%
                              32            0      0.00%   9925.55%
                              34            1      1.55%   9927.10%
                              36            0      0.00%   9927.10%
                              38            0      0.00%   9927.10%
                              40            0      0.00%   9927.10%
                              42            0      0.00%   9927.10%
                              44            0      0.00%   9927.10%
                              46            0      0.00%   9927.10%
                              48            0      0.00%   9927.10%
                              50            0      0.00%   9927.10%
                              52            0      0.00%   9927.10%
                              54            1      1.55%   9928.65%
                              56            0      0.00%   9928.65%
                              58            0      0.00%   9928.65%
                              60            0      0.00%   9928.65%
                              62            1      1.55%   9930.20%
                              64            2      3.10%   9933.30%
                              66           34     52.74%   9986.04%
                              68            0      0.00%   9986.04%
                              70            0      0.00%   9986.04%
                              72            0      0.00%   9986.04%
                              74            0      0.00%   9986.04%
                              76            0      0.00%   9986.04%
                              78            0      0.00%   9986.04%
                              80            0      0.00%   9986.04%
                              82            0      0.00%   9986.04%
                              84            0      0.00%   9986.04%
                              86            0      0.00%   9986.04%
                              88            0      0.00%   9986.04%
                              90            0      0.00%   9986.04%
                              92            0      0.00%   9986.04%
                              94            2      3.10%   9989.14%
                              96            0      0.00%   9989.14%
                              98            0      0.00%   9989.14%
system.cpu0.IQ:residence:FloatAdd.overflows            7                      
system.cpu0.IQ:residence:FloatAdd.max_value          478                      
system.cpu0.IQ:residence:FloatAdd.end_dist

system.cpu0.IQ:residence:FloatCmp.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:FloatCmp.samples            0                      
system.cpu0.IQ:residence:FloatCmp.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.IQ:residence:FloatCmp.max_value            0                      
system.cpu0.IQ:residence:FloatCmp.end_dist

system.cpu0.IQ:residence:FloatCvt.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:FloatCvt.samples            0                      
system.cpu0.IQ:residence:FloatCvt.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.IQ:residence:FloatCvt.max_value            0                      
system.cpu0.IQ:residence:FloatCvt.end_dist

system.cpu0.IQ:residence:FloatMult.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:FloatMult.samples            0                      
system.cpu0.IQ:residence:FloatMult.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.IQ:residence:FloatMult.max_value            0                      
system.cpu0.IQ:residence:FloatMult.end_dist

system.cpu0.IQ:residence:FloatDiv.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:FloatDiv.samples           64                      
system.cpu0.IQ:residence:FloatDiv.min_value            1                      
                               0            1    156.25%    156.25%
                               2            1    156.25%    312.50%
                               4            0      0.00%    312.50%
                               6           60   9375.00%   9687.50%
                               8            0      0.00%   9687.50%
                              10            0      0.00%   9687.50%
                              12            0      0.00%   9687.50%
                              14            0      0.00%   9687.50%
                              16            0      0.00%   9687.50%
                              18            0      0.00%   9687.50%
                              20            0      0.00%   9687.50%
                              22            1    156.25%   9843.75%
                              24            0      0.00%   9843.75%
                              26            0      0.00%   9843.75%
                              28            0      0.00%   9843.75%
                              30            0      0.00%   9843.75%
                              32            0      0.00%   9843.75%
                              34            0      0.00%   9843.75%
                              36            0      0.00%   9843.75%
                              38            0      0.00%   9843.75%
                              40            0      0.00%   9843.75%
                              42            0      0.00%   9843.75%
                              44            0      0.00%   9843.75%
                              46            0      0.00%   9843.75%
                              48            0      0.00%   9843.75%
                              50            0      0.00%   9843.75%
                              52            0      0.00%   9843.75%
                              54            0      0.00%   9843.75%
                              56            0      0.00%   9843.75%
                              58            0      0.00%   9843.75%
                              60            0      0.00%   9843.75%
                              62            0      0.00%   9843.75%
                              64            0      0.00%   9843.75%
                              66            0      0.00%   9843.75%
                              68            0      0.00%   9843.75%
                              70            0      0.00%   9843.75%
                              72            0      0.00%   9843.75%
                              74            0      0.00%   9843.75%
                              76            0      0.00%   9843.75%
                              78            0      0.00%   9843.75%
                              80            0      0.00%   9843.75%
                              82            0      0.00%   9843.75%
                              84            0      0.00%   9843.75%
                              86            0      0.00%   9843.75%
                              88            0      0.00%   9843.75%
                              90            0      0.00%   9843.75%
                              92            0      0.00%   9843.75%
                              94            0      0.00%   9843.75%
                              96            1    156.25%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu0.IQ:residence:FloatDiv.max_value           97                      
system.cpu0.IQ:residence:FloatDiv.end_dist

system.cpu0.IQ:residence:FloatSqrt.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:FloatSqrt.samples            0                      
system.cpu0.IQ:residence:FloatSqrt.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.IQ:residence:FloatSqrt.max_value            0                      
system.cpu0.IQ:residence:FloatSqrt.end_dist

system.cpu0.IQ:residence:MemRead.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:MemRead.samples     19776757                      
system.cpu0.IQ:residence:MemRead.min_value            1                      
                               0      3859889   1951.73%   1951.73%
                               2      5288637   2674.17%   4625.90%
                               4      1941282    981.60%   5607.50%
                               6      1361610    688.49%   6295.99%
                               8       858791    434.24%   6730.23%
                              10       891709    450.89%   7181.12%
                              12       540302    273.20%   7454.32%
                              14       435049    219.98%   7674.30%
                              16       288992    146.13%   7820.42%
                              18       209953    106.16%   7926.58%
                              20       141528     71.56%   7998.15%
                              22       134580     68.05%   8066.20%
                              24       156781     79.28%   8145.47%
                              26       151398     76.55%   8222.03%
                              28       131614     66.55%   8288.58%
                              30       122387     61.88%   8350.46%
                              32       105728     53.46%   8403.92%
                              34       105184     53.19%   8457.11%
                              36       102656     51.91%   8509.01%
                              38        62832     31.77%   8540.78%
                              40        77534     39.20%   8579.99%
                              42        31299     15.83%   8595.82%
                              44        32985     16.68%   8612.49%
                              46        84915     42.94%   8655.43%
                              48        39613     20.03%   8675.46%
                              50        81841     41.38%   8716.84%
                              52        33132     16.75%   8733.60%
                              54        34111     17.25%   8750.84%
                              56        32479     16.42%   8767.27%
                              58        23398     11.83%   8779.10%
                              60        52252     26.42%   8805.52%
                              62        30405     15.37%   8820.89%
                              64        93735     47.40%   8868.29%
                              66        23412     11.84%   8880.13%
                              68        26194     13.24%   8893.37%
                              70        27223     13.77%   8907.14%
                              72        26450     13.37%   8920.51%
                              74        19683      9.95%   8930.46%
                              76        18696      9.45%   8939.92%
                              78        22038     11.14%   8951.06%
                              80        29626     14.98%   8966.04%
                              82        14041      7.10%   8973.14%
                              84        12649      6.40%   8979.54%
                              86        18284      9.25%   8988.78%
                              88        12871      6.51%   8995.29%
                              90        27304     13.81%   9009.10%
                              92        21158     10.70%   9019.80%
                              94         7709      3.90%   9023.69%
                              96         9455      4.78%   9028.47%
                              98        11645      5.89%   9034.36%
system.cpu0.IQ:residence:MemRead.overflows      1909718                      
system.cpu0.IQ:residence:MemRead.max_value        17495                      
system.cpu0.IQ:residence:MemRead.end_dist

system.cpu0.IQ:residence:MemWrite.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:MemWrite.samples     12556236                      
system.cpu0.IQ:residence:MemWrite.min_value            1                      
                               0      2057255   1638.43%   1638.43%
                               2      3771480   3003.67%   4642.10%
                               4      1527825   1216.79%   5858.89%
                               6      1048105    834.73%   6693.62%
                               8       680974    542.34%   7235.96%
                              10       546281    435.07%   7671.02%
                              12       432185    344.20%   8015.22%
                              14       297090    236.61%   8251.83%
                              16       308763    245.90%   8497.74%
                              18       151001    120.26%   8618.00%
                              20       128910    102.67%   8720.66%
                              22       114958     91.55%   8812.22%
                              24       121625     96.86%   8909.08%
                              26        84945     67.65%   8976.73%
                              28        79892     63.63%   9040.36%
                              30        66059     52.61%   9092.97%
                              32        52786     42.04%   9135.01%
                              34        51776     41.24%   9176.25%
                              36        41217     32.83%   9209.07%
                              38        30470     24.27%   9233.34%
                              40        33574     26.74%   9260.08%
                              42        21120     16.82%   9276.90%
                              44        16642     13.25%   9290.15%
                              46        38916     30.99%   9321.14%
                              48        12863     10.24%   9331.39%
                              50       115543     92.02%   9423.41%
                              52        26643     21.22%   9444.63%
                              54        19223     15.31%   9459.94%
                              56        23970     19.09%   9479.03%
                              58        27257     21.71%   9500.74%
                              60        28927     23.04%   9523.77%
                              62        29317     23.35%   9547.12%
                              64       164231    130.80%   9677.92%
                              66        11428      9.10%   9687.02%
                              68         9588      7.64%   9694.66%
                              70        11393      9.07%   9703.73%
                              72         9337      7.44%   9711.17%
                              74        14761     11.76%   9722.92%
                              76        11312      9.01%   9731.93%
                              78        25686     20.46%   9752.39%
                              80        26884     21.41%   9773.80%
                              82         5696      4.54%   9778.33%
                              84        10249      8.16%   9786.50%
                              86         7477      5.95%   9792.45%
                              88         3560      2.84%   9795.29%
                              90         3554      2.83%   9798.12%
                              92         3364      2.68%   9800.80%
                              94         3376      2.69%   9803.49%
                              96         4657      3.71%   9807.19%
                              98         3895      3.10%   9810.30%
system.cpu0.IQ:residence:MemWrite.overflows       238196                      
system.cpu0.IQ:residence:MemWrite.max_value        17503                      
system.cpu0.IQ:residence:MemWrite.end_dist

system.cpu0.IQ:residence:IprAccess.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:IprAccess.samples       907681                      
system.cpu0.IQ:residence:IprAccess.min_value            1                      
                               0       221851   2444.15%   2444.15%
                               2        38881    428.36%   2872.51%
                               4       175681   1935.49%   4808.00%
                               6       186075   2050.00%   6858.00%
                               8        32453    357.54%   7215.54%
                              10       149588   1648.02%   8863.57%
                              12        19774    217.85%   9081.42%
                              14        15365    169.28%   9250.69%
                              16         7275     80.15%   9330.84%
                              18        10135    111.66%   9442.50%
                              20         9206    101.42%   9543.93%
                              22         4923     54.24%   9598.16%
                              24         8485     93.48%   9691.64%
                              26         7199     79.31%   9770.95%
                              28         3132     34.51%   9805.46%
                              30          603      6.64%   9812.10%
                              32         1603     17.66%   9829.76%
                              34         1546     17.03%   9846.80%
                              36         1619     17.84%   9864.63%
                              38          548      6.04%   9870.67%
                              40         1558     17.16%   9887.84%
                              42          470      5.18%   9893.01%
                              44          958     10.55%   9903.57%
                              46          448      4.94%   9908.50%
                              48         1178     12.98%   9921.48%
                              50          349      3.84%   9925.33%
                              52          849      9.35%   9934.68%
                              54          541      5.96%   9940.64%
                              56          403      4.44%   9945.08%
                              58          319      3.51%   9948.59%
                              60          456      5.02%   9953.62%
                              62          216      2.38%   9956.00%
                              64          725      7.99%   9963.99%
                              66          482      5.31%   9969.30%
                              68          218      2.40%   9971.70%
                              70          276      3.04%   9974.74%
                              72          146      1.61%   9976.35%
                              74          183      2.02%   9978.36%
                              76           59      0.65%   9979.01%
                              78           97      1.07%   9980.08%
                              80          105      1.16%   9981.24%
                              82          122      1.34%   9982.58%
                              84          215      2.37%   9984.95%
                              86           60      0.66%   9985.61%
                              88          100      1.10%   9986.71%
                              90           54      0.59%   9987.31%
                              92           45      0.50%   9987.80%
                              94           53      0.58%   9988.39%
                              96           42      0.46%   9988.85%
                              98           47      0.52%   9989.37%
system.cpu0.IQ:residence:IprAccess.overflows          965                      
system.cpu0.IQ:residence:IprAccess.max_value          371                      
system.cpu0.IQ:residence:IprAccess.end_dist

system.cpu0.IQ:residence:InstPrefetch.start_dist                     # cycles from dispatch to issue
system.cpu0.IQ:residence:InstPrefetch.samples            0                      
system.cpu0.IQ:residence:InstPrefetch.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.IQ:residence:InstPrefetch.max_value            0                      
system.cpu0.IQ:residence:InstPrefetch.end_dist

system.cpu0.ISSUE:(null)_delay.start_dist                      # cycles from operands ready to issue
system.cpu0.ISSUE:(null)_delay.samples           4226                      
system.cpu0.ISSUE:(null)_delay.min_value            1                      
                               0         4112   9730.24%   9730.24%
                               2          113    267.39%   9997.63%
                               4            0      0.00%   9997.63%
                               6            0      0.00%   9997.63%
                               8            1      2.37%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu0.ISSUE:(null)_delay.max_value            9                      
system.cpu0.ISSUE:(null)_delay.end_dist

system.cpu0.ISSUE:IntAlu_delay.start_dist                      # cycles from operands ready to issue
system.cpu0.ISSUE:IntAlu_delay.samples      758931823                      
system.cpu0.ISSUE:IntAlu_delay.min_value            0                      
                               0    516332632   6803.41%   6803.41%
                               2      1947278     25.66%   6829.07%
                               4       364470      4.80%   6833.87%
                               6       150037      1.98%   6835.85%
                               8     62182515    819.34%   7655.19%
                              10    177944601   2344.67%   9999.86%
                              12        10290      0.14%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu0.ISSUE:IntAlu_delay.max_value           12                      
system.cpu0.ISSUE:IntAlu_delay.end_dist

system.cpu0.ISSUE:IntMult_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:IntMult_delay.samples         60757                      
system.cpu0.ISSUE:IntMult_delay.min_value            0                      
                               0        60743   9997.70%   9997.70%
                               2            7      1.15%   9998.85%
                               4            7      1.15%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu0.ISSUE:IntMult_delay.max_value            4                      
system.cpu0.ISSUE:IntMult_delay.end_dist

system.cpu0.ISSUE:IntDiv_delay.start_dist                      # cycles from operands ready to issue
system.cpu0.ISSUE:IntDiv_delay.samples              0                      
system.cpu0.ISSUE:IntDiv_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.ISSUE:IntDiv_delay.max_value            0                      
system.cpu0.ISSUE:IntDiv_delay.end_dist

system.cpu0.ISSUE:FloatAdd_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:FloatAdd_delay.samples         6447                      
system.cpu0.ISSUE:FloatAdd_delay.min_value            0                      
                               0         4290   6654.26%   6654.26%
                               2          809   1254.85%   7909.11%
                               4          998   1548.01%   9457.11%
                               6          350    542.89%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu0.ISSUE:FloatAdd_delay.max_value            7                      
system.cpu0.ISSUE:FloatAdd_delay.end_dist

system.cpu0.ISSUE:FloatCmp_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:FloatCmp_delay.samples            0                      
system.cpu0.ISSUE:FloatCmp_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.ISSUE:FloatCmp_delay.max_value            0                      
system.cpu0.ISSUE:FloatCmp_delay.end_dist

system.cpu0.ISSUE:FloatCvt_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:FloatCvt_delay.samples            0                      
system.cpu0.ISSUE:FloatCvt_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.ISSUE:FloatCvt_delay.max_value            0                      
system.cpu0.ISSUE:FloatCvt_delay.end_dist

system.cpu0.ISSUE:FloatMult_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:FloatMult_delay.samples            0                      
system.cpu0.ISSUE:FloatMult_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.ISSUE:FloatMult_delay.max_value            0                      
system.cpu0.ISSUE:FloatMult_delay.end_dist

system.cpu0.ISSUE:FloatDiv_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:FloatDiv_delay.samples           64                      
system.cpu0.ISSUE:FloatDiv_delay.min_value            0                      
                               0           64  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu0.ISSUE:FloatDiv_delay.max_value            1                      
system.cpu0.ISSUE:FloatDiv_delay.end_dist

system.cpu0.ISSUE:FloatSqrt_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:FloatSqrt_delay.samples            0                      
system.cpu0.ISSUE:FloatSqrt_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.ISSUE:FloatSqrt_delay.max_value            0                      
system.cpu0.ISSUE:FloatSqrt_delay.end_dist

system.cpu0.ISSUE:MemRead_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:MemRead_delay.samples      19776757                      
system.cpu0.ISSUE:MemRead_delay.min_value            0                      
                               0     18054132   9128.96%   9128.96%
                               2      1251510    632.82%   9761.78%
                               4       285330    144.28%   9906.06%
                               6        99407     50.26%   9956.32%
                               8        57679     29.17%   9985.49%
                              10        26805     13.55%   9999.04%
                              12          390      0.20%   9999.24%
                              14           25      0.01%   9999.25%
                              16           22      0.01%   9999.26%
                              18            9      0.00%   9999.27%
                              20           20      0.01%   9999.28%
                              22           33      0.02%   9999.29%
                              24          163      0.08%   9999.38%
                              26           32      0.02%   9999.39%
                              28           50      0.03%   9999.42%
                              30           41      0.02%   9999.44%
                              32           63      0.03%   9999.47%
                              34           95      0.05%   9999.52%
                              36           78      0.04%   9999.56%
                              38           27      0.01%   9999.57%
                              40           14      0.01%   9999.58%
                              42           16      0.01%   9999.59%
                              44           16      0.01%   9999.60%
                              46           12      0.01%   9999.60%
                              48            9      0.00%   9999.61%
                              50            2      0.00%   9999.61%
                              52            9      0.00%   9999.61%
                              54           17      0.01%   9999.62%
                              56           16      0.01%   9999.63%
                              58           13      0.01%   9999.63%
                              60           13      0.01%   9999.64%
                              62            6      0.00%   9999.64%
                              64           14      0.01%   9999.65%
                              66           18      0.01%   9999.66%
                              68            9      0.00%   9999.67%
                              70            8      0.00%   9999.67%
                              72            4      0.00%   9999.67%
                              74            3      0.00%   9999.67%
                              76            9      0.00%   9999.68%
                              78            3      0.00%   9999.68%
                              80            1      0.00%   9999.68%
                              82            0      0.00%   9999.68%
                              84            5      0.00%   9999.68%
                              86            2      0.00%   9999.68%
                              88            2      0.00%   9999.68%
                              90            4      0.00%   9999.69%
                              92            0      0.00%   9999.69%
                              94            0      0.00%   9999.69%
                              96            0      0.00%   9999.69%
                              98            2      0.00%   9999.69%
system.cpu0.ISSUE:MemRead_delay.overflows          619                      
system.cpu0.ISSUE:MemRead_delay.max_value          950                      
system.cpu0.ISSUE:MemRead_delay.end_dist

system.cpu0.ISSUE:MemWrite_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:MemWrite_delay.samples     12556236                      
system.cpu0.ISSUE:MemWrite_delay.min_value            0                      
                               0     11614164   9249.72%   9249.72%
                               2       725407    577.73%   9827.44%
                               4       150968    120.23%   9947.68%
                               6        49095     39.10%   9986.78%
                               8        14179     11.29%   9998.07%
                              10         2119      1.69%   9999.76%
                              12            6      0.00%   9999.76%
                              14           14      0.01%   9999.77%
                              16            5      0.00%   9999.78%
                              18            3      0.00%   9999.78%
                              20            4      0.00%   9999.78%
                              22           23      0.02%   9999.80%
                              24            5      0.00%   9999.81%
                              26            6      0.00%   9999.81%
                              28           15      0.01%   9999.82%
                              30            1      0.00%   9999.82%
                              32           22      0.02%   9999.84%
                              34           34      0.03%   9999.87%
                              36            4      0.00%   9999.87%
                              38            4      0.00%   9999.87%
                              40            4      0.00%   9999.88%
                              42            3      0.00%   9999.88%
                              44            0      0.00%   9999.88%
                              46            1      0.00%   9999.88%
                              48            0      0.00%   9999.88%
                              50            0      0.00%   9999.88%
                              52            1      0.00%   9999.88%
                              54            2      0.00%   9999.88%
                              56            3      0.00%   9999.89%
                              58            3      0.00%   9999.89%
                              60            0      0.00%   9999.89%
                              62            0      0.00%   9999.89%
                              64            2      0.00%   9999.89%
                              66            5      0.00%   9999.89%
                              68            4      0.00%   9999.90%
                              70            0      0.00%   9999.90%
                              72            0      0.00%   9999.90%
                              74            0      0.00%   9999.90%
                              76            0      0.00%   9999.90%
                              78            0      0.00%   9999.90%
                              80            0      0.00%   9999.90%
                              82            0      0.00%   9999.90%
                              84            0      0.00%   9999.90%
                              86            0      0.00%   9999.90%
                              88            0      0.00%   9999.90%
                              90            1      0.00%   9999.90%
                              92            0      0.00%   9999.90%
                              94            0      0.00%   9999.90%
                              96            1      0.00%   9999.90%
                              98            1      0.00%   9999.90%
system.cpu0.ISSUE:MemWrite_delay.overflows          127                      
system.cpu0.ISSUE:MemWrite_delay.max_value          948                      
system.cpu0.ISSUE:MemWrite_delay.end_dist

system.cpu0.ISSUE:IprAccess_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:IprAccess_delay.samples       907681                      
system.cpu0.ISSUE:IprAccess_delay.min_value            0                      
                               0       281867   3105.35%   3105.35%
                               2       189150   2083.88%   5189.23%
                               4       182869   2014.68%   7203.92%
                               6        42337    466.43%   7670.35%
                               8        29877    329.16%   7999.51%
                              10       137838   1518.57%   9518.08%
                              12        18255    201.12%   9719.20%
                              14         4562     50.26%   9769.46%
                              16         4213     46.41%   9815.87%
                              18         2423     26.69%   9842.57%
                              20         5271     58.07%   9900.64%
                              22         2655     29.25%   9929.89%
                              24         1616     17.80%   9947.69%
                              26         4505     49.63%   9997.32%
                              28           57      0.63%   9997.95%
                              30           43      0.47%   9998.42%
                              32           51      0.56%   9998.99%
                              34           43      0.47%   9999.46%
                              36            2      0.02%   9999.48%
                              38            4      0.04%   9999.53%
                              40           43      0.47%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu0.ISSUE:IprAccess_delay.max_value           41                      
system.cpu0.ISSUE:IprAccess_delay.end_dist

system.cpu0.ISSUE:InstPrefetch_delay.start_dist                     # cycles from operands ready to issue
system.cpu0.ISSUE:InstPrefetch_delay.samples            0                      
system.cpu0.ISSUE:InstPrefetch_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu0.ISSUE:InstPrefetch_delay.max_value            0                      
system.cpu0.ISSUE:InstPrefetch_delay.end_dist

system.cpu0.ISSUE:FU_type_0                 791844789                       # Type of FU issued
system.cpu0.ISSUE:FU_type_0.start_dist
                          (null)         4226      0.00%            # Type of FU issued
                          IntAlu    775583311     97.95%            # Type of FU issued
                         IntMult        60757      0.01%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd         6447      0.00%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv           64      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead      9591966      1.21%            # Type of FU issued
                        MemWrite      5690337      0.72%            # Type of FU issued
                       IprAccess       907681      0.11%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu0.ISSUE:FU_type_0.end_dist
system.cpu0.ISSUE:IQ_0:fu_full.start_dist
                          (null)            0      0.00%           
                          IntAlu   2106422428     99.74%           
                         IntMult            2      0.00%           
                          IntDiv            0      0.00%           
                        FloatAdd            0      0.00%           
                        FloatCmp            0      0.00%           
                        FloatCvt            0      0.00%           
                       FloatMult            0      0.00%           
                        FloatDiv            0      0.00%           
                       FloatSqrt            0      0.00%           
                         MemRead      1590563      0.08%           
                        MemWrite       214303      0.01%           
                       IprAccess      3584850      0.17%           
                    InstPrefetch            0      0.00%           
system.cpu0.ISSUE:IQ_0:fu_full.end_dist
system.cpu0.ISSUE:MSIPC                      0.001156                       # Misspec issue rate
system.cpu0.ISSUE:addr_loads                    92416                       # number of invalid-address loads
system.cpu0.ISSUE:addr_swpfs                     1879                       # number of invalid-address SW prefetches
system.cpu0.ISSUE:branches                  250143158                       # Number of branches issued
system.cpu0.ISSUE:count                     776357793                       # number of insts issued
system.cpu0.ISSUE:fu_busy_cnt              2111812146                       # FU busy when requested
system.cpu0.ISSUE:fu_busy_rate               2.720153                       # FU busy rate (busy events/executed inst)
system.cpu0.ISSUE:fu_full.start_dist
                          (null)            0      0.00%            # attempts to use FU when none available
                          IntAlu   2106422428     99.74%            # attempts to use FU when none available
                         IntMult            2      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead      1590563      0.08%            # attempts to use FU when none available
                        MemWrite       214303      0.01%            # attempts to use FU when none available
                       IprAccess      3584850      0.17%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu0.ISSUE:fu_full.end_dist
system.cpu0.ISSUE:issued_per_cycle          140858155                       # Number of insts issued each cycle
system.cpu0.ISSUE:issued_per_cycle.start_dist
                               0      1863097      1.32%            # Number of insts issued each cycle
                               1      4488223      3.19%            # Number of insts issued each cycle
                               2      3028841      2.15%            # Number of insts issued each cycle
                               3      2383341      1.69%            # Number of insts issued each cycle
                               4      1402080      1.00%            # Number of insts issued each cycle
                               5      1969593      1.40%            # Number of insts issued each cycle
                               6    122610380     87.05%            # Number of insts issued each cycle
                               7      1471302      1.04%            # Number of insts issued each cycle
                               8      1641298      1.17%            # Number of insts issued each cycle
system.cpu0.ISSUE:issued_per_cycle.end_dist
system.cpu0.ISSUE:loads                      10184791                       # number of load insts issued
system.cpu0.ISSUE:lsq_inv_rate                      0                       # Early LSQ issues per cycle
system.cpu0.ISSUE:lsq_invert                        0                       # Number of times LSQ instruction issued early
system.cpu0.ISSUE:misspec_cnt                 8500504                       # Number of misspeculated insts issued
system.cpu0.ISSUE:nop                         8600849                       # number of nop insts issued
system.cpu0.ISSUE:op_count                  792243991                       # number of insts issued
system.cpu0.ISSUE:op_rate                    0.107752                       # Operation issue rate
system.cpu0.ISSUE:rate                       0.105591                       # Inst issue rate
system.cpu0.ISSUE:refs                       16651488                       # number of memory reference insts issued
system.cpu0.ISSUE:stores                      6466697                       # Number of stores issued
system.cpu0.ISSUE:swp                          212144                       # number of swp insts issued
system.cpu0.ISSUE:unissued_cause.start_dist
                          (null)            0      0.00%            # Reason ready instruction not issued
                          IntAlu   2106422428     99.75%            # Reason ready instruction not issued
                         IntMult            2      0.00%            # Reason ready instruction not issued
                          IntDiv            0      0.00%            # Reason ready instruction not issued
                        FloatAdd            0      0.00%            # Reason ready instruction not issued
                        FloatCmp            0      0.00%            # Reason ready instruction not issued
                        FloatCvt            0      0.00%            # Reason ready instruction not issued
                       FloatMult            0      0.00%            # Reason ready instruction not issued
                        FloatDiv            0      0.00%            # Reason ready instruction not issued
                       FloatSqrt            0      0.00%            # Reason ready instruction not issued
                         MemRead      1590563      0.08%            # Reason ready instruction not issued
                        MemWrite          690      0.00%            # Reason ready instruction not issued
                       IprAccess      3584850      0.17%            # Reason ready instruction not issued
                    InstPrefetch            0      0.00%            # Reason ready instruction not issued
                  DCache_Blocked       100135      0.00%            # Reason ready instruction not issued
                       Too_Young            0      0.00%            # Reason ready instruction not issued
system.cpu0.ISSUE:unissued_cause.end_dist
system.cpu0.LSQ:RQ:rdy_inst                  17996206                       # Number of ready instructions (cum)
system.cpu0.LSQ:RQ:rdy_inst_dist_0_mean      0.002448                       # standard deviation of ready rate
system.cpu0.LSQ:RQ:rdy_inst_dist_0_stdev     0.097786                       # standard deviation of ready rate
**Ignore: system.cpu0.LSQ:RQ:rdy_inst_dist_0_TOT   7352469842                       # standard deviation of ready rate
system.cpu0.LSQ:RQ:rdy_rate                  0.002448                       # Number of ready insts per cycle
system.cpu0.LSQ:RQ:rdy_x_count               15715611                       # number of insts that become ready (cum)
system.cpu0.LSQ:RQ:rdy_x_max                       32                       # largest number of insts that become ready
system.cpu0.LSQ:RQ:rdy_x_rate                0.002137                       # number of insts that become ready per cycle
system.cpu0.LSQ:avg_residency                0.931746                       # Average IQ residency
system.cpu0.LSQ:blocked_loads                32644491                       # number of ready loads not issued due to memory disambiguation
system.cpu0.LSQ:cum_num_insts               723368472                       # Total occupancy
system.cpu0.LSQ:current_count                       0                       # Occupancy this cycle
system.cpu0.LSQ:empty_count                7303412923                       # Number of empty cycles
system.cpu0.LSQ:empty_rate                  99.332783                       # Fraction of cycles empty
system.cpu0.LSQ:forw_loads                        222                       # number of loads forwarded via LSQ
system.cpu0.LSQ:full_count                          0                       # Number of full cycles
system.cpu0.LSQ:full_rate                           0                       # Fraction of cycles full
system.cpu0.LSQ:occ_dist_0.start_dist                          # IQ Occupancy per cycle
system.cpu0.LSQ:occ_dist_0.samples         7352469842                      
system.cpu0.LSQ:occ_dist_0.min_value                0                      
                               0   7305927108              9936.70%
                               2      3632388              9941.64%
                               4      2683991              9945.29%
                               6      1954248              9947.95%
                               8      1842692              9950.45%
                              10      1520664              9952.52%
                              12      1132282              9954.06%
                              14      1034752              9955.47%
                              16     22153696              9985.60%
                              18       683820              9986.53%
                              20       683696              9987.46%
                              22      3985466              9992.88%
                              24       566906              9993.65%
                              26       390597              9994.18%
                              28       847087              9995.33%
                              30       657824              9996.23%
                              32      2772625             10000.00%
system.cpu0.LSQ:occ_dist_0.max_value               32                      
system.cpu0.LSQ:occ_dist_0.end_dist

system.cpu0.LSQ:occ_rate                     0.098384                       # Average occupancy
system.cpu0.LSQ:peak_occupancy                     32                       # Peak IQ occupancy
system.cpu0.REG:fp:full                             0                       # number of cycles where there were no FP registers
system.cpu0.REG:fp:occ                        2868892                       # Cumulative count of FP register usage
system.cpu0.REG:fp:occ_rate                         0                       # Average FP register usage
system.cpu0.REG:int:full                            0                       # number of cycles where there were no INT registers
system.cpu0.REG:int:occ                    9724068205                       # Cumulative count of INT register usage
system.cpu0.REG:int:occ_rate                        1                       # Average INT register usage
system.cpu0.ROB:cap_events                          0                       # number of cycles where ROB cap was active
system.cpu0.ROB:cap_inst                            0                       # number of instructions held up by ROB cap
system.cpu0.ROB:current_count                       0                       # Current ROB occupancy
system.cpu0.ROB:full_count                    6009771                       # number of cycles where ROB was full
system.cpu0.ROB:full_rate                    0.000817                       # ROB full per cycle
system.cpu0.ROB:occ_dist_0.start_dist                          # ROB Occupancy per cycle
system.cpu0.ROB:occ_dist_0.samples         7352469842                      
system.cpu0.ROB:occ_dist_0.min_value                0                      
                               0   7173660307              9756.80%
                               2      1657483              9759.06%
                               4       864152              9760.23%
                               6      1254178              9761.94%
                               8      1800024              9764.39%
                              10      1136195              9765.93%
                              12      1174485              9767.53%
                              14       871080              9768.71%
                              16       691390              9769.65%
                              18       736611              9770.66%
                              20       799827              9771.74%
                              22       712399              9772.71%
                              24       457536              9773.34%
                              26       394939              9773.87%
                              28       705393              9774.83%
                              30       473337              9775.48%
                              32       322907              9775.92%
                              34       309892              9776.34%
                              36       350453              9776.81%
                              38       368754              9777.31%
                              40       258657              9777.67%
                              42       295960              9778.07%
                              44       280988              9778.45%
                              46       331106              9778.90%
                              48       232330              9779.22%
                              50       268452              9779.58%
                              52       245332              9779.92%
                              54       234554              9780.24%
                              56       199287              9780.51%
                              58       199496              9780.78%
                              60       226656              9781.09%
                              62       217628              9781.38%
                              64       229462              9781.69%
                              66       329656              9782.14%
                              68      3049062              9786.29%
                              70       729503              9787.28%
                              72       696338              9788.23%
                              74       559263              9788.99%
                              76       334954              9789.45%
                              78     29151458              9829.09%
                              80     58256319              9908.33%
                              82     33875923              9954.40%
                              84       411409              9954.96%
                              86       256710              9955.31%
                              88       264274              9955.67%
                              90       257784              9956.02%
                              92       252638              9956.36%
                              94       354392              9956.85%
                              96     20647681              9984.93%
                              98      1366143              9986.79%
                             100       366780              9987.29%
                             102       265681              9987.65%
                             104       200917              9987.92%
                             106       255799              9988.27%
                             108       193978              9988.53%
                             110       204454              9988.81%
                             112       201615              9989.08%
                             114       526869              9989.80%
                             116       180747              9990.05%
                             118       168213              9990.28%
                             120       167773              9990.50%
                             122       233259              9990.82%
                             124       245895              9991.16%
                             126       464559              9991.79%
                             128      6038546             10000.00%
system.cpu0.ROB:occ_dist_0.max_value              128                      
system.cpu0.ROB:occ_dist_0.end_dist

system.cpu0.ROB:occ_rate                     1.912854                       # ROB occupancy rate
system.cpu0.ROB:occupancy                 14064204721                       # system.cpu0.ROB occupancy (cumulative)
system.cpu0.SB:RQ:rdy_inst                    6423774                       # Number of ready instructions (cum)
system.cpu0.SB:RQ:rdy_inst_dist_0_mean       0.000874                       # standard deviation of ready rate
system.cpu0.SB:RQ:rdy_inst_dist_0_stdev      0.056177                       # standard deviation of ready rate
**Ignore: system.cpu0.SB:RQ:rdy_inst_dist_0_TOT   7352469842                       # standard deviation of ready rate
system.cpu0.SB:RQ:rdy_rate                   0.000874                       # Number of ready insts per cycle
system.cpu0.SB:RQ:rdy_x_count                 5682886                       # number of insts that become ready (cum)
system.cpu0.SB:RQ:rdy_x_max                        11                       # largest number of insts that become ready
system.cpu0.SB:RQ:rdy_x_rate                 0.000773                       # number of insts that become ready per cycle
system.cpu0.SB:full_count                     3457698                       # store buffer full events (cumulative)
system.cpu0.SB:full_rate                     0.000470                       # store buffer full rate
system.cpu0.SB:occ_rate                      0.023512                       # store buffer occupancy rate
system.cpu0.SB:occupancy                    172868330                       # store buffer occupancy (cumulative)
system.cpu0.SB:write_barrier_pending_cycles        86414                       # number of cycles write barriers were pending
system.cpu0.SB:write_barriers                    6695                       # number of write barrier operations
system.cpu0.WB:consumers                    545280354                       # num instructions consuming a value
system.cpu0.WB:count                        790331133                       # cumulative count of insts written-back
system.cpu0.WB:fanout                        0.980472                       # average fanout of values written-back
system.cpu0.WB:penalized                            0                       # number of instrctions required to write to 'other' IQ
system.cpu0.WB:penalized_rate                       0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.WB:pred_error.start_dist                           # error in predicted writeback times
system.cpu0.WB:pred_error.samples           790331133                      
system.cpu0.WB:pred_error.min_value               145                      
                             -10            0      0.00%      0.00%
                              -9            0      0.00%      0.00%
                              -8            0      0.00%      0.00%
                              -7            0      0.00%      0.00%
                              -6            0      0.00%      0.00%
                              -5            0      0.00%      0.00%
                              -4            0      0.00%      0.00%
                              -3            0      0.00%      0.00%
                              -2            0      0.00%      0.00%
                              -1            0      0.00%      0.00%
                               0            0      0.00%      0.00%
                               1            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               3            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               5            0      0.00%      0.00%
                               6            0      0.00%      0.00%
                               7            0      0.00%      0.00%
                               8            0      0.00%      0.00%
                               9            0      0.00%      0.00%
                              10            0      0.00%      0.00%
                              11            0      0.00%      0.00%
                              12            0      0.00%      0.00%
                              13            0      0.00%      0.00%
                              14            0      0.00%      0.00%
                              15            0      0.00%      0.00%
                              16            0      0.00%      0.00%
                              17            0      0.00%      0.00%
                              18            0      0.00%      0.00%
                              19            0      0.00%      0.00%
                              20            0      0.00%      0.00%
                              21            0      0.00%      0.00%
                              22            0      0.00%      0.00%
                              23            0      0.00%      0.00%
                              24            0      0.00%      0.00%
                              25            0      0.00%      0.00%
                              26            0      0.00%      0.00%
                              27            0      0.00%      0.00%
                              28            0      0.00%      0.00%
                              29            0      0.00%      0.00%
                              30            0      0.00%      0.00%
                              31            0      0.00%      0.00%
                              32            0      0.00%      0.00%
                              33            0      0.00%      0.00%
                              34            0      0.00%      0.00%
                              35            0      0.00%      0.00%
                              36            0      0.00%      0.00%
                              37            0      0.00%      0.00%
                              38            0      0.00%      0.00%
                              39            0      0.00%      0.00%
                              40            0      0.00%      0.00%
                              41            0      0.00%      0.00%
                              42            0      0.00%      0.00%
                              43            0      0.00%      0.00%
                              44            0      0.00%      0.00%
                              45            0      0.00%      0.00%
                              46            0      0.00%      0.00%
                              47            0      0.00%      0.00%
                              48            0      0.00%      0.00%
                              49            0      0.00%      0.00%
                              50            0      0.00%      0.00%
                              51            0      0.00%      0.00%
                              52            0      0.00%      0.00%
                              53            0      0.00%      0.00%
                              54            0      0.00%      0.00%
                              55            0      0.00%      0.00%
                              56            0      0.00%      0.00%
                              57            0      0.00%      0.00%
                              58            0      0.00%      0.00%
                              59            0      0.00%      0.00%
                              60            0      0.00%      0.00%
                              61            0      0.00%      0.00%
                              62            0      0.00%      0.00%
                              63            0      0.00%      0.00%
                              64            0      0.00%      0.00%
                              65            0      0.00%      0.00%
                              66            0      0.00%      0.00%
                              67            0      0.00%      0.00%
                              68            0      0.00%      0.00%
                              69            0      0.00%      0.00%
                              70            0      0.00%      0.00%
                              71            0      0.00%      0.00%
                              72            0      0.00%      0.00%
                              73            0      0.00%      0.00%
                              74            0      0.00%      0.00%
                              75            0      0.00%      0.00%
                              76            0      0.00%      0.00%
                              77            0      0.00%      0.00%
                              78            0      0.00%      0.00%
                              79            0      0.00%      0.00%
                              80            0      0.00%      0.00%
                              81            0      0.00%      0.00%
                              82            0      0.00%      0.00%
                              83            0      0.00%      0.00%
                              84            0      0.00%      0.00%
                              85            0      0.00%      0.00%
                              86            0      0.00%      0.00%
                              87            0      0.00%      0.00%
                              88            0      0.00%      0.00%
                              89            0      0.00%      0.00%
                              90            0      0.00%      0.00%
                              91            0      0.00%      0.00%
                              92            0      0.00%      0.00%
                              93            0      0.00%      0.00%
                              94            0      0.00%      0.00%
                              95            0      0.00%      0.00%
                              96            0      0.00%      0.00%
                              97            0      0.00%      0.00%
                              98            0      0.00%      0.00%
                              99            0      0.00%      0.00%
                             100            0      0.00%      0.00%
system.cpu0.WB:pred_error.overflows         790331133                      
system.cpu0.WB:pred_error.max_value        7351812267                      
system.cpu0.WB:pred_error.end_dist

system.cpu0.WB:producers                    534632349                       # num instructions producing a value
system.cpu0.WB:rate                          0.107492                       # insts written-back per cycle
system.cpu0.branch_pred.btb_accuracy         0.999977                       # fraction of BTB targets correct
system.cpu0.branch_pred.btb_correct         244271679                       # num correct BTB predictions
system.cpu0.branch_pred.btb_hit_rate         0.982658                       # BTB hit ratio
system.cpu0.branch_pred.btb_hits            248538576                       # Number of BTB hits
system.cpu0.branch_pred.btb_lookups         252924727                       # Number of BTB lookups
system.cpu0.branch_pred.cond_correct        245793699                       # num correct dir predictions
system.cpu0.branch_pred.cond_predicted      245971323                       # num committed conditional branches
system.cpu0.branch_pred.dir_accuracy         0.999278                       # fraction of predictions correct
system.cpu0.branch_pred.lookup_rate          0.036513                       # Rate of bpred lookups
system.cpu0.branch_pred.lookups             268462413                       # num BP lookups
system.cpu0.branch_pred.ras_accuracy         0.917703                       # fraction of RAS targets correct
system.cpu0.branch_pred.ras_correct            630863                       # num correct RAS predictions
system.cpu0.branch_pred.used_btb            244277226                       # num committed branches using target from BTB
system.cpu0.branch_pred.used_ras               687437                       # num returns predicted using RAS
system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets    13.532042                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs                  9.036035                       # Average number of references to valid blocks.
system.cpu0.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_no_targets             671                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets         9080                       # number of cycles access was blocked
system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu0.dcache.demand_accesses           14742156                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency    66.430840                       # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency    54.688612                       # average overall mshr miss latency
system.cpu0.dcache.demand_hits               11392553                       # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency      222516942                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_rate          0.227213                       # miss rate for demand accesses
system.cpu0.dcache.demand_misses              3349603                       # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits           2262476                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency     59453467                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate     0.073743                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_misses         1087127                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.dcache.overall_accesses          14952210                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_avg_miss_latency    64.644321                       # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency    50.852320                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency   147.117322                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_hits              11423961                       # number of overall hits
system.cpu0.dcache.overall_miss_latency     228081261                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_rate         0.235968                       # miss rate for overall accesses
system.cpu0.dcache.overall_misses             3528249                       # number of overall misses
system.cpu0.dcache.overall_mshr_hits          2263981                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency     64290961                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate     0.084554                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_misses        1264268                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency      2637078                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses        17925                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu0.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu0.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu0.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.dcache.read_accesses              9070093                       # number of read accesses(hits+misses)
system.cpu0.dcache.read_avg_miss_latency    41.041905                       # average read miss latency
system.cpu0.dcache.read_avg_mshr_miss_latency    46.094122                       # average read mshr miss latency
system.cpu0.dcache.read_avg_mshr_uncacheable_latency    92.599831                       # average read mshr uncacheable latency
system.cpu0.dcache.read_hits                  7508233                       # number of read hits
system.cpu0.dcache.read_miss_latency         64101709                       # number of read miss cycles
system.cpu0.dcache.read_miss_rate            0.172199                       # miss rate for read accesses
system.cpu0.dcache.read_misses                1561860                       # number of read misses
system.cpu0.dcache.read_mshr_hits              741597                       # number of read MSHR hits
system.cpu0.dcache.read_mshr_miss_latency     37809303                       # number of read MSHR miss cycles
system.cpu0.dcache.read_mshr_miss_rate       0.090436                       # mshr miss rate for read accesses
system.cpu0.dcache.read_mshr_misses            820263                       # number of read MSHR misses
system.cpu0.dcache.read_mshr_uncacheable         7102                       # number of read MSHR uncacheable
system.cpu0.dcache.read_mshr_uncacheable_latency       657644                       # number of read MSHR uncacheable cycles
system.cpu0.dcache.replacements               1263755                       # number of replacements
system.cpu0.dcache.sampled_refs               1264267                       # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.dcache.swpf_accesses               210054                       # number of swpf accesses(hits+misses)
system.cpu0.dcache.swpf_avg_miss_latency    31.147179                       # average swpf miss latency
system.cpu0.dcache.swpf_avg_mshr_miss_latency    27.308720                       # average swpf mshr miss latency
system.cpu0.dcache.swpf_hits                    31408                       # number of swpf hits
system.cpu0.dcache.swpf_miss_latency          5564319                       # number of swpf miss cycles
system.cpu0.dcache.swpf_miss_rate            0.850477                       # miss rate for swpf accesses
system.cpu0.dcache.swpf_misses                 178646                       # number of swpf misses
system.cpu0.dcache.swpf_mshr_hits                1505                       # number of swpf MSHR hits
system.cpu0.dcache.swpf_mshr_miss_latency      4837494                       # number of swpf MSHR miss cycles
system.cpu0.dcache.swpf_mshr_miss_rate       0.843312                       # mshr miss rate for swpf accesses
system.cpu0.dcache.swpf_mshr_misses            177141                       # number of swpf MSHR misses
system.cpu0.dcache.tagsinuse               511.996104                       # Cycle average of tags in use
system.cpu0.dcache.total_refs                11423961                       # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle                 67361                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.write_accesses             5672063                       # number of write accesses(hits+misses)
system.cpu0.dcache.write_avg_miss_latency    88.611860                       # average write miss latency
system.cpu0.dcache.write_avg_mshr_miss_latency    81.105597                       # average write mshr miss latency
system.cpu0.dcache.write_avg_mshr_uncacheable_latency   182.891435                       # average write mshr uncacheable latency
system.cpu0.dcache.write_hits                 3884320                       # number of write hits
system.cpu0.dcache.write_miss_latency       158415233                       # number of write miss cycles
system.cpu0.dcache.write_miss_rate           0.315184                       # miss rate for write accesses
system.cpu0.dcache.write_misses               1787743                       # number of write misses
system.cpu0.dcache.write_mshr_hits            1520879                       # number of write MSHR hits
system.cpu0.dcache.write_mshr_miss_latency     21644164                       # number of write MSHR miss cycles
system.cpu0.dcache.write_mshr_miss_rate      0.047049                       # mshr miss rate for write accesses
system.cpu0.dcache.write_mshr_misses           266864                       # number of write MSHR misses
system.cpu0.dcache.write_mshr_uncacheable        10823                       # number of write MSHR uncacheable
system.cpu0.dcache.write_mshr_uncacheable_latency      1979434                       # number of write MSHR uncacheable cycles
system.cpu0.dcache.writebacks                  420907                       # number of writebacks
system.cpu0.dtb.accesses                      3835150                       # DTB accesses
system.cpu0.dtb.acv                            194160                       # DTB access violations
system.cpu0.dtb.hits                         25535402                       # DTB hits
system.cpu0.dtb.misses                        1890198                       # DTB misses
system.cpu0.dtb.read_accesses                 2584932                       # DTB read accesses
system.cpu0.dtb.read_acv                        77364                       # DTB read access violations
system.cpu0.dtb.read_hits                    15658215                       # DTB read hits
system.cpu0.dtb.read_misses                   1221890                       # DTB read misses
system.cpu0.dtb.write_accesses                1250218                       # DTB write accesses
system.cpu0.dtb.write_acv                      116796                       # DTB write access violations
system.cpu0.dtb.write_hits                    9877187                       # DTB write hits
system.cpu0.dtb.write_misses                   668308                       # DTB write misses
system.cpu0.floss.fetch_0.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
system.cpu0.floss.fetch_0.end_dist
system.cpu0.floss.icache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu0.floss.icache_0.end_dist
system.cpu0.floss.iq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
system.cpu0.floss.iq_full_0.end_dist
system.cpu0.floss.iq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu0.floss.iq_full_dcache_0.end_dist
system.cpu0.floss.iq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu0.floss.iq_full_deps_0.end_dist
system.cpu0.floss.iq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu0.floss.iq_full_fu_0.end_dist
system.cpu0.floss.lsq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
system.cpu0.floss.lsq_full_0.end_dist
system.cpu0.floss.lsq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu0.floss.lsq_full_dcache_0.end_dist
system.cpu0.floss.lsq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu0.floss.lsq_full_deps_0.end_dist
system.cpu0.floss.lsq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu0.floss.lsq_full_fu_0.end_dist
system.cpu0.floss.qfull_0.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
system.cpu0.floss.qfull_0.end_dist
system.cpu0.floss.rob_full_0.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
system.cpu0.floss.rob_full_0.end_dist
system.cpu0.floss.rob_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu0.floss.rob_full_dcache_0.end_dist
system.cpu0.floss.rob_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu0.floss.rob_full_fu_0.end_dist
system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.icache.avg_refs                744.819139                       # Average number of references to valid blocks.
system.cpu0.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu0.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
system.cpu0.icache.demand_accesses          567349995                       # number of demand (read+write) accesses
system.cpu0.icache.demand_avg_miss_latency    17.251271                       # average overall miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency    21.388094                       # average overall mshr miss latency
system.cpu0.icache.demand_hits              566505713                       # number of demand (read+write) hits
system.cpu0.icache.demand_miss_latency       14564938                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate          0.001488                       # miss rate for demand accesses
system.cpu0.icache.demand_misses               844282                       # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits             28422                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_miss_latency     17449690                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_rate     0.001438                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses          815860                       # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu0.icache.overall_accesses         567349995                       # number of overall (read+write) accesses
system.cpu0.icache.overall_avg_miss_latency    17.251271                       # average overall miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency    21.388094                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_hits             566505713                       # number of overall hits
system.cpu0.icache.overall_miss_latency      14564938                       # number of overall miss cycles
system.cpu0.icache.overall_miss_rate         0.001488                       # miss rate for overall accesses
system.cpu0.icache.overall_misses              844282                       # number of overall misses
system.cpu0.icache.overall_mshr_hits            28422                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_miss_latency     17449690                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_rate     0.001438                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_misses         815860                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu0.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu0.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu0.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu0.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu0.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.icache.read_accesses            567349995                       # number of read accesses(hits+misses)
system.cpu0.icache.read_avg_miss_latency    17.251271                       # average read miss latency
system.cpu0.icache.read_avg_mshr_miss_latency    21.388094                       # average read mshr miss latency
system.cpu0.icache.read_hits                566505713                       # number of read hits
system.cpu0.icache.read_miss_latency         14564938                       # number of read miss cycles
system.cpu0.icache.read_miss_rate            0.001488                       # miss rate for read accesses
system.cpu0.icache.read_misses                 844282                       # number of read misses
system.cpu0.icache.read_mshr_hits               28422                       # number of read MSHR hits
system.cpu0.icache.read_mshr_miss_latency     17449690                       # number of read MSHR miss cycles
system.cpu0.icache.read_mshr_miss_rate       0.001438                       # mshr miss rate for read accesses
system.cpu0.icache.read_mshr_misses            815860                       # number of read MSHR misses
system.cpu0.icache.replacements                760083                       # number of replacements
system.cpu0.icache.sampled_refs                760595                       # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.tagsinuse               511.632017                       # Cycle average of tags in use
system.cpu0.icache.total_refs               566505713                       # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle              26429988                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks                       0                       # number of writebacks
system.cpu0.iq:RQ:rdy_inst                 2893026239                       # Number of ready instructions (cum)
system.cpu0.iq:RQ:rdy_inst_dist_0_mean       0.393477                       # standard deviation of ready rate
system.cpu0.iq:RQ:rdy_inst_dist_0_stdev      2.987863                       # standard deviation of ready rate
**Ignore: system.cpu0.iq:RQ:rdy_inst_dist_0_TOT   7352469842                       # standard deviation of ready rate
system.cpu0.iq:RQ:rdy_rate                   0.393477                       # Number of ready insts per cycle
system.cpu0.iq:RQ:rdy_x_count               778765923                       # number of insts that become ready (cum)
system.cpu0.iq:RQ:rdy_x_max                        35                       # largest number of insts that become ready
system.cpu0.iq:RQ:rdy_x_rate                 0.105919                       # number of insts that become ready per cycle
system.cpu0.iq:avg_residency                12.870231                       # Average IQ residency
system.cpu0.iq:cum_num_insts               9991903800                       # Total occupancy
system.cpu0.iq:current_count                        0                       # Occupancy this cycle
system.cpu0.iq:empty_count                 7178909350                       # Number of empty cycles
system.cpu0.iq:empty_rate                   97.639426                       # Fraction of cycles empty
system.cpu0.iq:full_count                   148698558                       # Number of full cycles
system.cpu0.iq:full_rate                     2.022430                       # Fraction of cycles full
system.cpu0.iq:occ_dist_0.start_dist                           # IQ Occupancy per cycle
system.cpu0.iq:occ_dist_0.samples          7352469842                      
system.cpu0.iq:occ_dist_0.min_value                 0                      
                               0   7181013053              9766.80%
                               2      2568672              9770.30%
                               4      2094590              9773.15%
                               6      1577343              9775.29%
                               8      2226097              9778.32%
                              10      1257722              9780.03%
                              12      1120256              9781.55%
                              14       886303              9782.76%
                              16       741773              9783.77%
                              18       765487              9784.81%
                              20       710297              9785.78%
                              22       688968              9786.71%
                              24       584713              9787.51%
                              26       520624              9788.22%
                              28       549227              9788.96%
                              30       474232              9789.61%
                              32       534205              9790.33%
                              34       452399              9790.95%
                              36       520967              9791.66%
                              38       416777              9792.22%
                              40       425337              9792.80%
                              42       365746              9793.30%
                              44       546191              9794.04%
                              46       331987              9794.50%
                              48       397181              9795.04%
                              50       304105              9795.45%
                              52       281466              9795.83%
                              54       226422              9796.14%
                              56       267567              9796.50%
                              58       214798              9796.80%
                              60       245570              9797.13%
                              62       288619              9797.52%
                              64    148871148             10000.00%
system.cpu0.iq:occ_dist_0.max_value                64                      
system.cpu0.iq:occ_dist_0.end_dist

system.cpu0.iq:occ_rate                      1.358986                       # Average occupancy
system.cpu0.iq:peak_occupancy                      64                       # Peak IQ occupancy
system.cpu0.itb.accesses                      7984508                       # ITB accesses
system.cpu0.itb.acv                             35269                       # ITB acv
system.cpu0.itb.hits                          7888639                       # ITB hits
system.cpu0.itb.misses                          95869                       # ITB misses
system.cpu0.kern.callpal                       172491                       # number of callpals executed
system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu0.kern.callpal_wripir                   577      0.33%      0.34% # number of callpals executed
system.cpu0.kern.callpal_wrmces                     1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal_wrfen                      1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.34% # number of callpals executed
system.cpu0.kern.callpal_swpctx                  3523      2.04%      2.38% # number of callpals executed
system.cpu0.kern.callpal_tbi                       17      0.01%      2.39% # number of callpals executed
system.cpu0.kern.callpal_wrent                      7      0.00%      2.39% # number of callpals executed
system.cpu0.kern.callpal_swpipl                158999     92.18%     94.57% # number of callpals executed
system.cpu0.kern.callpal_rdps                    4048      2.35%     96.92% # number of callpals executed
system.cpu0.kern.callpal_wrkgp                      1      0.00%     96.92% # number of callpals executed
system.cpu0.kern.callpal_wrusp                      4      0.00%     96.92% # number of callpals executed
system.cpu0.kern.callpal_rdusp                      9      0.01%     96.93% # number of callpals executed
system.cpu0.kern.callpal_whami                      1      0.00%     96.93% # number of callpals executed
system.cpu0.kern.callpal_rti                     4698      2.72%     99.65% # number of callpals executed
system.cpu0.kern.callpal_callsys                  413      0.24%     99.89% # number of callpals executed
system.cpu0.kern.callpal_imb                      190      0.11%    100.00% # number of callpals executed
system.cpu0.kern.faults                         16081                       # number of faults
system.cpu0.kern.faults_interrupt                2641     16.42%     16.42% # number of faults
system.cpu0.kern.faults_dtb_miss_single          6889     42.84%     59.26% # number of faults
system.cpu0.kern.faults_dtb_miss_double          2046     12.72%     71.99% # number of faults
system.cpu0.kern.faults_dfault                    117      0.73%     72.71% # number of faults
system.cpu0.kern.faults_dfault                    162      1.01%     73.72% # number of faults
system.cpu0.kern.faults_itbmiss                  4065     25.28%     99.00% # number of faults
system.cpu0.kern.faults_iaccvio                   161      1.00%    100.00% # number of faults
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.hwrei                    188574                       # number of hwrei instructions executed
system.cpu0.kern.inst.ivlb                          0                       # number of ivlb instructions executed
system.cpu0.kern.inst.ivle                          0                       # number of ivle instructions executed
system.cpu0.kern.inst.quiesce                    2361                       # number of quiesce instructions executed
system.cpu0.kern.ipl_count                     166339                       # number of times we switched to this ipl
system.cpu0.kern.ipl_count_0                    69533     41.80%     41.80% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_21                     281      0.17%     41.97% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_22                    5789      3.48%     45.45% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_30                     483      0.29%     45.74% # number of times we switched to this ipl
system.cpu0.kern.ipl_count_31                   90253     54.26%    100.00% # number of times we switched to this ipl
system.cpu0.kern.ipl_good                      147516                       # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_0                     68767     46.62%     46.62% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_21                      281      0.19%     46.81% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_22                     5789      3.92%     50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_30                      483      0.33%     51.06% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good_31                    72196     48.94%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_ticks                 7351812205                       # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_0               7302769490     99.33%     99.33% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_21                  110883      0.00%     99.33% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_22                  926350      0.01%     99.35% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_30                  204113      0.00%     99.35% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks_31                47801369      0.65%    100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used                    0.886840                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_0                  0.988984                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used_31                 0.799929                       # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good_kernel                2062                      
system.cpu0.kern.mode_good_user                  1299                      
system.cpu0.kern.mode_good_idle                   582                      
system.cpu0.kern.mode_good_interrupt              181                      
system.cpu0.kern.mode_switch_kernel              6792                       # number of protection mode switches
system.cpu0.kern.mode_switch_user                1299                       # number of protection mode switches
system.cpu0.kern.mode_switch_idle                7373                       # number of protection mode switches
system.cpu0.kern.mode_switch_interrupt            181                       # number of protection mode switches
system.cpu0.kern.mode_switch_good            0.263599                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_kernel     0.303592                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_idle       0.078937                       # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good_interrupt            1                       # fraction of useful protection mode switches
system.cpu0.kern.mode_ticks_kernel          156057907      2.12%      2.12% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_user              3910809      0.05%      2.18% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_idle           7190983859     97.81%     99.99% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks_interrupt          798028      0.01%    100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context                    3524                       # number of times the context was actually changed
system.cpu0.kern.syscall                          285                       # number of syscalls executed
system.cpu0.kern.syscall_fork                       7      2.46%      2.46% # number of syscalls executed
system.cpu0.kern.syscall_read                      19      6.67%      9.12% # number of syscalls executed
system.cpu0.kern.syscall_write                      4      1.40%     10.53% # number of syscalls executed
system.cpu0.kern.syscall_close                     32     11.23%     21.75% # number of syscalls executed
system.cpu0.kern.syscall_chdir                      1      0.35%     22.11% # number of syscalls executed
system.cpu0.kern.syscall_chmod                      1      0.35%     22.46% # number of syscalls executed
system.cpu0.kern.syscall_obreak                    24      8.42%     30.88% # number of syscalls executed
system.cpu0.kern.syscall_lseek                      9      3.16%     34.04% # number of syscalls executed
system.cpu0.kern.syscall_getpid                     6      2.11%     36.14% # number of syscalls executed
system.cpu0.kern.syscall_setuid                     2      0.70%     36.84% # number of syscalls executed
system.cpu0.kern.syscall_getuid                     4      1.40%     38.25% # number of syscalls executed
system.cpu0.kern.syscall_access                     4      1.40%     39.65% # number of syscalls executed
system.cpu0.kern.syscall_dup                        2      0.70%     40.35% # number of syscalls executed
system.cpu0.kern.syscall_open                      39     13.68%     54.04% # number of syscalls executed
system.cpu0.kern.syscall_getgid                     4      1.40%     55.44% # number of syscalls executed
system.cpu0.kern.syscall_sigprocmask                9      3.16%     58.60% # number of syscalls executed
system.cpu0.kern.syscall_ioctl                     10      3.51%     62.11% # number of syscalls executed
system.cpu0.kern.syscall_readlink                   1      0.35%     62.46% # number of syscalls executed
system.cpu0.kern.syscall_execve                     6      2.11%     64.56% # number of syscalls executed
system.cpu0.kern.syscall_pre_F64_stat              24      8.42%     72.98% # number of syscalls executed
system.cpu0.kern.syscall_pre_F64_lstat              1      0.35%     73.33% # number of syscalls executed
system.cpu0.kern.syscall_mmap                      28      9.82%     83.16% # number of syscalls executed
system.cpu0.kern.syscall_munmap                     3      1.05%     84.21% # number of syscalls executed
system.cpu0.kern.syscall_mprotect                   7      2.46%     86.67% # number of syscalls executed
system.cpu0.kern.syscall_gethostname                1      0.35%     87.02% # number of syscalls executed
system.cpu0.kern.syscall_dup2                       3      1.05%     88.07% # number of syscalls executed
system.cpu0.kern.syscall_pre_F64_fstat             15      5.26%     93.33% # number of syscalls executed
system.cpu0.kern.syscall_fcntl                      9      3.16%     96.49% # number of syscalls executed
system.cpu0.kern.syscall_socket                     2      0.70%     97.19% # number of syscalls executed
system.cpu0.kern.syscall_connect                    2      0.70%     97.89% # number of syscalls executed
system.cpu0.kern.syscall_setgid                     2      0.70%     98.60% # number of syscalls executed
system.cpu0.kern.syscall_getrlimit                  2      0.70%     99.30% # number of syscalls executed
system.cpu0.kern.syscall_setsid                     2      0.70%    100.00% # number of syscalls executed
system.cpu0.l2.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.l2.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.l2.avg_refs                      3.358127                       # Average number of references to valid blocks.
system.cpu0.l2.blocked_no_mshrs                     0                       # number of cycles access was blocked
system.cpu0.l2.blocked_no_targets                   0                       # number of cycles access was blocked
system.cpu0.l2.blocked_cycles_no_mshrs              0                       # number of cycles access was blocked
system.cpu0.l2.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.l2.cache_copies                         0                       # number of cache copies performed
system.cpu0.l2.demand_accesses                2024863                       # number of demand (read+write) accesses
system.cpu0.l2.demand_avg_miss_latency      96.720035                       # average overall miss latency
system.cpu0.l2.demand_avg_mshr_miss_latency    80.362395                       # average overall mshr miss latency
system.cpu0.l2.demand_hits                    1463693                       # number of demand (read+write) hits
system.cpu0.l2.demand_miss_latency           54276382                       # number of demand (read+write) miss cycles
system.cpu0.l2.demand_miss_rate              0.277140                       # miss rate for demand accesses
system.cpu0.l2.demand_misses                   561170                       # number of demand (read+write) misses
system.cpu0.l2.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.cpu0.l2.demand_mshr_miss_latency      45096965                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2.demand_mshr_miss_rate         0.277140                       # mshr miss rate for demand accesses
system.cpu0.l2.demand_mshr_misses              561170                       # number of demand (read+write) MSHR misses
system.cpu0.l2.fast_writes                          0                       # number of fast writes performed
system.cpu0.l2.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.cpu0.l2.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.l2.overall_accesses               2445770                       # number of overall (read+write) accesses
system.cpu0.l2.overall_avg_miss_latency     96.568772                       # average overall miss latency
system.cpu0.l2.overall_avg_mshr_miss_latency    80.362395                       # average overall mshr miss latency
system.cpu0.l2.overall_avg_mshr_uncacheable_latency   128.129986                       # average overall mshr uncacheable latency
system.cpu0.l2.overall_hits                   1883721                       # number of overall hits
system.cpu0.l2.overall_miss_latency          54276382                       # number of overall miss cycles
system.cpu0.l2.overall_miss_rate             0.229805                       # miss rate for overall accesses
system.cpu0.l2.overall_misses                  562049                       # number of overall misses
system.cpu0.l2.overall_mshr_hits                    0                       # number of overall MSHR hits
system.cpu0.l2.overall_mshr_miss_latency     45096965                       # number of overall MSHR miss cycles
system.cpu0.l2.overall_mshr_miss_rate        0.229445                       # mshr miss rate for overall accesses
system.cpu0.l2.overall_mshr_misses             561170                       # number of overall MSHR misses
system.cpu0.l2.overall_mshr_uncacheable_latency      2296730                       # number of overall MSHR uncacheable cycles
system.cpu0.l2.overall_mshr_uncacheable_misses        17925                       # number of overall MSHR uncacheable misses
system.cpu0.l2.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu0.l2.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu0.l2.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu0.l2.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l2.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu0.l2.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.l2.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu0.l2.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu0.l2.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l2.read_accesses                  2024863                       # number of read accesses(hits+misses)
system.cpu0.l2.read_avg_miss_latency        96.720035                       # average read miss latency
system.cpu0.l2.read_avg_mshr_miss_latency    80.362395                       # average read mshr miss latency
system.cpu0.l2.read_avg_mshr_uncacheable_latency    73.606308                       # average read mshr uncacheable latency
system.cpu0.l2.read_hits                      1463693                       # number of read hits
system.cpu0.l2.read_miss_latency             54276382                       # number of read miss cycles
system.cpu0.l2.read_miss_rate                0.277140                       # miss rate for read accesses
system.cpu0.l2.read_misses                     561170                       # number of read misses
system.cpu0.l2.read_mshr_miss_latency        45096965                       # number of read MSHR miss cycles
system.cpu0.l2.read_mshr_miss_rate           0.277140                       # mshr miss rate for read accesses
system.cpu0.l2.read_mshr_misses                561170                       # number of read MSHR misses
system.cpu0.l2.read_mshr_uncacheable             7102                       # number of read MSHR uncacheable
system.cpu0.l2.read_mshr_uncacheable_latency       522752                       # number of read MSHR uncacheable cycles
system.cpu0.l2.replacements                    556848                       # number of replacements
system.cpu0.l2.sampled_refs                    560944                       # Sample count of references to valid blocks.
system.cpu0.l2.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.l2.tagsinuse                  4095.872703                       # Cycle average of tags in use
system.cpu0.l2.total_refs                     1883721                       # Total number of references to valid blocks.
system.cpu0.l2.warmup_cycle                    788915                       # Cycle when the warmup percentage was hit.
system.cpu0.l2.write_avg_mshr_uncacheable_latency   163.908159                       # average write mshr uncacheable latency
system.cpu0.l2.write_mshr_uncacheable           10823                       # number of write MSHR uncacheable
system.cpu0.l2.write_mshr_uncacheable_latency      1773978                       # number of write MSHR uncacheable cycles
system.cpu0.l2.writeback_accesses              420907                       # number of writeback accesses(hits+misses)
system.cpu0.l2.writeback_hits                  420028                       # number of writeback hits
system.cpu0.l2.writeback_miss_rate           0.002088                       # miss rate for writeback accesses
system.cpu0.l2.writeback_misses                   879                       # number of writeback misses
system.cpu0.l2.writeback_mshr_miss_rate      0.002088                       # mshr miss rate for writeback accesses
system.cpu0.l2.writeback_mshr_misses              879                       # number of writeback MSHR misses
system.cpu0.l2.writebacks                      221903                       # number of writebacks
system.cpu0.l3.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.l3.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu0.l3.avg_refs                      1.459374                       # Average number of references to valid blocks.
system.cpu0.l3.blocked_no_mshrs                     0                       # number of cycles access was blocked
system.cpu0.l3.blocked_no_targets                   0                       # number of cycles access was blocked
system.cpu0.l3.blocked_cycles_no_mshrs              0                       # number of cycles access was blocked
system.cpu0.l3.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu0.l3.cache_copies                         0                       # number of cache copies performed
system.cpu0.l3.demand_accesses                 561170                       # number of demand (read+write) accesses
system.cpu0.l3.demand_avg_miss_latency     108.937544                       # average overall miss latency
system.cpu0.l3.demand_avg_mshr_miss_latency    71.225957                       # average overall mshr miss latency
system.cpu0.l3.demand_hits                     242579                       # number of demand (read+write) hits
system.cpu0.l3.demand_miss_latency           34706521                       # number of demand (read+write) miss cycles
system.cpu0.l3.demand_miss_rate              0.567726                       # miss rate for demand accesses
system.cpu0.l3.demand_misses                   318591                       # number of demand (read+write) misses
system.cpu0.l3.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.cpu0.l3.demand_mshr_miss_latency      22691949                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l3.demand_mshr_miss_rate         0.567726                       # mshr miss rate for demand accesses
system.cpu0.l3.demand_mshr_misses              318591                       # number of demand (read+write) MSHR misses
system.cpu0.l3.fast_writes                          0                       # number of fast writes performed
system.cpu0.l3.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.cpu0.l3.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu0.l3.overall_accesses                783952                       # number of overall (read+write) accesses
system.cpu0.l3.overall_avg_miss_latency    108.911221                       # average overall miss latency
system.cpu0.l3.overall_avg_mshr_miss_latency    71.225957                       # average overall mshr miss latency
system.cpu0.l3.overall_avg_mshr_uncacheable_latency    87.227950                       # average overall mshr uncacheable latency
system.cpu0.l3.overall_hits                    465284                       # number of overall hits
system.cpu0.l3.overall_miss_latency          34706521                       # number of overall miss cycles
system.cpu0.l3.overall_miss_rate             0.406489                       # miss rate for overall accesses
system.cpu0.l3.overall_misses                  318668                       # number of overall misses
system.cpu0.l3.overall_mshr_hits                    0                       # number of overall MSHR hits
system.cpu0.l3.overall_mshr_miss_latency     22691949                       # number of overall MSHR miss cycles
system.cpu0.l3.overall_mshr_miss_rate        0.406391                       # mshr miss rate for overall accesses
system.cpu0.l3.overall_mshr_misses             318591                       # number of overall MSHR misses
system.cpu0.l3.overall_mshr_uncacheable_latency      1563561                       # number of overall MSHR uncacheable cycles
system.cpu0.l3.overall_mshr_uncacheable_misses        17925                       # number of overall MSHR uncacheable misses
system.cpu0.l3.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu0.l3.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu0.l3.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu0.l3.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu0.l3.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu0.l3.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.l3.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu0.l3.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu0.l3.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu0.l3.read_accesses                   561170                       # number of read accesses(hits+misses)
system.cpu0.l3.read_avg_miss_latency       108.937544                       # average read miss latency
system.cpu0.l3.read_avg_mshr_miss_latency    71.225957                       # average read mshr miss latency
system.cpu0.l3.read_avg_mshr_uncacheable_latency    32.685018                       # average read mshr uncacheable latency
system.cpu0.l3.read_hits                       242579                       # number of read hits
system.cpu0.l3.read_miss_latency             34706521                       # number of read miss cycles
system.cpu0.l3.read_miss_rate                0.567726                       # miss rate for read accesses
system.cpu0.l3.read_misses                     318591                       # number of read misses
system.cpu0.l3.read_mshr_miss_latency        22691949                       # number of read MSHR miss cycles
system.cpu0.l3.read_mshr_miss_rate           0.567726                       # mshr miss rate for read accesses
system.cpu0.l3.read_mshr_misses                318591                       # number of read MSHR misses
system.cpu0.l3.read_mshr_uncacheable             7102                       # number of read MSHR uncacheable
system.cpu0.l3.read_mshr_uncacheable_latency       232129                       # number of read MSHR uncacheable cycles
system.cpu0.l3.replacements                    285390                       # number of replacements
system.cpu0.l3.sampled_refs                    317293                       # Sample count of references to valid blocks.
system.cpu0.l3.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.cpu0.l3.tagsinuse                 32753.454202                       # Cycle average of tags in use
system.cpu0.l3.total_refs                      463049                       # Total number of references to valid blocks.
system.cpu0.l3.warmup_cycle                   5920087                       # Cycle when the warmup percentage was hit.
system.cpu0.l3.write_avg_mshr_uncacheable_latency   123.018756                       # average write mshr uncacheable latency
system.cpu0.l3.write_mshr_uncacheable           10823                       # number of write MSHR uncacheable
system.cpu0.l3.write_mshr_uncacheable_latency      1331432                       # number of write MSHR uncacheable cycles
system.cpu0.l3.writeback_accesses              222782                       # number of writeback accesses(hits+misses)
system.cpu0.l3.writeback_hits                  222705                       # number of writeback hits
system.cpu0.l3.writeback_miss_rate           0.000346                       # miss rate for writeback accesses
system.cpu0.l3.writeback_misses                    77                       # number of writeback misses
system.cpu0.l3.writeback_mshr_miss_rate      0.000346                       # mshr miss rate for writeback accesses
system.cpu0.l3.writeback_mshr_misses               77                       # number of writeback MSHR misses
system.cpu0.l3.writebacks                      139062                       # number of writebacks
system.cpu0.numCycles                      7352469842                       # number of cpu cycles simulated
system.cpu0.toL2Bus.addr_idle_cycles       7349290232                       # number of cycles bus was idle
system.cpu0.toL2Bus.addr_idle_fraction       0.999568                       # fraction of time addr bus was idle
system.cpu0.toL2Bus.addr_queued              3.780156                       # average queueing delay seen by bus request
system.cpu0.toL2Bus.addr_queued_cycles        9502972                       # total number of queued cycles for all requests
system.cpu0.toL2Bus.addr_requests             2513910                       # number of transmissions on bus
system.cpu0.toL2Bus.bus_blocked                   334                       # number of times bus was blocked
system.cpu0.toL2Bus.bus_blocked_cycles          90700                       # number of cycles bus was blocked
system.cpu0.toL2Bus.bus_blocked_fraction     0.000012                       # fraction of time bus was blocked
system.cpu0.toL2Bus.data_idle_cycles       7349348603                       # number of cycles bus was idle
system.cpu0.toL2Bus.data_idle_fraction       0.999575                       # fraction of time data bus was idle
system.cpu0.toL2Bus.data_queued              1.023644                       # average queueing delay seen by bus request
system.cpu0.toL2Bus.data_queued_cycles        2080009                       # total number of queued cycles for all requests
system.cpu0.toL2Bus.data_requests             2031965                       # number of transmissions on bus
system.cpu0.toL2Bus.null_grants                 45597                       # number of null grants (wasted cycles)
system.cpu0.toL3Bus.addr_idle_cycles       7350959072                       # number of cycles bus was idle
system.cpu0.toL3Bus.addr_idle_fraction       0.999795                       # fraction of time addr bus was idle
system.cpu0.toL3Bus.addr_queued              9.665259                       # average queueing delay seen by bus request
system.cpu0.toL3Bus.addr_queued_cycles        8235690                       # total number of queued cycles for all requests
system.cpu0.toL3Bus.addr_requests              852092                       # number of transmissions on bus
system.cpu0.toL3Bus.bus_blocked                   372                       # number of times bus was blocked
system.cpu0.toL3Bus.bus_blocked_cycles          80264                       # number of cycles bus was blocked
system.cpu0.toL3Bus.bus_blocked_fraction     0.000011                       # fraction of time bus was blocked
system.cpu0.toL3Bus.data_idle_cycles       7351010407                       # number of cycles bus was idle
system.cpu0.toL3Bus.data_idle_fraction       0.999802                       # fraction of time data bus was idle
system.cpu0.toL3Bus.data_queued              1.064726                       # average queueing delay seen by bus request
system.cpu0.toL3Bus.data_queued_cycles         605054                       # total number of queued cycles for all requests
system.cpu0.toL3Bus.data_requests              568272                       # number of transmissions on bus
system.cpu0.toL3Bus.null_grants                     0                       # number of null grants (wasted cycles)
system.cpu0inst_class_dist.start_dist
                   All ops ready            0      0.00%            # Operand status at dispatch
                One op not ready            0      0.00%            # Operand status at dispatch
           None rdy, mult chains            0      0.00%            # Operand status at dispatch
           None rdy, one chained            0      0.00%            # Operand status at dispatch
        None rdy, all self-timed            0      0.00%            # Operand status at dispatch
system.cpu0inst_class_dist.end_dist
system.cpu1.COM:IPB                          2.167640                       # Committed instructions per branch
system.cpu1.COM:IPC                          0.020961                       # Committed instructions per cycle
system.cpu1.COM:branches                     71096147                       # Number of branches committed
system.cpu1.COM:bw_lim_avg               <err: div-0>                       # Avg number not committed in cycles BW limited
system.cpu1.COM:bw_lim_events                       0                       # number cycles where commit BW limit reached
system.cpu1.COM:bw_lim_rate                    0.0000                       # Average number not committed due to BW (over all cycles)
system.cpu1.COM:bw_lim_stdev_0_mean      <err: div-0>                       # standard deviation of bw_lim_avg value
system.cpu1.COM:bw_lim_stdev_0_stdev     <err: div-0>                       # standard deviation of bw_lim_avg value
**Ignore: system.cpu1.COM:bw_lim_stdev_0_TOT       0.0000                       # standard deviation of bw_lim_avg value
system.cpu1.COM:bw_limited                          0                       # number of insts not committed due to BW limits
system.cpu1.COM:committed_per_cycle.start_dist                     # Number of insts commited each cycle
system.cpu1.COM:committed_per_cycle.samples     32225781                      
system.cpu1.COM:committed_per_cycle.min_value            0                      
                               0       115001     35.69%           
                               1      5719402   1774.79%           
                               2      4586720   1423.31%           
                               3       597125    185.29%           
                               4      4204789   1304.79%           
                               5       217458     67.48%           
                               6      5367244   1665.51%           
                               7      4022823   1248.32%           
                               8      7395219   2294.81%           
system.cpu1.COM:committed_per_cycle.max_value            8                      
system.cpu1.COM:committed_per_cycle.end_dist

system.cpu1.COM:count                       154110851                       # Number of instructions committed
system.cpu1.COM:loads                        71322022                       # Number of loads committed
system.cpu1.COM:membars                         84487                       # Number of memory barriers committed
system.cpu1.COM:refs                         73524494                       # Number of memory references committed
system.cpu1.COM:stores                        2202472                       # Number of stores committed
system.cpu1.COM:swp_count                        4789                       # Number of s/w prefetches committed
system.cpu1.DDQ:count                      4380897235                       # cum count of instructions
system.cpu1.DDQ:rate                                1                       # average number of instructions
system.cpu1.DIS:chain_creation.start_dist
     Inst has no outstanding IDEPS            0      0.00%            # Reason that chain head was created
      IDEP chain reached max depth            0      0.00%            # Reason that chain head was created
                    Inst is a load            0      0.00%            # Reason that chain head was created
  Chain has multiple chained IDEPS            0      0.00%            # Reason that chain head was created
system.cpu1.DIS:chain_creation.end_dist
system.cpu1.DIS:chain_head_frac                     0                       # fraction of insts that are chain heads
system.cpu1.DIS:chain_heads                         0                       # number insts that are chain heads
system.cpu1.DIS:chains_insuf                        0                       # number of times thread had insuf chains
system.cpu1.DIS:chains_insuf_rate                   0                       # rate that thread had insuf chains
system.cpu1.DIS:count                       161770372                       # cumulative count of dispatched insts
system.cpu1.DIS:insufficient_chains                 0                       # Number of instances where dispatch stopped
system.cpu1.DIS:mod_n_stall_avg_free         no value                       # avg free slots per cycle
system.cpu1.DIS:mod_n_stall_frac                    0                       # avg stalls per cycle
system.cpu1.DIS:mod_n_stall_free                    0                       # free slots when dispatch stalled due to mod-n
system.cpu1.DIS:mod_n_stalls                        0                       # cycles where dispatch stalled due to mod-n
system.cpu1.DIS:one_rdy_insts                       0                       # number of 2-op insts w/ one rdy op
system.cpu1.DIS:one_rdy_ratio                no value                       # fraction of 2-op insts w/ one ready op
system.cpu1.DIS:op_count                    237376591                       # number of operations dispatched
system.cpu1.DIS:op_rate                      0.032287                       # dispatched operations per cycle
system.cpu1.DIS:rate                         0.022003                       # dispatched_insts per cycle
system.cpu1.DIS:second_choice_clust                 0                       # Number of instructions dispatched to second-choice cluster
system.cpu1.DIS:second_choice_stall                 0                       # Number of instructions stalled when first choice not available
system.cpu1.DIS:serialize_stall_cycles        2225441                       # count of cycles dispatch stalled for serializing inst
system.cpu1.DIS:serializing_insts              164952                       # count of serializing insts dispatched
system.cpu1.DIS:two_input_insts                     0                       # Number of two input instructions queued
system.cpu1.DIS:two_input_ratio                     0                       # fraction of all insts having 2 inputs
system.cpu1.FETCH:branch_count               68243561                       # Number of branches fetched
system.cpu1.FETCH:branch_rate                0.009282                       # Number of branch fetches per cycle
system.cpu1.FETCH:chance_pct                        1                       # Percentage of all fetch chances
system.cpu1.FETCH:chances                    34877232                       # Number of fetch opportunities
system.cpu1.FETCH:choice                     34877232                       # Number of times we fetched from our first choice
system.cpu1.FETCH:count                     188205211                       # Number of instructions fetched
system.cpu1.FETCH:decisions                  34877232                       # number of times the fetch stage chose between threads
system.cpu1.FETCH:idle_cycles              7317310708                       # number of cycles where fetch stage was idle
system.cpu1.FETCH:idle_icache_blocked_cycles            0                       # number of cycles where fetch was idle due to icache blocked
system.cpu1.FETCH:idle_rate                     99.53                       # percent of cycles fetch stage was idle
system.cpu1.FETCH:prio_changes                      0                       # Number of times priorities were changed
system.cpu1.FETCH:rate                       0.025599                       # Number of inst fetches per cycle
system.cpu1.FETCH:rate_dist.start_dist                         # Number of instructions fetched each cycle (Total)
system.cpu1.FETCH:rate_dist.samples          34877232                      
system.cpu1.FETCH:rate_dist.min_value               0                      
                               0        85484     24.51%           
                               1       151256     43.37%           
                               2       180247     51.68%           
                               3       965878    276.94%           
                               4      5447969   1562.04%           
                               5     15643217   4485.22%           
                               6      7091917   2033.39%           
                               7       253748     72.75%           
                               8      5057516   1450.09%           
system.cpu1.FETCH:rate_dist.max_value               8                      
system.cpu1.FETCH:rate_dist.end_dist

system.cpu1.FETCH:rate_dist_0.start_dist                       # Number of instructions fetched each cycle (Thread 0)
system.cpu1.FETCH:rate_dist_0.samples        34877232                      
system.cpu1.FETCH:rate_dist_0.min_value             0                      
                               0        85484     24.51%           
                               1       151256     43.37%           
                               2       180247     51.68%           
                               3       965878    276.94%           
                               4      5447969   1562.04%           
                               5     15643217   4485.22%           
                               6      7091917   2033.39%           
                               7       253748     72.75%           
                               8      5057516   1450.09%           
system.cpu1.FETCH:rate_dist_0.max_value             8                      
system.cpu1.FETCH:rate_dist_0.end_dist

system.cpu1.IFQ:count                      1062896435                       # cumulative IFQ occupancy
system.cpu1.IFQ:full_count                   24370316                       # cumulative IFQ full count
system.cpu1.IFQ:full_rate                    0.331470                       # fraction of time (cycle's) IFQ was full
system.cpu1.IFQ:latency                      6.570402                       # avg IFQ occupant latency (cycle's)
system.cpu1.IFQ:occupancy                    0.144569                       # avg IFQ occupancy (inst's)
system.cpu1.IFQ:qfull_iq_occ                 61885319                       # Number of insts in IQ when fetch-queue full
system.cpu1.IFQ:qfull_iq_occ_dist_0.start_dist                     # Number of insts in IQ when fetch-queue full
system.cpu1.IFQ:qfull_iq_occ_dist_0.samples      2401591                      
system.cpu1.IFQ:qfull_iq_occ_dist_0.min_value            0                      
                               0      1132545   4715.81%           
                              10       250325   1042.33%           
                              20        91621    381.50%           
                              30       112154    467.00%           
                              40        67767    282.18%           
                              50        88171    367.14%           
                              60       659008   2744.05%           
system.cpu1.IFQ:qfull_iq_occ_dist_0.max_value           64                      
system.cpu1.IFQ:qfull_iq_occ_dist_0.end_dist

system.cpu1.IFQ:qfull_rob_occ               192351258                       # Number of insts in ROB when fetch-queue full
system.cpu1.IFQ:qfull_rob_occ_dist_0.start_dist                     # Number of insts in ROB when fetch-queue full
system.cpu1.IFQ:qfull_rob_occ_dist_0.samples      2401591                      
system.cpu1.IFQ:qfull_rob_occ_dist_0.min_value            1                      
                               0       247397   1030.14%           
                              10       188773    786.03%           
                              20        94103    391.84%           
                              30        78729    327.82%           
                              40        50601    210.70%           
                              50        27737    115.49%           
                              60        45149    188.00%           
                              70       500065   2082.22%           
                              80        95411    397.28%           
                              90        95483    397.58%           
                             100        97863    407.49%           
                             110        94976    395.47%           
                             120       785304   3269.93%           
                             130            0      0.00%           
system.cpu1.IFQ:qfull_rob_occ_dist_0.max_value          128                      
system.cpu1.IFQ:qfull_rob_occ_dist_0.end_dist

system.cpu1.IQ:cap_events                           0                       # number of cycles where IQ cap was active
system.cpu1.IQ:cap_inst                             0                       # number of instructions held up by IQ cap
system.cpu1.IQ:residence:(null).start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:(null).samples          2790                      
system.cpu1.IQ:residence:(null).min_value            1                      
                               0         2697   9666.67%   9666.67%
                               2           88    315.41%   9982.08%
                               4            2      7.17%   9989.25%
                               6            1      3.58%   9992.83%
                               8            2      7.17%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu1.IQ:residence:(null).max_value            9                      
system.cpu1.IQ:residence:(null).end_dist

system.cpu1.IQ:residence:IntAlu.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:IntAlu.samples      82237075                      
system.cpu1.IQ:residence:IntAlu.min_value            1                      
                               0      3463155    421.12%    421.12%
                               2      2330087    283.34%    704.46%
                               4      1580610    192.20%    896.66%
                               6      1026194    124.78%   1021.44%
                               8       779398     94.77%   1116.22%
                              10      1481227    180.12%   1296.33%
                              12       694247     84.42%   1380.75%
                              14     68579660   8339.26%   9720.02%
                              16       325103     39.53%   9759.55%
                              18       155170     18.87%   9778.42%
                              20       141266     17.18%   9795.60%
                              22       127065     15.45%   9811.05%
                              24       147339     17.92%   9828.96%
                              26       126199     15.35%   9844.31%
                              28       104655     12.73%   9857.04%
                              30        86754     10.55%   9867.58%
                              32       131873     16.04%   9883.62%
                              34       105251     12.80%   9896.42%
                              36        39986      4.86%   9901.28%
                              38        67229      8.18%   9909.46%
                              40        36139      4.39%   9913.85%
                              42        35598      4.33%   9918.18%
                              44        29537      3.59%   9921.77%
                              46        27260      3.31%   9925.09%
                              48        23698      2.88%   9927.97%
                              50        26466      3.22%   9931.19%
                              52        31633      3.85%   9935.03%
                              54        34933      4.25%   9939.28%
                              56        16140      1.96%   9941.24%
                              58        11248      1.37%   9942.61%
                              60        12081      1.47%   9944.08%
                              62        12342      1.50%   9945.58%
                              64        15621      1.90%   9947.48%
                              66        15668      1.91%   9949.38%
                              68        13557      1.65%   9951.03%
                              70         8953      1.09%   9952.12%
                              72        11754      1.43%   9953.55%
                              74        16619      2.02%   9955.57%
                              76        10949      1.33%   9956.90%
                              78        14107      1.72%   9958.62%
                              80        13657      1.66%   9960.28%
                              82        18375      2.23%   9962.51%
                              84        18846      2.29%   9964.81%
                              86         9072      1.10%   9965.91%
                              88         8129      0.99%   9966.90%
                              90         8318      1.01%   9967.91%
                              92         5664      0.69%   9968.60%
                              94         5466      0.66%   9969.26%
                              96         7336      0.89%   9970.15%
                              98         2912      0.35%   9970.51%
system.cpu1.IQ:residence:IntAlu.overflows       242529                      
system.cpu1.IQ:residence:IntAlu.max_value         1004                      
system.cpu1.IQ:residence:IntAlu.end_dist

system.cpu1.IQ:residence:IntMult.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:IntMult.samples        15978                      
system.cpu1.IQ:residence:IntMult.min_value            1                      
                               0          567    354.86%    354.86%
                               2          205    128.30%    483.16%
                               4         2632   1647.26%   2130.43%
                               6         1397    874.33%   3004.76%
                               8         1141    714.11%   3718.86%
                              10         2662   1666.04%   5384.90%
                              12         1585    991.99%   6376.89%
                              14         1260    788.58%   7165.48%
                              16          490    306.67%   7472.15%
                              18         1005    628.99%   8101.14%
                              20           45     28.16%   8129.30%
                              22           39     24.41%   8153.71%
                              24           40     25.03%   8178.75%
                              26           81     50.69%   8229.44%
                              28           34     21.28%   8250.72%
                              30          458    286.64%   8537.36%
                              32           15      9.39%   8546.75%
                              34           40     25.03%   8571.79%
                              36          449    281.01%   8852.80%
                              38            6      3.76%   8856.55%
                              40         1179    737.89%   9594.44%
                              42            9      5.63%   9600.08%
                              44          451    282.26%   9882.34%
                              46            5      3.13%   9885.47%
                              48            9      5.63%   9891.10%
                              50            0      0.00%   9891.10%
                              52            2      1.25%   9892.35%
                              54            1      0.63%   9892.98%
                              56            0      0.00%   9892.98%
                              58            1      0.63%   9893.60%
                              60            1      0.63%   9894.23%
                              62            1      0.63%   9894.86%
                              64           17     10.64%   9905.50%
                              66            1      0.63%   9906.12%
                              68            1      0.63%   9906.75%
                              70           12      7.51%   9914.26%
                              72            2      1.25%   9915.51%
                              74            6      3.76%   9919.26%
                              76            0      0.00%   9919.26%
                              78            2      1.25%   9920.52%
                              80            2      1.25%   9921.77%
                              82            1      0.63%   9922.39%
                              84            1      0.63%   9923.02%
                              86            4      2.50%   9925.52%
                              88            1      0.63%   9926.15%
                              90            2      1.25%   9927.40%
                              92            5      3.13%   9930.53%
                              94            0      0.00%   9930.53%
                              96            2      1.25%   9931.78%
                              98            3      1.88%   9933.66%
system.cpu1.IQ:residence:IntMult.overflows          106                      
system.cpu1.IQ:residence:IntMult.max_value          368                      
system.cpu1.IQ:residence:IntMult.end_dist

system.cpu1.IQ:residence:IntDiv.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:IntDiv.samples             0                      
system.cpu1.IQ:residence:IntDiv.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.IQ:residence:IntDiv.max_value            0                      
system.cpu1.IQ:residence:IntDiv.end_dist

system.cpu1.IQ:residence:FloatAdd.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:FloatAdd.samples         4957                      
system.cpu1.IQ:residence:FloatAdd.min_value            1                      
                               0          918   1851.93%   1851.93%
                               2           23     46.40%   1898.33%
                               4          959   1934.64%   3832.96%
                               6         2015   4064.96%   7897.92%
                               8            6     12.10%   7910.03%
                              10            2      4.03%   7914.06%
                              12            1      2.02%   7916.08%
                              14            2      4.03%   7920.11%
                              16            1      2.02%   7922.13%
                              18            1      2.02%   7924.15%
                              20            0      0.00%   7924.15%
                              22            1      2.02%   7926.17%
                              24         1000   2017.35%   9943.51%
                              26            3      6.05%   9949.57%
                              28            0      0.00%   9949.57%
                              30            0      0.00%   9949.57%
                              32            0      0.00%   9949.57%
                              34            0      0.00%   9949.57%
                              36            0      0.00%   9949.57%
                              38            0      0.00%   9949.57%
                              40            0      0.00%   9949.57%
                              42            0      0.00%   9949.57%
                              44            0      0.00%   9949.57%
                              46            0      0.00%   9949.57%
                              48            0      0.00%   9949.57%
                              50            0      0.00%   9949.57%
                              52            0      0.00%   9949.57%
                              54            0      0.00%   9949.57%
                              56            0      0.00%   9949.57%
                              58            0      0.00%   9949.57%
                              60            0      0.00%   9949.57%
                              62            0      0.00%   9949.57%
                              64            3      6.05%   9955.62%
                              66           10     20.17%   9975.79%
                              68            0      0.00%   9975.79%
                              70            0      0.00%   9975.79%
                              72            0      0.00%   9975.79%
                              74            0      0.00%   9975.79%
                              76            0      0.00%   9975.79%
                              78            0      0.00%   9975.79%
                              80            0      0.00%   9975.79%
                              82            0      0.00%   9975.79%
                              84            0      0.00%   9975.79%
                              86            0      0.00%   9975.79%
                              88            0      0.00%   9975.79%
                              90            0      0.00%   9975.79%
                              92            0      0.00%   9975.79%
                              94            0      0.00%   9975.79%
                              96            0      0.00%   9975.79%
                              98            0      0.00%   9975.79%
system.cpu1.IQ:residence:FloatAdd.overflows           12                      
system.cpu1.IQ:residence:FloatAdd.max_value          145                      
system.cpu1.IQ:residence:FloatAdd.end_dist

system.cpu1.IQ:residence:FloatCmp.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:FloatCmp.samples            0                      
system.cpu1.IQ:residence:FloatCmp.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.IQ:residence:FloatCmp.max_value            0                      
system.cpu1.IQ:residence:FloatCmp.end_dist

system.cpu1.IQ:residence:FloatCvt.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:FloatCvt.samples            0                      
system.cpu1.IQ:residence:FloatCvt.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.IQ:residence:FloatCvt.max_value            0                      
system.cpu1.IQ:residence:FloatCvt.end_dist

system.cpu1.IQ:residence:FloatMult.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:FloatMult.samples            0                      
system.cpu1.IQ:residence:FloatMult.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.IQ:residence:FloatMult.max_value            0                      
system.cpu1.IQ:residence:FloatMult.end_dist

system.cpu1.IQ:residence:FloatDiv.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:FloatDiv.samples            4                      
system.cpu1.IQ:residence:FloatDiv.min_value            1                      
                               0            1   2500.00%   2500.00%
                               2            1   2500.00%   5000.00%
                               4            0      0.00%   5000.00%
                               6            2   5000.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu1.IQ:residence:FloatDiv.max_value            7                      
system.cpu1.IQ:residence:FloatDiv.end_dist

system.cpu1.IQ:residence:FloatSqrt.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:FloatSqrt.samples            0                      
system.cpu1.IQ:residence:FloatSqrt.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.IQ:residence:FloatSqrt.max_value            0                      
system.cpu1.IQ:residence:FloatSqrt.end_dist

system.cpu1.IQ:residence:MemRead.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:MemRead.samples    144042411                      
system.cpu1.IQ:residence:MemRead.min_value            1                      
                               0      1571368    109.09%    109.09%
                               2      2336575    162.21%    271.31%
                               4       884889     61.43%    332.74%
                               6       588126     40.83%    373.57%
                               8       340394     23.63%    397.20%
                              10     77582989   5386.12%   5783.32%
                              12     59475352   4129.02%   9912.34%
                              14       162815     11.30%   9923.64%
                              16        99218      6.89%   9930.53%
                              18        70580      4.90%   9935.43%
                              20        54765      3.80%   9939.23%
                              22        46034      3.20%   9942.43%
                              24        65027      4.51%   9946.94%
                              26        50457      3.50%   9950.44%
                              28        60746      4.22%   9954.66%
                              30        65686      4.56%   9959.22%
                              32        51278      3.56%   9962.78%
                              34        56291      3.91%   9966.69%
                              36        48699      3.38%   9970.07%
                              38        27529      1.91%   9971.98%
                              40        39805      2.76%   9974.74%
                              42        21597      1.50%   9976.24%
                              44        21542      1.50%   9977.74%
                              46        16877      1.17%   9978.91%
                              48        17536      1.22%   9980.13%
                              50        20670      1.43%   9981.56%
                              52        17018      1.18%   9982.74%
                              54        10395      0.72%   9983.47%
                              56         8104      0.56%   9984.03%
                              58         7759      0.54%   9984.57%
                              60         4296      0.30%   9984.87%
                              62         5047      0.35%   9985.22%
                              64         4920      0.34%   9985.56%
                              66         8123      0.56%   9986.12%
                              68         8711      0.60%   9986.73%
                              70         7678      0.53%   9987.26%
                              72         7475      0.52%   9987.78%
                              74         6189      0.43%   9988.21%
                              76         7791      0.54%   9988.75%
                              78        15478      1.07%   9989.82%
                              80         5378      0.37%   9990.20%
                              82         8267      0.57%   9990.77%
                              84         3673      0.25%   9991.03%
                              86         7301      0.51%   9991.53%
                              88         5653      0.39%   9991.93%
                              90         3060      0.21%   9992.14%
                              92         5605      0.39%   9992.53%
                              94         4822      0.33%   9992.86%
                              96         1423      0.10%   9992.96%
                              98         1582      0.11%   9993.07%
system.cpu1.IQ:residence:MemRead.overflows        99818                      
system.cpu1.IQ:residence:MemRead.max_value         1001                      
system.cpu1.IQ:residence:MemRead.end_dist

system.cpu1.IQ:residence:MemWrite.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:MemWrite.samples      4858703                      
system.cpu1.IQ:residence:MemWrite.min_value            1                      
                               0       826537   1701.15%   1701.15%
                               2      1592694   3278.02%   4979.17%
                               4       558174   1148.81%   6127.98%
                               6       322842    664.46%   6792.44%
                               8       219013    450.76%   7243.21%
                              10       195895    403.18%   7646.39%
                              12       214338    441.14%   8087.53%
                              14       155859    320.78%   8408.32%
                              16       121112    249.27%   8657.59%
                              18        59774    123.02%   8780.61%
                              20        54989    113.18%   8893.79%
                              22        49903    102.71%   8996.50%
                              24        56797    116.90%   9113.39%
                              26        33239     68.41%   9181.80%
                              28        42293     87.05%   9268.85%
                              30        37010     76.17%   9345.02%
                              32        22383     46.07%   9391.09%
                              34        28084     57.80%   9448.89%
                              36        22938     47.21%   9496.10%
                              38        23236     47.82%   9543.93%
                              40         9484     19.52%   9563.45%
                              42        17847     36.73%   9600.18%
                              44         8333     17.15%   9617.33%
                              46         6322     13.01%   9630.34%
                              48         7421     15.27%   9645.61%
                              50         6768     13.93%   9659.54%
                              52        11109     22.86%   9682.41%
                              54         9356     19.26%   9701.66%
                              56         6125     12.61%   9714.27%
                              58         7777     16.01%   9730.28%
                              60         7593     15.63%   9745.90%
                              62         7286     15.00%   9760.90%
                              64         4401      9.06%   9769.96%
                              66         3457      7.12%   9777.07%
                              68         2208      4.54%   9781.62%
                              70         2145      4.41%   9786.03%
                              72         2672      5.50%   9791.53%
                              74         8556     17.61%   9809.14%
                              76         4761      9.80%   9818.94%
                              78         1194      2.46%   9821.40%
                              80          877      1.81%   9823.20%
                              82         1561      3.21%   9826.41%
                              84         7117     14.65%   9841.06%
                              86         4314      8.88%   9849.94%
                              88          993      2.04%   9851.99%
                              90          914      1.88%   9853.87%
                              92         1076      2.21%   9856.08%
                              94          600      1.23%   9857.32%
                              96          448      0.92%   9858.24%
                              98          905      1.86%   9860.10%
system.cpu1.IQ:residence:MemWrite.overflows        67973                      
system.cpu1.IQ:residence:MemWrite.max_value         1001                      
system.cpu1.IQ:residence:MemWrite.end_dist

system.cpu1.IQ:residence:IprAccess.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:IprAccess.samples       481562                      
system.cpu1.IQ:residence:IprAccess.min_value            1                      
                               0       115041   2388.91%   2388.91%
                               2        24664    512.17%   2901.08%
                               4        86152   1789.01%   4690.09%
                               6        93411   1939.75%   6629.84%
                               8        20847    432.90%   7062.75%
                              10        72718   1510.04%   8572.79%
                              12        14736    306.00%   8878.79%
                              14        11065    229.77%   9108.57%
                              16         4021     83.50%   9192.07%
                              18         6669    138.49%   9330.55%
                              20         5344    110.97%   9441.53%
                              22         2804     58.23%   9499.75%
                              24         5595    116.18%   9615.94%
                              26         4791     99.49%   9715.43%
                              28         1666     34.60%   9750.02%
                              30          731     15.18%   9765.20%
                              32          923     19.17%   9784.37%
                              34         1423     29.55%   9813.92%
                              36          936     19.44%   9833.35%
                              38          164      3.41%   9836.76%
                              40         1183     24.57%   9861.33%
                              42          154      3.20%   9864.52%
                              44          521     10.82%   9875.34%
                              46          646     13.41%   9888.76%
                              48         1042     21.64%   9910.40%
                              50          341      7.08%   9917.48%
                              52          281      5.84%   9923.31%
                              54          488     10.13%   9933.45%
                              56          338      7.02%   9940.46%
                              58          319      6.62%   9947.09%
                              60          209      4.34%   9951.43%
                              62          178      3.70%   9955.13%
                              64          320      6.65%   9961.77%
                              66          266      5.52%   9967.29%
                              68          154      3.20%   9970.49%
                              70          159      3.30%   9973.79%
                              72           31      0.64%   9974.44%
                              74          116      2.41%   9976.85%
                              76           26      0.54%   9977.39%
                              78           50      1.04%   9978.42%
                              80           59      1.23%   9979.65%
                              82           60      1.25%   9980.90%
                              84           34      0.71%   9981.60%
                              86           35      0.73%   9982.33%
                              88           44      0.91%   9983.24%
                              90           41      0.85%   9984.09%
                              92           19      0.39%   9984.49%
                              94           23      0.48%   9984.97%
                              96           30      0.62%   9985.59%
                              98           32      0.66%   9986.25%
system.cpu1.IQ:residence:IprAccess.overflows          662                      
system.cpu1.IQ:residence:IprAccess.max_value          516                      
system.cpu1.IQ:residence:IprAccess.end_dist

system.cpu1.IQ:residence:InstPrefetch.start_dist                     # cycles from dispatch to issue
system.cpu1.IQ:residence:InstPrefetch.samples            0                      
system.cpu1.IQ:residence:InstPrefetch.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.IQ:residence:InstPrefetch.max_value            0                      
system.cpu1.IQ:residence:InstPrefetch.end_dist

system.cpu1.ISSUE:(null)_delay.start_dist                      # cycles from operands ready to issue
system.cpu1.ISSUE:(null)_delay.samples           2790                      
system.cpu1.ISSUE:(null)_delay.min_value            1                      
                               0         2697   9666.67%   9666.67%
                               2           88    315.41%   9982.08%
                               4            2      7.17%   9989.25%
                               6            1      3.58%   9992.83%
                               8            2      7.17%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu1.ISSUE:(null)_delay.max_value            9                      
system.cpu1.ISSUE:(null)_delay.end_dist

system.cpu1.ISSUE:IntAlu_delay.start_dist                      # cycles from operands ready to issue
system.cpu1.ISSUE:IntAlu_delay.samples       82237075                      
system.cpu1.ISSUE:IntAlu_delay.min_value            0                      
                               0     81052260   9855.93%   9855.93%
                               2       657907     80.00%   9935.93%
                               4       111499     13.56%   9949.49%
                               6        45009      5.47%   9954.96%
                               8       123370     15.00%   9969.96%
                              10       233267     28.37%   9998.33%
                              12        13763      1.67%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu1.ISSUE:IntAlu_delay.max_value           12                      
system.cpu1.ISSUE:IntAlu_delay.end_dist

system.cpu1.ISSUE:IntMult_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:IntMult_delay.samples         15978                      
system.cpu1.ISSUE:IntMult_delay.min_value            0                      
                               0        15965   9991.86%   9991.86%
                               2            8      5.01%   9996.87%
                               4            5      3.13%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu1.ISSUE:IntMult_delay.max_value            4                      
system.cpu1.ISSUE:IntMult_delay.end_dist

system.cpu1.ISSUE:IntDiv_delay.start_dist                      # cycles from operands ready to issue
system.cpu1.ISSUE:IntDiv_delay.samples              0                      
system.cpu1.ISSUE:IntDiv_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.ISSUE:IntDiv_delay.max_value            0                      
system.cpu1.ISSUE:IntDiv_delay.end_dist

system.cpu1.ISSUE:FloatAdd_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:FloatAdd_delay.samples         4957                      
system.cpu1.ISSUE:FloatAdd_delay.min_value            0                      
                               0         3389   6836.80%   6836.80%
                               2           23     46.40%   6883.20%
                               4          947   1910.43%   8793.63%
                               6          593   1196.29%   9989.91%
                               8            5     10.09%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu1.ISSUE:FloatAdd_delay.max_value            8                      
system.cpu1.ISSUE:FloatAdd_delay.end_dist

system.cpu1.ISSUE:FloatCmp_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:FloatCmp_delay.samples            0                      
system.cpu1.ISSUE:FloatCmp_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.ISSUE:FloatCmp_delay.max_value            0                      
system.cpu1.ISSUE:FloatCmp_delay.end_dist

system.cpu1.ISSUE:FloatCvt_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:FloatCvt_delay.samples            0                      
system.cpu1.ISSUE:FloatCvt_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.ISSUE:FloatCvt_delay.max_value            0                      
system.cpu1.ISSUE:FloatCvt_delay.end_dist

system.cpu1.ISSUE:FloatMult_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:FloatMult_delay.samples            0                      
system.cpu1.ISSUE:FloatMult_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.ISSUE:FloatMult_delay.max_value            0                      
system.cpu1.ISSUE:FloatMult_delay.end_dist

system.cpu1.ISSUE:FloatDiv_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:FloatDiv_delay.samples            4                      
system.cpu1.ISSUE:FloatDiv_delay.min_value            0                      
                               0            4  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu1.ISSUE:FloatDiv_delay.max_value            1                      
system.cpu1.ISSUE:FloatDiv_delay.end_dist

system.cpu1.ISSUE:FloatSqrt_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:FloatSqrt_delay.samples            0                      
system.cpu1.ISSUE:FloatSqrt_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.ISSUE:FloatSqrt_delay.max_value            0                      
system.cpu1.ISSUE:FloatSqrt_delay.end_dist

system.cpu1.ISSUE:MemRead_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:MemRead_delay.samples     144042411                      
system.cpu1.ISSUE:MemRead_delay.min_value            0                      
                               0     75038537   5209.48%   5209.48%
                               2       576904     40.05%   5249.53%
                               4       136630      9.49%   5259.01%
                               6        44481      3.09%   5262.10%
                               8        16838      1.17%   5263.27%
                              10     61792128   4289.86%   9553.13%
                              12      6436195    446.83%   9999.95%
                              14          142      0.01%   9999.96%
                              16           76      0.01%   9999.97%
                              18           22      0.00%   9999.97%
                              20            6      0.00%   9999.97%
                              22            5      0.00%   9999.97%
                              24            4      0.00%   9999.97%
                              26           10      0.00%   9999.97%
                              28           11      0.00%   9999.97%
                              30            9      0.00%   9999.97%
                              32           16      0.00%   9999.97%
                              34           17      0.00%   9999.97%
                              36           13      0.00%   9999.97%
                              38            2      0.00%   9999.97%
                              40            0      0.00%   9999.97%
                              42            2      0.00%   9999.97%
                              44            0      0.00%   9999.97%
                              46            3      0.00%   9999.98%
                              48           12      0.00%   9999.98%
                              50           17      0.00%   9999.98%
                              52           15      0.00%   9999.98%
                              54            4      0.00%   9999.98%
                              56            1      0.00%   9999.98%
                              58            1      0.00%   9999.98%
                              60            1      0.00%   9999.98%
                              62            0      0.00%   9999.98%
                              64            7      0.00%   9999.98%
                              66            4      0.00%   9999.98%
                              68            2      0.00%   9999.98%
                              70            7      0.00%   9999.98%
                              72            6      0.00%   9999.98%
                              74            1      0.00%   9999.98%
                              76            3      0.00%   9999.98%
                              78            2      0.00%   9999.98%
                              80            6      0.00%   9999.98%
                              82            1      0.00%   9999.98%
                              84            1      0.00%   9999.98%
                              86            2      0.00%   9999.98%
                              88            3      0.00%   9999.98%
                              90            2      0.00%   9999.98%
                              92            1      0.00%   9999.98%
                              94            1      0.00%   9999.98%
                              96            0      0.00%   9999.98%
                              98            0      0.00%   9999.98%
system.cpu1.ISSUE:MemRead_delay.overflows          260                      
system.cpu1.ISSUE:MemRead_delay.max_value          952                      
system.cpu1.ISSUE:MemRead_delay.end_dist

system.cpu1.ISSUE:MemWrite_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:MemWrite_delay.samples      4858703                      
system.cpu1.ISSUE:MemWrite_delay.min_value            0                      
                               0      4488646   9238.36%   9238.36%
                               2       265456    546.35%   9784.71%
                               4        73467    151.21%   9935.92%
                               6        25787     53.07%   9989.00%
                               8         5097     10.49%   9999.49%
                              10          194      0.40%   9999.88%
                              12            0      0.00%   9999.88%
                              14            4      0.01%   9999.89%
                              16            1      0.00%   9999.90%
                              18            0      0.00%   9999.90%
                              20            1      0.00%   9999.90%
                              22            2      0.00%   9999.90%
                              24            0      0.00%   9999.90%
                              26            0      0.00%   9999.90%
                              28            3      0.01%   9999.91%
                              30            0      0.00%   9999.91%
                              32            4      0.01%   9999.92%
                              34            6      0.01%   9999.93%
                              36            0      0.00%   9999.93%
                              38            0      0.00%   9999.93%
                              40            1      0.00%   9999.93%
                              42            0      0.00%   9999.93%
                              44            0      0.00%   9999.93%
                              46            0      0.00%   9999.93%
                              48            0      0.00%   9999.93%
                              50            0      0.00%   9999.93%
                              52            0      0.00%   9999.93%
                              54            1      0.00%   9999.93%
                              56            0      0.00%   9999.93%
                              58            0      0.00%   9999.93%
                              60            0      0.00%   9999.93%
                              62            0      0.00%   9999.93%
                              64            1      0.00%   9999.93%
                              66            0      0.00%   9999.93%
                              68            3      0.01%   9999.94%
                              70            1      0.00%   9999.94%
                              72            1      0.00%   9999.94%
                              74            0      0.00%   9999.94%
                              76            1      0.00%   9999.95%
                              78            1      0.00%   9999.95%
                              80            1      0.00%   9999.95%
                              82            0      0.00%   9999.95%
                              84            0      0.00%   9999.95%
                              86            1      0.00%   9999.95%
                              88            1      0.00%   9999.95%
                              90            0      0.00%   9999.95%
                              92            0      0.00%   9999.95%
                              94            0      0.00%   9999.95%
                              96            1      0.00%   9999.96%
                              98            1      0.00%   9999.96%
system.cpu1.ISSUE:MemWrite_delay.overflows           20                      
system.cpu1.ISSUE:MemWrite_delay.max_value          946                      
system.cpu1.ISSUE:MemWrite_delay.end_dist

system.cpu1.ISSUE:IprAccess_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:IprAccess_delay.samples       481562                      
system.cpu1.ISSUE:IprAccess_delay.min_value            0                      
                               0       155030   3219.32%   3219.32%
                               2        93630   1944.30%   5163.61%
                               4        92815   1927.37%   7090.99%
                               6        27068    562.09%   7653.07%
                               8        19175    398.18%   8051.26%
                              10        64707   1343.69%   9394.95%
                              12        12533    260.26%   9655.21%
                              14         2756     57.23%   9712.44%
                              16         2790     57.94%   9770.37%
                              18         1347     27.97%   9798.34%
                              20         3746     77.79%   9876.13%
                              22         1577     32.75%   9908.88%
                              24          787     16.34%   9925.22%
                              26         3351     69.59%   9994.81%
                              28           59      1.23%   9996.03%
                              30           44      0.91%   9996.95%
                              32           52      1.08%   9998.03%
                              34           43      0.89%   9998.92%
                              36            5      0.10%   9999.02%
                              38            4      0.08%   9999.11%
                              40           43      0.89%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
system.cpu1.ISSUE:IprAccess_delay.max_value           41                      
system.cpu1.ISSUE:IprAccess_delay.end_dist

system.cpu1.ISSUE:InstPrefetch_delay.start_dist                     # cycles from operands ready to issue
system.cpu1.ISSUE:InstPrefetch_delay.samples            0                      
system.cpu1.ISSUE:InstPrefetch_delay.min_value            0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
system.cpu1.ISSUE:InstPrefetch_delay.max_value            0                      
system.cpu1.ISSUE:InstPrefetch_delay.end_dist

system.cpu1.ISSUE:FU_type_0                 231483011                       # Type of FU issued
system.cpu1.ISSUE:FU_type_0.start_dist
                          (null)         2790      0.00%            # Type of FU issued
                          IntAlu    156886398     67.77%            # Type of FU issued
                         IntMult        15978      0.01%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd         4957      0.00%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv            4      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead     71888088     31.06%            # Type of FU issued
                        MemWrite      2203234      0.95%            # Type of FU issued
                       IprAccess       481562      0.21%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
system.cpu1.ISSUE:FU_type_0.end_dist
system.cpu1.ISSUE:IQ_0:fu_full.start_dist
                          (null)            0      0.00%           
                          IntAlu    189408440     96.53%           
                         IntMult            0      0.00%           
                          IntDiv            0      0.00%           
                        FloatAdd            0      0.00%           
                        FloatCmp            0      0.00%           
                        FloatCvt            0      0.00%           
                       FloatMult            0      0.00%           
                        FloatDiv            0      0.00%           
                       FloatSqrt            0      0.00%           
                         MemRead      4691941      2.39%           
                        MemWrite        99814      0.05%           
                       IprAccess      2007676      1.02%           
                    InstPrefetch            0      0.00%           
system.cpu1.ISSUE:IQ_0:fu_full.end_dist
system.cpu1.ISSUE:MSIPC                      0.000446                       # Misspec issue rate
system.cpu1.ISSUE:addr_loads                    45870                       # number of invalid-address loads
system.cpu1.ISSUE:addr_swpfs                     2589                       # number of invalid-address SW prefetches
system.cpu1.ISSUE:branches                   72080937                       # Number of branches issued
system.cpu1.ISSUE:count                     157386660                       # number of insts issued
system.cpu1.ISSUE:fu_busy_cnt               196207871                       # FU busy when requested
system.cpu1.ISSUE:fu_busy_rate               1.246661                       # FU busy rate (busy events/executed inst)
system.cpu1.ISSUE:fu_full.start_dist
                          (null)            0      0.00%            # attempts to use FU when none available
                          IntAlu    189408440     96.53%            # attempts to use FU when none available
                         IntMult            0      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead      4691941      2.39%            # attempts to use FU when none available
                        MemWrite        99814      0.05%            # attempts to use FU when none available
                       IprAccess      2007676      1.02%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
system.cpu1.ISSUE:fu_full.end_dist
system.cpu1.ISSUE:issued_per_cycle           34826095                       # Number of insts issued each cycle
system.cpu1.ISSUE:issued_per_cycle.start_dist
                               0       842728      2.42%            # Number of insts issued each cycle
                               1      1658861      4.76%            # Number of insts issued each cycle
                               2      1035157      2.97%            # Number of insts issued each cycle
                               3       820119      2.35%            # Number of insts issued each cycle
                               4       601966      1.73%            # Number of insts issued each cycle
                               5       577575      1.66%            # Number of insts issued each cycle
                               6      4894479     14.05%            # Number of insts issued each cycle
                               7      4370345     12.55%            # Number of insts issued each cycle
                               8     20024865     57.50%            # Number of insts issued each cycle
system.cpu1.ISSUE:issued_per_cycle.end_dist
system.cpu1.ISSUE:loads                      72154324                       # number of load insts issued
system.cpu1.ISSUE:lsq_inv_rate                      0                       # Early LSQ issues per cycle
system.cpu1.ISSUE:lsq_invert                        0                       # Number of times LSQ instruction issued early
system.cpu1.ISSUE:misspec_cnt                 3275809                       # Number of misspeculated insts issued
system.cpu1.ISSUE:nop                         3288657                       # number of nop insts issued
system.cpu1.ISSUE:op_count                  231643480                       # number of insts issued
system.cpu1.ISSUE:op_rate                    0.031507                       # Operation issue rate
system.cpu1.ISSUE:rate                       0.021407                       # Inst issue rate
system.cpu1.ISSUE:refs                       74649329                       # number of memory reference insts issued
system.cpu1.ISSUE:stores                      2495005                       # Number of stores issued
system.cpu1.ISSUE:swp                            6455                       # number of swp insts issued
system.cpu1.ISSUE:unissued_cause.start_dist
                          (null)            0      0.00%            # Reason ready instruction not issued
                          IntAlu    189408440     96.57%            # Reason ready instruction not issued
                         IntMult            0      0.00%            # Reason ready instruction not issued
                          IntDiv            0      0.00%            # Reason ready instruction not issued
                        FloatAdd            0      0.00%            # Reason ready instruction not issued
                        FloatCmp            0      0.00%            # Reason ready instruction not issued
                        FloatCvt            0      0.00%            # Reason ready instruction not issued
                       FloatMult            0      0.00%            # Reason ready instruction not issued
                        FloatDiv            0      0.00%            # Reason ready instruction not issued
                       FloatSqrt            0      0.00%            # Reason ready instruction not issued
                         MemRead      4691941      2.39%            # Reason ready instruction not issued
                        MemWrite          294      0.00%            # Reason ready instruction not issued
                       IprAccess      2007676      1.02%            # Reason ready instruction not issued
                    InstPrefetch            0      0.00%            # Reason ready instruction not issued
                  DCache_Blocked        22355      0.01%            # Reason ready instruction not issued
                       Too_Young            0      0.00%            # Reason ready instruction not issued
system.cpu1.ISSUE:unissued_cause.end_dist
system.cpu1.LSQ:RQ:rdy_inst                  84303304                       # Number of ready instructions (cum)
system.cpu1.LSQ:RQ:rdy_inst_dist_0_mean      0.011466                       # standard deviation of ready rate
system.cpu1.LSQ:RQ:rdy_inst_dist_0_stdev     0.218177                       # standard deviation of ready rate
**Ignore: system.cpu1.LSQ:RQ:rdy_inst_dist_0_TOT   7352187940                       # standard deviation of ready rate
system.cpu1.LSQ:RQ:rdy_rate                  0.011466                       # Number of ready insts per cycle
system.cpu1.LSQ:RQ:rdy_x_count               74278305                       # number of insts that become ready (cum)
system.cpu1.LSQ:RQ:rdy_x_max                       32                       # largest number of insts that become ready
system.cpu1.LSQ:RQ:rdy_x_rate                0.010103                       # number of insts that become ready per cycle
system.cpu1.LSQ:avg_residency                5.757858                       # Average IQ residency
system.cpu1.LSQ:blocked_loads                 8520553                       # number of ready loads not issued due to memory disambiguation
system.cpu1.LSQ:cum_num_insts               906210112                       # Total occupancy
system.cpu1.LSQ:current_count                       0                       # Occupancy this cycle
system.cpu1.LSQ:empty_count                7316687938                       # Number of empty cycles
system.cpu1.LSQ:empty_rate                  99.517151                       # Fraction of cycles empty
system.cpu1.LSQ:forw_loads                         57                       # number of loads forwarded via LSQ
system.cpu1.LSQ:full_count                          0                       # Number of full cycles
system.cpu1.LSQ:full_rate                           0                       # Fraction of cycles full
system.cpu1.LSQ:occ_dist_0.start_dist                          # IQ Occupancy per cycle
system.cpu1.LSQ:occ_dist_0.samples         7352187940                      
system.cpu1.LSQ:occ_dist_0.min_value                0                      
                               0   7317776829              9953.20%
                               2      1314316              9954.98%
                               4      1014265              9956.36%
                               6       754139              9957.39%
                               8       505184              9958.08%
                              10       498635              9958.75%
                              12       342267              9959.22%
                              14       304533              9959.63%
                              16       596869              9960.45%
                              18       248434              9960.78%
                              20       196479              9961.05%
                              22       206165              9961.33%
                              24       178499              9961.57%
                              26       177062              9961.82%
                              28     10449546              9976.03%
                              30     14343145              9995.54%
                              32      3281573             10000.00%
system.cpu1.LSQ:occ_dist_0.max_value               32                      
system.cpu1.LSQ:occ_dist_0.end_dist

system.cpu1.LSQ:occ_rate                     0.123257                       # Average occupancy
system.cpu1.LSQ:peak_occupancy                     32                       # Peak IQ occupancy
system.cpu1.REG:fp:full                             0                       # number of cycles where there were no FP registers
system.cpu1.REG:fp:occ                        2208201                       # Cumulative count of FP register usage
system.cpu1.REG:fp:occ_rate                         0                       # Average FP register usage
system.cpu1.REG:int:full                            0                       # number of cycles where there were no INT registers
system.cpu1.REG:int:occ                    1541046833                       # Cumulative count of INT register usage
system.cpu1.REG:int:occ_rate                        0                       # Average INT register usage
system.cpu1.ROB:cap_events                          0                       # number of cycles where ROB cap was active
system.cpu1.ROB:cap_inst                            0                       # number of instructions held up by ROB cap
system.cpu1.ROB:current_count                       0                       # Current ROB occupancy
system.cpu1.ROB:full_count                    1103640                       # number of cycles where ROB was full
system.cpu1.ROB:full_rate                    0.000150                       # ROB full per cycle
system.cpu1.ROB:occ_dist_0.start_dist                          # ROB Occupancy per cycle
system.cpu1.ROB:occ_dist_0.samples         7352187940                      
system.cpu1.ROB:occ_dist_0.min_value                0                      
                               0   7312720482              9946.32%
                               2       829693              9947.45%
                               4       443800              9948.05%
                               6       661564              9948.95%
                               8       907283              9950.18%
                              10       492934              9950.86%
                              12       567780              9951.63%
                              14       394012              9952.16%
                              16       329568              9952.61%
                              18       266090              9952.97%
                              20       321332              9953.41%
                              22       298874              9953.82%
                              24       211468              9954.10%
                              26       190168              9954.36%
                              28       194552              9954.63%
                              30       188520              9954.88%
                              32       126091              9955.06%
                              34       127294              9955.23%
                              36       158992              9955.45%
                              38       164028              9955.67%
                              40        97028              9955.80%
                              42       108879              9955.95%
                              44       114846              9956.10%
                              46       108114              9956.25%
                              48       103865              9956.39%
                              50       126738              9956.57%
                              52       108734              9956.71%
                              54        86334              9956.83%
                              56        82479              9956.94%
                              58        71516              9957.04%
                              60        85062              9957.16%
                              62       100649              9957.29%
                              64        77352              9957.40%
                              66        82932              9957.51%
                              68        89564              9957.63%
                              70        80793              9957.74%
                              72       211789              9958.03%
                              74       123414              9958.20%
                              76        94990              9958.33%
                              78       482950              9958.98%
                              80      3991457              9964.41%
                              82      7915897              9975.18%
                              84     10388526              9989.31%
                              86      5263850              9996.47%
                              88        85243              9996.59%
                              90        76270              9996.69%
                              92        78378              9996.80%
                              94       104755              9996.94%
                              96       136186              9997.12%
                              98        70936              9997.22%
                             100        55189              9997.30%
                             102        52806              9997.37%
                             104        51431              9997.44%
                             106        66469              9997.53%
                             108        48915              9997.59%
                             110        41170              9997.65%
                             112       104086              9997.79%
                             114       102926              9997.93%
                             116        41760              9997.99%
                             118        58344              9998.07%
                             120        44760              9998.13%
                             122        78768              9998.24%
                             124        65471              9998.32%
                             126       122836              9998.49%
                             128      1108958             10000.00%
system.cpu1.ROB:occ_dist_0.max_value              128                      
system.cpu1.ROB:occ_dist_0.end_dist

system.cpu1.ROB:occ_rate                     0.388940                       # ROB occupancy rate
system.cpu1.ROB:occupancy                  2859562168                       # system.cpu1.ROB occupancy (cumulative)
system.cpu1.SB:RQ:rdy_inst                    2596652                       # Number of ready instructions (cum)
system.cpu1.SB:RQ:rdy_inst_dist_0_mean       0.000353                       # standard deviation of ready rate
system.cpu1.SB:RQ:rdy_inst_dist_0_stdev      0.039792                       # standard deviation of ready rate
**Ignore: system.cpu1.SB:RQ:rdy_inst_dist_0_TOT   7352187940                       # standard deviation of ready rate
system.cpu1.SB:RQ:rdy_rate                   0.000353                       # Number of ready insts per cycle
system.cpu1.SB:RQ:rdy_x_count                 2201807                       # number of insts that become ready (cum)
system.cpu1.SB:RQ:rdy_x_max                         8                       # largest number of insts that become ready
system.cpu1.SB:RQ:rdy_x_rate                 0.000299                       # number of insts that become ready per cycle
system.cpu1.SB:full_count                      479084                       # store buffer full events (cumulative)
system.cpu1.SB:full_rate                     0.000065                       # store buffer full rate
system.cpu1.SB:occ_rate                      0.004032                       # store buffer occupancy rate
system.cpu1.SB:occupancy                     29644096                       # store buffer occupancy (cumulative)
system.cpu1.SB:write_barrier_pending_cycles        54793                       # number of cycles write barriers were pending
system.cpu1.SB:write_barriers                    1247                       # number of write barrier operations
system.cpu1.WB:consumers                    160058072                       # num instructions consuming a value
system.cpu1.WB:count                        230953229                       # cumulative count of insts written-back
system.cpu1.WB:fanout                        0.978512                       # average fanout of values written-back
system.cpu1.WB:penalized                            0                       # number of instrctions required to write to 'other' IQ
system.cpu1.WB:penalized_rate                       0                       # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.WB:pred_error.start_dist                           # error in predicted writeback times
system.cpu1.WB:pred_error.samples           230953229                      
system.cpu1.WB:pred_error.min_value            282047                      
                             -10            0      0.00%      0.00%
                              -9            0      0.00%      0.00%
                              -8            0      0.00%      0.00%
                              -7            0      0.00%      0.00%
                              -6            0      0.00%      0.00%
                              -5            0      0.00%      0.00%
                              -4            0      0.00%      0.00%
                              -3            0      0.00%      0.00%
                              -2            0      0.00%      0.00%
                              -1            0      0.00%      0.00%
                               0            0      0.00%      0.00%
                               1            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               3            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               5            0      0.00%      0.00%
                               6            0      0.00%      0.00%
                               7            0      0.00%      0.00%
                               8            0      0.00%      0.00%
                               9            0      0.00%      0.00%
                              10            0      0.00%      0.00%
                              11            0      0.00%      0.00%
                              12            0      0.00%      0.00%
                              13            0      0.00%      0.00%
                              14            0      0.00%      0.00%
                              15            0      0.00%      0.00%
                              16            0      0.00%      0.00%
                              17            0      0.00%      0.00%
                              18            0      0.00%      0.00%
                              19            0      0.00%      0.00%
                              20            0      0.00%      0.00%
                              21            0      0.00%      0.00%
                              22            0      0.00%      0.00%
                              23            0      0.00%      0.00%
                              24            0      0.00%      0.00%
                              25            0      0.00%      0.00%
                              26            0      0.00%      0.00%
                              27            0      0.00%      0.00%
                              28            0      0.00%      0.00%
                              29            0      0.00%      0.00%
                              30            0      0.00%      0.00%
                              31            0      0.00%      0.00%
                              32            0      0.00%      0.00%
                              33            0      0.00%      0.00%
                              34            0      0.00%      0.00%
                              35            0      0.00%      0.00%
                              36            0      0.00%      0.00%
                              37            0      0.00%      0.00%
                              38            0      0.00%      0.00%
                              39            0      0.00%      0.00%
                              40            0      0.00%      0.00%
                              41            0      0.00%      0.00%
                              42            0      0.00%      0.00%
                              43            0      0.00%      0.00%
                              44            0      0.00%      0.00%
                              45            0      0.00%      0.00%
                              46            0      0.00%      0.00%
                              47            0      0.00%      0.00%
                              48            0      0.00%      0.00%
                              49            0      0.00%      0.00%
                              50            0      0.00%      0.00%
                              51            0      0.00%      0.00%
                              52            0      0.00%      0.00%
                              53            0      0.00%      0.00%
                              54            0      0.00%      0.00%
                              55            0      0.00%      0.00%
                              56            0      0.00%      0.00%
                              57            0      0.00%      0.00%
                              58            0      0.00%      0.00%
                              59            0      0.00%      0.00%
                              60            0      0.00%      0.00%
                              61            0      0.00%      0.00%
                              62            0      0.00%      0.00%
                              63            0      0.00%      0.00%
                              64            0      0.00%      0.00%
                              65            0      0.00%      0.00%
                              66            0      0.00%      0.00%
                              67            0      0.00%      0.00%
                              68            0      0.00%      0.00%
                              69            0      0.00%      0.00%
                              70            0      0.00%      0.00%
                              71            0      0.00%      0.00%
                              72            0      0.00%      0.00%
                              73            0      0.00%      0.00%
                              74            0      0.00%      0.00%
                              75            0      0.00%      0.00%
                              76            0      0.00%      0.00%
                              77            0      0.00%      0.00%
                              78            0      0.00%      0.00%
                              79            0      0.00%      0.00%
                              80            0      0.00%      0.00%
                              81            0      0.00%      0.00%
                              82            0      0.00%      0.00%
                              83            0      0.00%      0.00%
                              84            0      0.00%      0.00%
                              85            0      0.00%      0.00%
                              86            0      0.00%      0.00%
                              87            0      0.00%      0.00%
                              88            0      0.00%      0.00%
                              89            0      0.00%      0.00%
                              90            0      0.00%      0.00%
                              91            0      0.00%      0.00%
                              92            0      0.00%      0.00%
                              93            0      0.00%      0.00%
                              94            0      0.00%      0.00%
                              95            0      0.00%      0.00%
                              96            0      0.00%      0.00%
                              97            0      0.00%      0.00%
                              98            0      0.00%      0.00%
                              99            0      0.00%      0.00%
                             100            0      0.00%      0.00%
system.cpu1.WB:pred_error.overflows         230953229                      
system.cpu1.WB:pred_error.max_value        7352469840                      
system.cpu1.WB:pred_error.end_dist

system.cpu1.WB:producers                    156618708                       # num instructions producing a value
system.cpu1.WB:rate                          0.031413                       # insts written-back per cycle
system.cpu1.branch_pred.btb_accuracy         0.999989                       # fraction of BTB targets correct
system.cpu1.branch_pred.btb_correct          69870281                       # num correct BTB predictions
system.cpu1.branch_pred.btb_hit_rate         0.975317                       # BTB hit ratio
system.cpu1.branch_pred.btb_hits             71484878                       # Number of BTB hits
system.cpu1.branch_pred.btb_lookups          73294013                       # Number of BTB lookups
system.cpu1.branch_pred.cond_correct         70346483                       # num correct dir predictions
system.cpu1.branch_pred.cond_predicted       70407760                       # num committed conditional branches
system.cpu1.branch_pred.dir_accuracy         0.999130                       # fraction of predictions correct
system.cpu1.branch_pred.lookup_rate          0.010834                       # Rate of bpred lookups
system.cpu1.branch_pred.lookups              79653595                       # num BP lookups
system.cpu1.branch_pred.ras_accuracy         0.906240                       # fraction of RAS targets correct
system.cpu1.branch_pred.ras_correct            231577                       # num correct RAS predictions
system.cpu1.branch_pred.used_btb             69871065                       # num committed branches using target from BTB
system.cpu1.branch_pred.used_ras               255536                       # num returns predicted using RAS
system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles_no_targets    37.333333                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs                290.854942                       # Average number of references to valid blocks.
system.cpu1.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_no_targets              75                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles_no_targets         2800                       # number of cycles access was blocked
system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
system.cpu1.dcache.demand_accesses           73943624                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency    43.925347                       # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency    36.032533                       # average overall mshr miss latency
system.cpu1.dcache.demand_hits               73010454                       # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency       40989816                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_rate          0.012620                       # miss rate for demand accesses
system.cpu1.dcache.demand_misses               933170                       # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits            682780                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency      9022186                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate     0.003386                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_misses          250390                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.dcache.overall_accesses          73947436                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency    43.924470                       # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency    36.040074                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency   149.604999                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_hits              73013607                       # number of overall hits
system.cpu1.dcache.overall_miss_latency      41017944                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_rate         0.012628                       # miss rate for overall accesses
system.cpu1.dcache.overall_misses              933829                       # number of overall misses
system.cpu1.dcache.overall_mshr_hits           682792                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency      9047392                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate     0.003395                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_misses         251037                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_uncacheable_latency       520775                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses         3481                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu1.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu1.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu1.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.dcache.read_accesses             71745213                       # number of read accesses(hits+misses)
system.cpu1.dcache.read_avg_miss_latency    36.636756                       # average read miss latency
system.cpu1.dcache.read_avg_mshr_miss_latency    32.224921                       # average read mshr miss latency
system.cpu1.dcache.read_avg_mshr_uncacheable_latency    89.541176                       # average read mshr uncacheable latency
system.cpu1.dcache.read_hits                 71266918                       # number of read hits
system.cpu1.dcache.read_miss_latency         17523177                       # number of read miss cycles
system.cpu1.dcache.read_miss_rate            0.006667                       # miss rate for read accesses
system.cpu1.dcache.read_misses                 478295                       # number of read misses
system.cpu1.dcache.read_mshr_hits              303300                       # number of read MSHR hits
system.cpu1.dcache.read_mshr_miss_latency      5639200                       # number of read MSHR miss cycles
system.cpu1.dcache.read_mshr_miss_rate       0.002439                       # mshr miss rate for read accesses
system.cpu1.dcache.read_mshr_misses            174995                       # number of read MSHR misses
system.cpu1.dcache.read_mshr_uncacheable           85                       # number of read MSHR uncacheable
system.cpu1.dcache.read_mshr_uncacheable_latency         7611                       # number of read MSHR uncacheable cycles
system.cpu1.dcache.replacements                250519                       # number of replacements
system.cpu1.dcache.sampled_refs                251031                       # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.dcache.swpf_accesses                 3812                       # number of swpf accesses(hits+misses)
system.cpu1.dcache.swpf_avg_miss_latency    42.682853                       # average swpf miss latency
system.cpu1.dcache.swpf_avg_mshr_miss_latency    38.958269                       # average swpf mshr miss latency
system.cpu1.dcache.swpf_hits                     3153                       # number of swpf hits
system.cpu1.dcache.swpf_miss_latency            28128                       # number of swpf miss cycles
system.cpu1.dcache.swpf_miss_rate            0.172875                       # miss rate for swpf accesses
system.cpu1.dcache.swpf_misses                    659                       # number of swpf misses
system.cpu1.dcache.swpf_mshr_hits                  12                       # number of swpf MSHR hits
system.cpu1.dcache.swpf_mshr_miss_latency        25206                       # number of swpf MSHR miss cycles
system.cpu1.dcache.swpf_mshr_miss_rate       0.169727                       # mshr miss rate for swpf accesses
system.cpu1.dcache.swpf_mshr_misses               647                       # number of swpf MSHR misses
system.cpu1.dcache.tagsinuse               509.627388                       # Cycle average of tags in use
system.cpu1.dcache.total_refs                73013607                       # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle              46795539                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.write_accesses             2198411                       # number of write accesses(hits+misses)
system.cpu1.dcache.write_avg_miss_latency    51.589204                       # average write miss latency
system.cpu1.dcache.write_avg_mshr_miss_latency    44.870164                       # average write mshr miss latency
system.cpu1.dcache.write_avg_mshr_uncacheable_latency   151.108363                       # average write mshr uncacheable latency
system.cpu1.dcache.write_hits                 1743536                       # number of write hits
system.cpu1.dcache.write_miss_latency        23466639                       # number of write miss cycles
system.cpu1.dcache.write_miss_rate           0.206911                       # miss rate for write accesses
system.cpu1.dcache.write_misses                454875                       # number of write misses
system.cpu1.dcache.write_mshr_hits             379480                       # number of write MSHR hits
system.cpu1.dcache.write_mshr_miss_latency      3382986                       # number of write MSHR miss cycles
system.cpu1.dcache.write_mshr_miss_rate      0.034295                       # mshr miss rate for write accesses
system.cpu1.dcache.write_mshr_misses            75395                       # number of write MSHR misses
system.cpu1.dcache.write_mshr_uncacheable         3396                       # number of write MSHR uncacheable
system.cpu1.dcache.write_mshr_uncacheable_latency       513164                       # number of write MSHR uncacheable cycles
system.cpu1.dcache.writebacks                  128854                       # number of writebacks
system.cpu1.dtb.accesses                      1946580                       # DTB accesses
system.cpu1.dtb.acv                            119325                       # DTB access violations
system.cpu1.dtb.hits                         78477393                       # DTB hits
system.cpu1.dtb.misses                         613996                       # DTB misses
system.cpu1.dtb.read_accesses                 1383539                       # DTB read accesses
system.cpu1.dtb.read_acv                        44224                       # DTB read access violations
system.cpu1.dtb.read_hits                    74679587                       # DTB read hits
system.cpu1.dtb.read_misses                    430248                       # DTB read misses
system.cpu1.dtb.write_accesses                 563041                       # DTB write accesses
system.cpu1.dtb.write_acv                       75101                       # DTB write access violations
system.cpu1.dtb.write_hits                    3797806                       # DTB write hits
system.cpu1.dtb.write_misses                   183748                       # DTB write misses
system.cpu1.floss.fetch_0.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
system.cpu1.floss.fetch_0.end_dist
system.cpu1.floss.icache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu1.floss.icache_0.end_dist
system.cpu1.floss.iq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
system.cpu1.floss.iq_full_0.end_dist
system.cpu1.floss.iq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu1.floss.iq_full_dcache_0.end_dist
system.cpu1.floss.iq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu1.floss.iq_full_deps_0.end_dist
system.cpu1.floss.iq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu1.floss.iq_full_fu_0.end_dist
system.cpu1.floss.lsq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
system.cpu1.floss.lsq_full_0.end_dist
system.cpu1.floss.lsq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu1.floss.lsq_full_dcache_0.end_dist
system.cpu1.floss.lsq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu1.floss.lsq_full_deps_0.end_dist
system.cpu1.floss.lsq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu1.floss.lsq_full_fu_0.end_dist
system.cpu1.floss.qfull_0.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
system.cpu1.floss.qfull_0.end_dist
system.cpu1.floss.rob_full_0.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
system.cpu1.floss.rob_full_0.end_dist
system.cpu1.floss.rob_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
system.cpu1.floss.rob_full_dcache_0.end_dist
system.cpu1.floss.rob_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
system.cpu1.floss.rob_full_fu_0.end_dist
system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.icache.avg_refs                246.906996                       # Average number of references to valid blocks.
system.cpu1.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
system.cpu1.icache.blocked_no_targets               0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
system.cpu1.icache.demand_accesses           91472277                       # number of demand (read+write) accesses
system.cpu1.icache.demand_avg_miss_latency    17.391548                       # average overall miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency    20.350054                       # average overall mshr miss latency
system.cpu1.icache.demand_hits               91070411                       # number of demand (read+write) hits
system.cpu1.icache.demand_miss_latency        6989072                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_rate          0.004393                       # miss rate for demand accesses
system.cpu1.icache.demand_misses               401866                       # number of demand (read+write) misses
system.cpu1.icache.demand_mshr_hits              9384                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_miss_latency      7987030                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_rate     0.004291                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_misses          392482                       # number of demand (read+write) MSHR misses
system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu1.icache.overall_accesses          91472277                       # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency    17.391548                       # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency    20.350054                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_hits              91070411                       # number of overall hits
system.cpu1.icache.overall_miss_latency       6989072                       # number of overall miss cycles
system.cpu1.icache.overall_miss_rate         0.004393                       # miss rate for overall accesses
system.cpu1.icache.overall_misses              401866                       # number of overall misses
system.cpu1.icache.overall_mshr_hits             9384                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_miss_latency      7987030                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_rate     0.004291                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_misses         392482                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu1.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu1.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu1.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu1.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.icache.read_accesses             91472277                       # number of read accesses(hits+misses)
system.cpu1.icache.read_avg_miss_latency    17.391548                       # average read miss latency
system.cpu1.icache.read_avg_mshr_miss_latency    20.350054                       # average read mshr miss latency
system.cpu1.icache.read_hits                 91070411                       # number of read hits
system.cpu1.icache.read_miss_latency          6989072                       # number of read miss cycles
system.cpu1.icache.read_miss_rate            0.004393                       # miss rate for read accesses
system.cpu1.icache.read_misses                 401866                       # number of read misses
system.cpu1.icache.read_mshr_hits                9384                       # number of read MSHR hits
system.cpu1.icache.read_mshr_miss_latency      7987030                       # number of read MSHR miss cycles
system.cpu1.icache.read_mshr_miss_rate       0.004291                       # mshr miss rate for read accesses
system.cpu1.icache.read_mshr_misses            392482                       # number of read MSHR misses
system.cpu1.icache.replacements                368333                       # number of replacements
system.cpu1.icache.sampled_refs                368845                       # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.icache.tagsinuse               500.643412                       # Cycle average of tags in use
system.cpu1.icache.total_refs                91070411                       # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle            7313687047                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks                       0                       # number of writebacks
system.cpu1.iq:RQ:rdy_inst                  831967938                       # Number of ready instructions (cum)
system.cpu1.iq:RQ:rdy_inst_dist_0_mean       0.113159                       # standard deviation of ready rate
system.cpu1.iq:RQ:rdy_inst_dist_0_stdev      1.804473                       # standard deviation of ready rate
**Ignore: system.cpu1.iq:RQ:rdy_inst_dist_0_TOT   7352187940                       # standard deviation of ready rate
system.cpu1.iq:RQ:rdy_rate                   0.113159                       # Number of ready insts per cycle
system.cpu1.iq:RQ:rdy_x_count               158426784                       # number of insts that become ready (cum)
system.cpu1.iq:RQ:rdy_x_max                        32                       # largest number of insts that become ready
system.cpu1.iq:RQ:rdy_x_rate                 0.021548                       # number of insts that become ready per cycle
system.cpu1.iq:avg_residency                12.545466                       # Average IQ residency
system.cpu1.iq:cum_num_insts               1974489037                       # Total occupancy
system.cpu1.iq:current_count                        0                       # Occupancy this cycle
system.cpu1.iq:empty_count                 7314368924                       # Number of empty cycles
system.cpu1.iq:empty_rate                   99.485609                       # Fraction of cycles empty
system.cpu1.iq:full_count                    25930578                       # Number of full cycles
system.cpu1.iq:full_rate                     0.352692                       # Fraction of cycles full
system.cpu1.iq:occ_dist_0.start_dist                           # IQ Occupancy per cycle
system.cpu1.iq:occ_dist_0.samples          7352187940                      
system.cpu1.iq:occ_dist_0.min_value                 0                      
                               0   7315204993              9949.70%
                               2      1193841              9951.32%
                               4       931632              9952.59%
                               6       710362              9953.56%
                               8       900174              9954.78%
                              10       507024              9955.47%
                              12       396876              9956.01%
                              14       333201              9956.46%
                              16       347211              9956.93%
                              18       300198              9957.34%
                              20       242986              9957.67%
                              22       213763              9957.96%
                              24       174340              9958.20%
                              26       178905              9958.44%
                              28       203593              9958.72%
                              30       167281              9958.95%
                              32       168386              9959.18%
                              34       185062              9959.43%
                              36       172699              9959.66%
                              38       167444              9959.89%
                              40       116650              9960.05%
                              42       108594              9960.20%
                              44        90955              9960.32%
                              46        79798              9960.43%
                              48        85473              9960.55%
                              50        77404              9960.65%
                              52        73711              9960.75%
                              54        62373              9960.84%
                              56        85101              9960.95%
                              58        65437              9961.04%
                              60        59305              9961.12%
                              62        50797              9961.19%
                              64     28532371             10000.00%
system.cpu1.iq:occ_dist_0.max_value                64                      
system.cpu1.iq:occ_dist_0.end_dist

system.cpu1.iq:occ_rate                      0.268558                       # Average occupancy
system.cpu1.iq:peak_occupancy                      64                       # Peak IQ occupancy
system.cpu1.itb.accesses                      5903927                       # ITB accesses
system.cpu1.itb.acv                             22991                       # ITB acv
system.cpu1.itb.hits                          5836053                       # ITB hits
system.cpu1.itb.misses                          67874                       # ITB misses
system.cpu1.kern.callpal                        79643                       # number of callpals executed
system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
system.cpu1.kern.callpal_wripir                   483      0.61%      0.61% # number of callpals executed
system.cpu1.kern.callpal_wrmces                     1      0.00%      0.61% # number of callpals executed
system.cpu1.kern.callpal_wrfen                      1      0.00%      0.61% # number of callpals executed
system.cpu1.kern.callpal_swpctx                  2568      3.22%      3.83% # number of callpals executed
system.cpu1.kern.callpal_tbi                       10      0.01%      3.85% # number of callpals executed
system.cpu1.kern.callpal_wrent                      7      0.01%      3.86% # number of callpals executed
system.cpu1.kern.callpal_swpipl                 71130     89.31%     93.17% # number of callpals executed
system.cpu1.kern.callpal_rdps                     756      0.95%     94.12% # number of callpals executed
system.cpu1.kern.callpal_wrkgp                      1      0.00%     94.12% # number of callpals executed
system.cpu1.kern.callpal_wrusp                      4      0.01%     94.12% # number of callpals executed
system.cpu1.kern.callpal_rdusp                      3      0.00%     94.13% # number of callpals executed
system.cpu1.kern.callpal_whami                      2      0.00%     94.13% # number of callpals executed
system.cpu1.kern.callpal_rti                     4296      5.39%     99.52% # number of callpals executed
system.cpu1.kern.callpal_callsys                  256      0.32%     99.84% # number of callpals executed
system.cpu1.kern.callpal_imb                      123      0.15%    100.00% # number of callpals executed
system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
system.cpu1.kern.faults                         11682                       # number of faults
system.cpu1.kern.faults_interrupt                2453     21.00%     21.00% # number of faults
system.cpu1.kern.faults_dtb_miss_single          4915     42.07%     63.07% # number of faults
system.cpu1.kern.faults_dtb_miss_double          1383     11.84%     74.91% # number of faults
system.cpu1.kern.faults_dfault                     61      0.52%     75.43% # number of faults
system.cpu1.kern.faults_dfault                     80      0.68%     76.12% # number of faults
system.cpu1.kern.faults_itbmiss                  2712     23.22%     99.33% # number of faults
system.cpu1.kern.faults_iaccvio                    78      0.67%    100.00% # number of faults
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.hwrei                     91327                       # number of hwrei instructions executed
system.cpu1.kern.inst.ivlb                          0                       # number of ivlb instructions executed
system.cpu1.kern.inst.ivle                          0                       # number of ivle instructions executed
system.cpu1.kern.inst.quiesce                    2445                       # number of quiesce instructions executed
system.cpu1.kern.ipl_count                      77880                       # number of times we switched to this ipl
system.cpu1.kern.ipl_count_0                    31407     40.33%     40.33% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_22                    5731      7.36%     47.69% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_30                     577      0.74%     48.43% # number of times we switched to this ipl
system.cpu1.kern.ipl_count_31                   40165     51.57%    100.00% # number of times we switched to this ipl
system.cpu1.kern.ipl_good                       68586                       # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_0                     30438     44.38%     44.38% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_22                     5731      8.36%     52.74% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_30                      577      0.84%     53.58% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good_31                    31840     46.42%    100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_ticks                 7352467913                       # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_0               7319086518     99.55%     99.55% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_22                  977516      0.01%     99.56% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_30                  252568      0.00%     99.56% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks_31                32151311      0.44%    100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used                    0.880663                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_0                  0.969147                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used_31                 0.792730                       # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_good_kernel                 873                      
system.cpu1.kern.mode_good_user                   874                      
system.cpu1.kern.mode_good_idle                     0                      
system.cpu1.kern.mode_good_interrupt                0                      
system.cpu1.kern.mode_switch_kernel             12088                       # number of protection mode switches
system.cpu1.kern.mode_switch_user                 874                       # number of protection mode switches
system.cpu1.kern.mode_switch_idle                   0                       # number of protection mode switches
system.cpu1.kern.mode_switch_interrupt              0                       # number of protection mode switches
system.cpu1.kern.mode_switch_good            0.134779                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_kernel     0.072220                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good_interrupt <err: div-0>                       # fraction of useful protection mode switches
system.cpu1.kern.mode_ticks_kernel         7349605747     99.96%     99.96% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks_user              2862166      0.04%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks_interrupt               0      0.00%    100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context                    2569                       # number of times the context was actually changed
system.cpu1.kern.syscall                          190                       # number of syscalls executed
system.cpu1.kern.syscall_fork                       3      1.58%      1.58% # number of syscalls executed
system.cpu1.kern.syscall_read                      14      7.37%      8.95% # number of syscalls executed
system.cpu1.kern.syscall_write                      3      1.58%     10.53% # number of syscalls executed
system.cpu1.kern.syscall_close                     17      8.95%     19.47% # number of syscalls executed
system.cpu1.kern.syscall_obreak                    20     10.53%     30.00% # number of syscalls executed
system.cpu1.kern.syscall_lseek                      4      2.11%     32.11% # number of syscalls executed
system.cpu1.kern.syscall_getpid                     4      2.11%     34.21% # number of syscalls executed
system.cpu1.kern.syscall_setuid                     2      1.05%     35.26% # number of syscalls executed
system.cpu1.kern.syscall_getuid                     4      2.11%     37.37% # number of syscalls executed
system.cpu1.kern.syscall_dup                        2      1.05%     38.42% # number of syscalls executed
system.cpu1.kern.syscall_open                      29     15.26%     53.68% # number of syscalls executed
system.cpu1.kern.syscall_getgid                     4      2.11%     55.79% # number of syscalls executed
system.cpu1.kern.syscall_sigprocmask                5      2.63%     58.42% # number of syscalls executed
system.cpu1.kern.syscall_ioctl                      6      3.16%     61.58% # number of syscalls executed
system.cpu1.kern.syscall_readlink                   1      0.53%     62.11% # number of syscalls executed
system.cpu1.kern.syscall_execve                     2      1.05%     63.16% # number of syscalls executed
system.cpu1.kern.syscall_pre_F64_stat               7      3.68%     66.84% # number of syscalls executed
system.cpu1.kern.syscall_mmap                      27     14.21%     81.05% # number of syscalls executed
system.cpu1.kern.syscall_munmap                     3      1.58%     82.63% # number of syscalls executed
system.cpu1.kern.syscall_mprotect                   7      3.68%     86.32% # number of syscalls executed
system.cpu1.kern.syscall_gethostname                1      0.53%     86.84% # number of syscalls executed
system.cpu1.kern.syscall_dup2                       1      0.53%     87.37% # number of syscalls executed
system.cpu1.kern.syscall_pre_F64_fstat             13      6.84%     94.21% # number of syscalls executed
system.cpu1.kern.syscall_fcntl                      5      2.63%     96.84% # number of syscalls executed
system.cpu1.kern.syscall_socket                     1      0.53%     97.37% # number of syscalls executed
system.cpu1.kern.syscall_connect                    1      0.53%     97.89% # number of syscalls executed
system.cpu1.kern.syscall_setgid                     2      1.05%     98.95% # number of syscalls executed
system.cpu1.kern.syscall_getrlimit                  1      0.53%     99.47% # number of syscalls executed
system.cpu1.kern.syscall_setsid                     1      0.53%    100.00% # number of syscalls executed
system.cpu1.l2.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.l2.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.l2.avg_refs                      7.595096                       # Average number of references to valid blocks.
system.cpu1.l2.blocked_no_mshrs                     0                       # number of cycles access was blocked
system.cpu1.l2.blocked_no_targets                   0                       # number of cycles access was blocked
system.cpu1.l2.blocked_cycles_no_mshrs              0                       # number of cycles access was blocked
system.cpu1.l2.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.l2.cache_copies                         0                       # number of cache copies performed
system.cpu1.l2.demand_accesses                 619883                       # number of demand (read+write) accesses
system.cpu1.l2.demand_avg_miss_latency      85.745171                       # average overall miss latency
system.cpu1.l2.demand_avg_mshr_miss_latency    69.812158                       # average overall mshr miss latency
system.cpu1.l2.demand_hits                     532762                       # number of demand (read+write) hits
system.cpu1.l2.demand_miss_latency            7470205                       # number of demand (read+write) miss cycles
system.cpu1.l2.demand_miss_rate              0.140544                       # miss rate for demand accesses
system.cpu1.l2.demand_misses                    87121                       # number of demand (read+write) misses
system.cpu1.l2.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.cpu1.l2.demand_mshr_miss_latency       6082105                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2.demand_mshr_miss_rate         0.140544                       # mshr miss rate for demand accesses
system.cpu1.l2.demand_mshr_misses               87121                       # number of demand (read+write) MSHR misses
system.cpu1.l2.fast_writes                          0                       # number of fast writes performed
system.cpu1.l2.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.cpu1.l2.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu1.l2.overall_accesses                748737                       # number of overall (read+write) accesses
system.cpu1.l2.overall_avg_miss_latency     85.514504                       # average overall miss latency
system.cpu1.l2.overall_avg_mshr_miss_latency    69.812158                       # average overall mshr miss latency
system.cpu1.l2.overall_avg_mshr_uncacheable_latency   130.607584                       # average overall mshr uncacheable latency
system.cpu1.l2.overall_hits                    661381                       # number of overall hits
system.cpu1.l2.overall_miss_latency           7470205                       # number of overall miss cycles
system.cpu1.l2.overall_miss_rate             0.116671                       # miss rate for overall accesses
system.cpu1.l2.overall_misses                   87356                       # number of overall misses
system.cpu1.l2.overall_mshr_hits                    0                       # number of overall MSHR hits
system.cpu1.l2.overall_mshr_miss_latency      6082105                       # number of overall MSHR miss cycles
system.cpu1.l2.overall_mshr_miss_rate        0.116357                       # mshr miss rate for overall accesses
system.cpu1.l2.overall_mshr_misses              87121                       # number of overall MSHR misses
system.cpu1.l2.overall_mshr_uncacheable_latency       454645                       # number of overall MSHR uncacheable cycles
system.cpu1.l2.overall_mshr_uncacheable_misses         3481                       # number of overall MSHR uncacheable misses
system.cpu1.l2.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu1.l2.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu1.l2.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu1.l2.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l2.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu1.l2.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.l2.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu1.l2.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu1.l2.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l2.read_accesses                   619883                       # number of read accesses(hits+misses)
system.cpu1.l2.read_avg_miss_latency        85.745171                       # average read miss latency
system.cpu1.l2.read_avg_mshr_miss_latency    69.812158                       # average read mshr miss latency
system.cpu1.l2.read_avg_mshr_uncacheable_latency    70.552941                       # average read mshr uncacheable latency
system.cpu1.l2.read_hits                       532762                       # number of read hits
system.cpu1.l2.read_miss_latency              7470205                       # number of read miss cycles
system.cpu1.l2.read_miss_rate                0.140544                       # miss rate for read accesses
system.cpu1.l2.read_misses                      87121                       # number of read misses
system.cpu1.l2.read_mshr_miss_latency         6082105                       # number of read MSHR miss cycles
system.cpu1.l2.read_mshr_miss_rate           0.140544                       # mshr miss rate for read accesses
system.cpu1.l2.read_mshr_misses                 87121                       # number of read MSHR misses
system.cpu1.l2.read_mshr_uncacheable               85                       # number of read MSHR uncacheable
system.cpu1.l2.read_mshr_uncacheable_latency         5997                       # number of read MSHR uncacheable cycles
system.cpu1.l2.replacements                     82984                       # number of replacements
system.cpu1.l2.sampled_refs                     87080                       # Sample count of references to valid blocks.
system.cpu1.l2.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.l2.tagsinuse                  3748.334169                       # Cycle average of tags in use
system.cpu1.l2.total_refs                      661381                       # Total number of references to valid blocks.
system.cpu1.l2.warmup_cycle                7314260242                       # Cycle when the warmup percentage was hit.
system.cpu1.l2.write_avg_mshr_uncacheable_latency   132.110718                       # average write mshr uncacheable latency
system.cpu1.l2.write_mshr_uncacheable            3396                       # number of write MSHR uncacheable
system.cpu1.l2.write_mshr_uncacheable_latency       448648                       # number of write MSHR uncacheable cycles
system.cpu1.l2.writeback_accesses              128854                       # number of writeback accesses(hits+misses)
system.cpu1.l2.writeback_hits                  128619                       # number of writeback hits
system.cpu1.l2.writeback_miss_rate           0.001824                       # miss rate for writeback accesses
system.cpu1.l2.writeback_misses                   235                       # number of writeback misses
system.cpu1.l2.writeback_mshr_miss_rate      0.001824                       # mshr miss rate for writeback accesses
system.cpu1.l2.writeback_mshr_misses              235                       # number of writeback MSHR misses
system.cpu1.l2.writebacks                       27567                       # number of writebacks
system.cpu1.l3.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.l3.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
system.cpu1.l3.avg_refs                      2.077435                       # Average number of references to valid blocks.
system.cpu1.l3.blocked_no_mshrs                     0                       # number of cycles access was blocked
system.cpu1.l3.blocked_no_targets                   0                       # number of cycles access was blocked
system.cpu1.l3.blocked_cycles_no_mshrs              0                       # number of cycles access was blocked
system.cpu1.l3.blocked_cycles_no_targets            0                       # number of cycles access was blocked
system.cpu1.l3.cache_copies                         0                       # number of cache copies performed
system.cpu1.l3.demand_accesses                  87121                       # number of demand (read+write) accesses
system.cpu1.l3.demand_avg_miss_latency     107.327668                       # average overall miss latency
system.cpu1.l3.demand_avg_mshr_miss_latency    69.886005                       # average overall mshr miss latency
system.cpu1.l3.demand_hits                      49821                       # number of demand (read+write) hits
system.cpu1.l3.demand_miss_latency            4003322                       # number of demand (read+write) miss cycles
system.cpu1.l3.demand_miss_rate              0.428140                       # miss rate for demand accesses
system.cpu1.l3.demand_misses                    37300                       # number of demand (read+write) misses
system.cpu1.l3.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
system.cpu1.l3.demand_mshr_miss_latency       2606748                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l3.demand_mshr_miss_rate         0.428140                       # mshr miss rate for demand accesses
system.cpu1.l3.demand_mshr_misses               37300                       # number of demand (read+write) MSHR misses
system.cpu1.l3.fast_writes                          0                       # number of fast writes performed
system.cpu1.l3.mshr_cap_events                      0                       # number of times MSHR cap was activated
system.cpu1.l3.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.cpu1.l3.overall_accesses                114923                       # number of overall (read+write) accesses
system.cpu1.l3.overall_avg_miss_latency    107.316159                       # average overall miss latency
system.cpu1.l3.overall_avg_mshr_miss_latency    69.886005                       # average overall mshr miss latency
system.cpu1.l3.overall_avg_mshr_uncacheable_latency    89.665039                       # average overall mshr uncacheable latency
system.cpu1.l3.overall_hits                     77619                       # number of overall hits
system.cpu1.l3.overall_miss_latency           4003322                       # number of overall miss cycles
system.cpu1.l3.overall_miss_rate             0.324600                       # miss rate for overall accesses
system.cpu1.l3.overall_misses                   37304                       # number of overall misses
system.cpu1.l3.overall_mshr_hits                    0                       # number of overall MSHR hits
system.cpu1.l3.overall_mshr_miss_latency      2606748                       # number of overall MSHR miss cycles
system.cpu1.l3.overall_mshr_miss_rate        0.324565                       # mshr miss rate for overall accesses
system.cpu1.l3.overall_mshr_misses              37300                       # number of overall MSHR misses
system.cpu1.l3.overall_mshr_uncacheable_latency       312124                       # number of overall MSHR uncacheable cycles
system.cpu1.l3.overall_mshr_uncacheable_misses         3481                       # number of overall MSHR uncacheable misses
system.cpu1.l3.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
system.cpu1.l3.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
system.cpu1.l3.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
system.cpu1.l3.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
system.cpu1.l3.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
system.cpu1.l3.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.l3.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
system.cpu1.l3.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
system.cpu1.l3.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu1.l3.read_accesses                    87121                       # number of read accesses(hits+misses)
system.cpu1.l3.read_avg_miss_latency       107.327668                       # average read miss latency
system.cpu1.l3.read_avg_mshr_miss_latency    69.886005                       # average read mshr miss latency
system.cpu1.l3.read_avg_mshr_uncacheable_latency    30.305882                       # average read mshr uncacheable latency
system.cpu1.l3.read_hits                        49821                       # number of read hits
system.cpu1.l3.read_miss_latency              4003322                       # number of read miss cycles
system.cpu1.l3.read_miss_rate                0.428140                       # miss rate for read accesses
system.cpu1.l3.read_misses                      37300                       # number of read misses
system.cpu1.l3.read_mshr_miss_latency         2606748                       # number of read MSHR miss cycles
system.cpu1.l3.read_mshr_miss_rate           0.428140                       # mshr miss rate for read accesses
system.cpu1.l3.read_mshr_misses                 37300                       # number of read MSHR misses
system.cpu1.l3.read_mshr_uncacheable               85                       # number of read MSHR uncacheable
system.cpu1.l3.read_mshr_uncacheable_latency         2576                       # number of read MSHR uncacheable cycles
system.cpu1.l3.replacements                      6998                       # number of replacements
system.cpu1.l3.sampled_refs                     36831                       # Sample count of references to valid blocks.
system.cpu1.l3.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
system.cpu1.l3.tagsinuse                  5032.550331                       # Cycle average of tags in use
system.cpu1.l3.total_refs                       76514                       # Total number of references to valid blocks.
system.cpu1.l3.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.cpu1.l3.write_avg_mshr_uncacheable_latency    91.150766                       # average write mshr uncacheable latency
system.cpu1.l3.write_mshr_uncacheable            3396                       # number of write MSHR uncacheable
system.cpu1.l3.write_mshr_uncacheable_latency       309548                       # number of write MSHR uncacheable cycles
system.cpu1.l3.writeback_accesses               27802                       # number of writeback accesses(hits+misses)
system.cpu1.l3.writeback_hits                   27798                       # number of writeback hits
system.cpu1.l3.writeback_miss_rate           0.000144                       # miss rate for writeback accesses
system.cpu1.l3.writeback_misses                     4                       # number of writeback misses
system.cpu1.l3.writeback_mshr_miss_rate      0.000144                       # mshr miss rate for writeback accesses
system.cpu1.l3.writeback_mshr_misses                4                       # number of writeback MSHR misses
system.cpu1.l3.writebacks                        3451                       # number of writebacks
system.cpu1.numCycles                      7352187940                       # number of cpu cycles simulated
system.cpu1.toL2Bus.addr_idle_cycles       7351674817                       # number of cycles bus was idle
system.cpu1.toL2Bus.addr_idle_fraction       0.999892                       # fraction of time addr bus was idle
system.cpu1.toL2Bus.addr_queued              3.353599                       # average queueing delay seen by bus request
system.cpu1.toL2Bus.addr_queued_cycles        2666131                       # total number of queued cycles for all requests
system.cpu1.toL2Bus.addr_requests              795006                       # number of transmissions on bus
system.cpu1.toL2Bus.bus_blocked                    71                       # number of times bus was blocked
system.cpu1.toL2Bus.bus_blocked_cycles          18817                       # number of cycles bus was blocked
system.cpu1.toL2Bus.bus_blocked_fraction     0.000003                       # fraction of time bus was blocked
system.cpu1.toL2Bus.data_idle_cycles       7351717599                       # number of cycles bus was idle
system.cpu1.toL2Bus.data_idle_fraction       0.999898                       # fraction of time data bus was idle
system.cpu1.toL2Bus.data_queued              1.017804                       # average queueing delay seen by bus request
system.cpu1.toL2Bus.data_queued_cycles         631005                       # total number of queued cycles for all requests
system.cpu1.toL2Bus.data_requests              619967                       # number of transmissions on bus
system.cpu1.toL2Bus.null_grants                 19769                       # number of null grants (wasted cycles)
system.cpu1.toL3Bus.addr_idle_cycles       7352308645                       # number of cycles bus was idle
system.cpu1.toL3Bus.addr_idle_fraction       0.999978                       # fraction of time addr bus was idle
system.cpu1.toL3Bus.addr_queued              8.229956                       # average queueing delay seen by bus request
system.cpu1.toL3Bus.addr_queued_cycles        1326603                       # total number of queued cycles for all requests
system.cpu1.toL3Bus.addr_requests              161192                       # number of transmissions on bus
system.cpu1.toL3Bus.bus_blocked                    37                       # number of times bus was blocked
system.cpu1.toL3Bus.bus_blocked_cycles          16884                       # number of cycles bus was blocked
system.cpu1.toL3Bus.bus_blocked_fraction     0.000002                       # fraction of time bus was blocked
system.cpu1.toL3Bus.data_idle_cycles       7352351403                       # number of cycles bus was idle
system.cpu1.toL3Bus.data_idle_fraction       0.999984                       # fraction of time data bus was idle
system.cpu1.toL3Bus.data_queued              1.050009                       # average queueing delay seen by bus request
system.cpu1.toL3Bus.data_queued_cycles          91566                       # total number of queued cycles for all requests
system.cpu1.toL3Bus.data_requests               87205                       # number of transmissions on bus
system.cpu1.toL3Bus.null_grants                     0                       # number of null grants (wasted cycles)
system.cpu1inst_class_dist.start_dist
                   All ops ready            0      0.00%            # Operand status at dispatch
                One op not ready            0      0.00%            # Operand status at dispatch
           None rdy, mult chains            0      0.00%            # Operand status at dispatch
           None rdy, one chained            0      0.00%            # Operand status at dispatch
        None rdy, all self-timed            0      0.00%            # Operand status at dispatch
system.cpu1inst_class_dist.end_dist
system.kern.fnCalls                                 0                       # all fn calls being tracked
system.ram.accesses                            538045                       # total number of accesses
system.ram.bytes_requested                          0                       # total number of bytes requested
system.ram.bytes_sent                               0                       # total number of bytes sent
system.ram.compressed_responses                     0                       # total number of accesses that are compressed
system.toMemBus.addr_idle_cycles           7351855085                       # number of cycles bus was idle
system.toMemBus.addr_idle_fraction           0.999916                       # fraction of time addr bus was idle
system.toMemBus.addr_queued                 32.488360                       # average queueing delay seen by bus request
system.toMemBus.addr_queued_cycles           19917379                       # total number of queued cycles for all requests
system.toMemBus.addr_requests                  613062                       # number of transmissions on bus
system.toMemBus.bus_blocked                         0                       # number of times bus was blocked
system.toMemBus.bus_blocked_cycles                  0                       # number of cycles bus was blocked
system.toMemBus.bus_blocked_fraction                0                       # fraction of time bus was blocked
system.toMemBus.data_idle_cycles           7350294622                       # number of cycles bus was idle
system.toMemBus.data_idle_fraction           0.999704                       # fraction of time data bus was idle
system.toMemBus.data_queued                  4.327761                       # average queueing delay seen by bus request
system.toMemBus.data_queued_cycles            1572042                       # total number of queued cycles for all requests
system.toMemBus.data_requests                  363246                       # number of transmissions on bus
system.toMemBus.null_grants                         0                       # number of null grants (wasted cycles)
system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle  <err: div-0>                       # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk    <err: div-0>                       # average number of RxOk's coalesced into each post
system.tsunami.ethernet.coalescedRxOrn   <err: div-0>                       # average number of RxOrn's coalesced into each post
system.tsunami.ethernet.coalescedSwi     <err: div-0>                       # average number of Swi's coalesced into each post
system.tsunami.ethernet.coalescedTotal   <err: div-0>                       # average number of interrupts coalesced into each post
system.tsunami.ethernet.coalescedTxDesc  <err: div-0>                       # average number of TxDesc's coalesced into each post
system.tsunami.ethernet.coalescedTxIdle  <err: div-0>                       # average number of TxIdle's coalesced into each post
system.tsunami.ethernet.coalescedTxOk    <err: div-0>                       # average number of TxOk's coalesced into each post
system.tsunami.ethernet.descDMAReads                0                       # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites               0                       # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.tsunami.ethernet.dma.avg_large_transaction_latency <err: div-0>                       # The average latency of large transactions.
system.tsunami.ethernet.dma.avg_small_transaction_latency <err: div-0>                       # The average latency of small transactions.
system.tsunami.ethernet.dma.avg_transaction_latency <err: div-0>                       # The average latency of all transactions.
system.tsunami.ethernet.dma.bytes_transfered            0                       # Total bytes sent
system.tsunami.ethernet.dma.large_transaction_latency            0                       # The total cycle latency of all large transactions.
system.tsunami.ethernet.dma.large_transactions            0                       # Total number of transactions greater than the block size.
system.tsunami.ethernet.dma.packets_sent            0                       # number of packets sent(blocks)
system.tsunami.ethernet.dma.requests                0                       # Total number of dma requests made
system.tsunami.ethernet.dma.round_trip_latency <err: div-0>                       # Average Round-Trip latency
system.tsunami.ethernet.dma.small_transaction_latency            0                       # The total cycle latency of all small transactions.
system.tsunami.ethernet.dma.small_transactions            0                       # Total number of transactions less than the block size.
system.tsunami.ethernet.dma.total_cycle_latency            0                       # sum of all latencies
system.tsunami.ethernet.dma.transaction_latency            0                       # The total cycle latency of all transactions.
system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
system.tsunami.ethernet.postedInterrupts            0                       # number of posts to CPU
system.tsunami.ethernet.postedRxDesc                0                       # number of RxDesc interrupts posted to CPU
system.tsunami.ethernet.postedRxIdle                0                       # number of rxIdle interrupts posted to CPU
system.tsunami.ethernet.postedRxOk                  0                       # number of RxOk interrupts posted to CPU
system.tsunami.ethernet.postedRxOrn                 0                       # number of RxOrn posted to CPU
system.tsunami.ethernet.postedSwi                   0                       # number of software interrupts posted to CPU
system.tsunami.ethernet.postedTxDesc                0                       # number of TxDesc interrupts posted to CPU
system.tsunami.ethernet.postedTxIdle                0                       # number of TxIdle interrupts posted to CPU
system.tsunami.ethernet.postedTxOk                  0                       # number of TxOk interrupts posted to CPU
system.tsunami.ethernet.totalRxDesc                 0                       # number of total RxDesc written to ISR
system.tsunami.ethernet.totalRxIdle                 0                       # number of total RxIdle written to ISR
system.tsunami.ethernet.totalRxOk                   0                       # number of total RxOk written to ISR
system.tsunami.ethernet.totalRxOrn                  0                       # number of total RxOrn written to ISR
system.tsunami.ethernet.totalSwi                    0                       # number of total Swi written to ISR
system.tsunami.ethernet.totalTxDesc                 0                       # number of total TxDesc written to ISR
system.tsunami.ethernet.totalTxIdle                 0                       # number of total TxIdle written to ISR
system.tsunami.ethernet.totalTxOk                   0                       # number of total TxOk written to ISR
system.tsunami.ide.dma.avg_large_transaction_latency   528.263298                       # The average latency of large transactions.
system.tsunami.ide.dma.avg_small_transaction_latency    44.013158                       # The average latency of small transactions.
system.tsunami.ide.dma.avg_transaction_latency   388.857955                       # The average latency of all transactions.
system.tsunami.ide.dma.bytes_transfered       2531336                       # Total bytes sent
system.tsunami.ide.dma.large_transaction_latency       198627                       # The total cycle latency of all large transactions.
system.tsunami.ide.dma.large_transactions          376                       # Total number of transactions greater than the block size.
system.tsunami.ide.dma.packets_sent             39560                       # number of packets sent(blocks)
system.tsunami.ide.dma.requests                   528                       # Total number of dma requests made
system.tsunami.ide.dma.round_trip_latency   286.045905                       # Average Round-Trip latency
system.tsunami.ide.dma.small_transaction_latency         6690                       # The total cycle latency of all small transactions.
system.tsunami.ide.dma.small_transactions          152                       # Total number of transactions less than the block size.
system.tsunami.ide.dma.total_cycle_latency     11315976                       # sum of all latencies
system.tsunami.ide.dma.transaction_latency       205317                       # The total cycle latency of all transactions.

---------- End Simulation Statistics   ----------
