
---------- Begin Simulation Statistics ----------
cpu.COM:IPB                                  6.177777                       # Committed instructions per branch
cpu.COM:IPB_0                                6.174517                       # Committed instructions per branch
cpu.COM:IPB_1                                6.187812                       # Committed instructions per branch
cpu.COM:IPC                                  2.155084                       # Committed instructions per cycle
cpu.COM:IPC_0                                1.625686                       # Committed instructions per cycle
cpu.COM:IPC_1                                0.529398                       # Committed instructions per cycle
cpu.COM:branches                               214583                       # Number of branches committed
cpu.COM:branches_0                             161956                       # Number of branches committed
cpu.COM:branches_1                              52627                       # Number of branches committed
cpu.COM:bw_lim_avg                            21.5798                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_0                          13.5457                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_1                           8.0340                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_events                           40431                       # number cycles where commit BW limit reached
cpu.COM:bw_lim_rate                            1.4184                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_0                          0.8903                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_1                          0.5281                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_stdev_0_mean                   13.5457                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_0_stdev                  14.4791                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_0_TOT       40431.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_1_mean                    8.0340                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_1_stdev                  20.0407                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_1_TOT       40431.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_limited                             872491                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_0                           547667                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_1                           324824                       # number of insts not committed due to BW limits
cpu.COM:committed_per_cycle.start_dist                         # Number of insts commited each cycle
cpu.COM:committed_per_cycle.samples            327796                      
cpu.COM:committed_per_cycle.min_value               0                      
                               0         3395    103.57%           
                               1        82423   2514.46%           
                               2        58547   1786.08%           
                               3        30471    929.57%           
                               4        27859    849.89%           
                               5        11958    364.80%           
                               6        15090    460.35%           
                               7         9357    285.45%           
                               8        88696   2705.83%           
cpu.COM:committed_per_cycle.max_value               8                      
cpu.COM:committed_per_cycle.end_dist

cpu.COM:count                                 1325646                       # Number of instructions committed
cpu.COM:count_0                               1000000                       # Number of instructions committed
cpu.COM:count_1                                325646                       # Number of instructions committed
cpu.COM:loads                                  377908                       # Number of loads committed
cpu.COM:loads_0                                297370                       # Number of loads committed
cpu.COM:loads_1                                 80538                       # Number of loads committed
cpu.COM:membars                                     0                       # Number of memory barriers committed
cpu.COM:membars_0                                   0                       # Number of memory barriers committed
cpu.COM:membars_1                                   0                       # Number of memory barriers committed
cpu.COM:refs                                   511043                       # Number of memory references committed
cpu.COM:refs_0                                 392508                       # Number of memory references committed
cpu.COM:refs_1                                 118535                       # Number of memory references committed
cpu.COM:stores                                 133135                       # Number of stores committed
cpu.COM:stores_0                                95138                       # Number of stores committed
cpu.COM:stores_1                                37997                       # Number of stores committed
cpu.COM:swp_count                                2117                       # Number of s/w prefetches committed
cpu.COM:swp_count_0                              1316                       # Number of s/w prefetches committed
cpu.COM:swp_count_1                               801                       # Number of s/w prefetches committed
cpu.DDQ:count                                89498340                       # cum count of instructions
cpu.DDQ:count_0                              59977303                       # cum count of instructions
cpu.DDQ:count_1                              29521037                       # cum count of instructions
cpu.DDQ:rate                                      145                       # average number of instructions
cpu.DDQ:rate_0                                     98                       # average number of instructions
cpu.DDQ:rate_1                                     48                       # average number of instructions
cpu.DIS:chain_creation.start_dist
     Inst has no outstanding IDEPS            0      0.00%            # Reason that chain head was created
      IDEP chain reached max depth            0      0.00%            # Reason that chain head was created
                    Inst is a load            0      0.00%            # Reason that chain head was created
  Chain has multiple chained IDEPS            0      0.00%            # Reason that chain head was created
cpu.DIS:chain_creation.end_dist
cpu.DIS:chain_head_frac                             0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_0                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_1                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_heads                                 0                       # number insts that are chain heads
cpu.DIS:chain_heads_0                               0                       # number insts that are chain heads
cpu.DIS:chain_heads_1                               0                       # number insts that are chain heads
cpu.DIS:chains_insuf                                0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_0                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_1                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_rate                           0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_0                         0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_1                         0                       # rate that thread had insuf chains
cpu.DIS:count                                 1994687                       # cumulative count of dispatched insts
cpu.DIS:count_0                               1433668                       # cumulative count of dispatched insts
cpu.DIS:count_1                                561019                       # cumulative count of dispatched insts
cpu.DIS:insufficient_chains                         0                       # Number of instances where dispatch stopped
cpu.DIS:mod_n_stall_avg_free                 no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_0               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_1               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_frac                            0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_0                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_1                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_free                            0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_0                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_1                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls                                0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_0                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_1                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:one_rdy_insts                               0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_0                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_1                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_ratio                        no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_0                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_1                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:op_count                              2762181                       # number of operations dispatched
cpu.DIS:op_count_0                            1994446                       # number of operations dispatched
cpu.DIS:op_count_1                             767735                       # number of operations dispatched
cpu.DIS:op_rate                              4.490439                       # dispatched operations per cycle
cpu.DIS:op_rate_0                            3.242343                       # dispatched operations per cycle
cpu.DIS:op_rate_1                            1.248096                       # dispatched operations per cycle
cpu.DIS:rate                                 3.242734                       # dispatched_insts per cycle
cpu.DIS:rate_0                               2.330694                       # dispatched_insts per cycle
cpu.DIS:rate_1                               0.912041                       # dispatched_insts per cycle
cpu.DIS:second_choice_clust                         0                       # Number of instructions dispatched to second-choice cluster
cpu.DIS:second_choice_stall                         0                       # Number of instructions stalled when first choice not available
cpu.DIS:serialize_stall_cycles                      0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_0                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_1                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serializing_insts                           0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_0                         0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_1                         0                       # count of serializing insts dispatched
cpu.DIS:two_input_insts                             0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_0                           0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_1                           0                       # Number of two input instructions queued
cpu.DIS:two_input_ratio                             0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_0                           0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_1                           0                       # fraction of all insts having 2 inputs
cpu.FETCH:branch_count                         424815                       # Number of branches fetched
cpu.FETCH:branch_count_0                       296694                       # Number of branches fetched
cpu.FETCH:branch_count_1                       128121                       # Number of branches fetched
cpu.FETCH:branch_rate                        0.690616                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_0                      0.482331                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_1                      0.208284                       # Number of branch fetches per cycle
cpu.FETCH:chance_pct_0                       0.708860                       # Percentage of all fetch chances
cpu.FETCH:chance_pct_1                       0.291140                       # Percentage of all fetch chances
cpu.FETCH:chances                              466996                       # Number of fetch opportunities
cpu.FETCH:chances_0                            331035                       # Number of fetch opportunities
cpu.FETCH:chances_1                            135961                       # Number of fetch opportunities
cpu.FETCH:choice                               466996                       # Number of times we fetched from our first choice
cpu.FETCH:choice.start_dist
                               0       466996    100.00%            # Number of times we fetched from our first choice
                               1            0      0.00%            # Number of times we fetched from our first choice
cpu.FETCH:choice.end_dist
cpu.FETCH:count                               3155378                       # Number of instructions fetched
cpu.FETCH:count_0                             2121084                       # Number of instructions fetched
cpu.FETCH:count_1                             1034294                       # Number of instructions fetched
cpu.FETCH:decisions                            466996                       # number of times the fetch stage chose between threads
cpu.FETCH:idle_cycles                          148129                       # number of cycles where fetch stage was idle
cpu.FETCH:idle_icache_blocked_cycles                0                       # number of cycles where fetch was idle due to icache blocked
cpu.FETCH:idle_rate                             24.08                       # percent of cycles fetch stage was idle
cpu.FETCH:prio_changes                              0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_0                            0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_1                            0                       # Number of times priorities were changed
cpu.FETCH:rate                               5.129653                       # Number of inst fetches per cycle
cpu.FETCH:rate_0                             3.448216                       # Number of inst fetches per cycle
cpu.FETCH:rate_1                             1.681437                       # Number of inst fetches per cycle
cpu.FETCH:rate_dist.start_dist                                 # Number of instructions fetched each cycle (Total)
cpu.FETCH:rate_dist.samples                    466996                      
cpu.FETCH:rate_dist.min_value                       0                      
                               0         1943     41.61%           
                               1        17377    372.10%           
                               2        17226    368.87%           
                               3        20269    434.03%           
                               4        16259    348.16%           
                               5        19208    411.31%           
                               6        53243   1140.12%           
                               7         9560    204.71%           
                               8       311911   6679.09%           
cpu.FETCH:rate_dist.max_value                       8                      
cpu.FETCH:rate_dist.end_dist

cpu.FETCH:rate_dist_0.start_dist                               # Number of instructions fetched each cycle (Thread 0)
cpu.FETCH:rate_dist_0.samples                  331035                      
cpu.FETCH:rate_dist_0.min_value                     0                      
                               0          673     20.33%           
                               1        15903    480.40%           
                               2        16062    485.21%           
                               3        19139    578.16%           
                               4        14532    438.99%           
                               5        17755    536.35%           
                               6        50254   1518.09%           
                               7         6523    197.05%           
                               8       190194   5745.43%           
cpu.FETCH:rate_dist_0.max_value                     8                      
cpu.FETCH:rate_dist_0.end_dist

cpu.FETCH:rate_dist_1.start_dist                               # Number of instructions fetched each cycle (Thread 1)
cpu.FETCH:rate_dist_1.samples                  135961                      
cpu.FETCH:rate_dist_1.min_value                     0                      
                               0         1270     93.41%           
                               1         1474    108.41%           
                               2         1164     85.61%           
                               3         1130     83.11%           
                               4         1727    127.02%           
                               5         1453    106.87%           
                               6         2989    219.84%           
                               7         3037    223.37%           
                               8       121717   8952.35%           
cpu.FETCH:rate_dist_1.max_value                     8                      
cpu.FETCH:rate_dist_1.end_dist

cpu.IFQ:count                                19989497                       # cumulative IFQ occupancy
cpu.IFQ:full_count                             422698                       # cumulative IFQ full count
cpu.IFQ:full_count_0                           289153                       # cumulative IFQ full count
cpu.IFQ:full_count_1                           133545                       # cumulative IFQ full count
cpu.IFQ:full_rate                           68.717415                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_0                         47.007194                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_1                         21.710221                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:latency                             10.021370                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_0                           13.942905                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_1                           35.630695                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:occupancy                           32.496642                       # avg IFQ occupancy (inst's)
cpu.IFQ:qfull_iq_occ                         17185552                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_0                        8094601                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_1                        9090951                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_0.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_0.samples            288048                      
cpu.IFQ:qfull_iq_occ_dist_0.min_value               0                      
                               0       124226   4312.68%           
                              10        19327    670.96%           
                              20        12940    449.23%           
                              30        23092    801.67%           
                              40        13891    482.25%           
                              50        22639    785.95%           
                              60        71933   2497.26%           
cpu.IFQ:qfull_iq_occ_dist_0.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_0.end_dist

cpu.IFQ:qfull_iq_occ_dist_1.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_1.samples            288048                      
cpu.IFQ:qfull_iq_occ_dist_1.min_value               0                      
                               0       114808   3985.72%           
                              10        11667    405.04%           
                              20         8872    308.00%           
                              30        19629    681.45%           
                              40        13128    455.76%           
                              50        35833   1243.99%           
                              60        84111   2920.03%           
cpu.IFQ:qfull_iq_occ_dist_1.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_1.end_dist

cpu.IFQ:qfull_rob_occ                        28414982                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_0                      14930509                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_1                      13484473                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_0.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_0.samples           288048                      
cpu.IFQ:qfull_rob_occ_dist_0.min_value              0                      
                               0        94390   3276.88%           
                              10         9437    327.62%           
                              20        17198    597.05%           
                              30        12576    436.59%           
                              40        15228    528.66%           
                              50        15193    527.45%           
                              60         9612    333.69%           
                              70        16381    568.69%           
                              80        21919    760.95%           
                              90        17906    621.63%           
                             100        12377    429.69%           
                             110        37499   1301.83%           
                             120         1137     39.47%           
                             130          652     22.64%           
                             140          369     12.81%           
                             150          587     20.38%           
                             160          322     11.18%           
                             170          292     10.14%           
                             180          950     32.98%           
                             190         4023    139.66%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_0.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_0.end_dist

cpu.IFQ:qfull_rob_occ_dist_1.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_1.samples           288048                      
cpu.IFQ:qfull_rob_occ_dist_1.min_value              0                      
                               0        93761   3255.05%           
                              10         9177    318.59%           
                              20         6714    233.09%           
                              30         7466    259.19%           
                              40        11825    410.52%           
                              50        15847    550.15%           
                              60        36313   1260.66%           
                              70        88175   3061.12%           
                              80         4741    164.59%           
                              90         1860     64.57%           
                             100         1777     61.69%           
                             110         1090     37.84%           
                             120         1961     68.08%           
                             130          619     21.49%           
                             140         1134     39.37%           
                             150         1227     42.60%           
                             160         1097     38.08%           
                             170          616     21.39%           
                             180          604     20.97%           
                             190         2044     70.96%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_1.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_1.end_dist

cpu.IQ:cap_events                                   0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_0                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_1                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_inst                                     0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_0                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_1                                   0                       # number of instructions held up by IQ cap
cpu.IQ:residence:(null).start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:(null).samples                     0                      
cpu.IQ:residence:(null).min_value                   0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:(null).max_value                   0                      
cpu.IQ:residence:(null).end_dist

cpu.IQ:residence:IntAlu.start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:IntAlu.samples               1001558                      
cpu.IQ:residence:IntAlu.min_value                   1                      
                               0       166789   1665.30%   1665.30%
                               2       118779   1185.94%   2851.24%
                               4        78354    782.32%   3633.56%
                               6        94871    947.23%   4580.79%
                               8        88627    884.89%   5465.68%
                              10        84106    839.75%   6305.44%
                              12        54951    548.66%   6854.09%
                              14        42813    427.46%   7281.56%
                              16        31941    318.91%   7600.47%
                              18        38156    380.97%   7981.43%
                              20        24984    249.45%   8230.89%
                              22        17406    173.79%   8404.68%
                              24        16634    166.08%   8570.76%
                              26        12926    129.06%   8699.82%
                              28        11936    119.17%   8818.99%
                              30         8759     87.45%   8906.44%
                              32        11340    113.22%   9019.67%
                              34        12174    121.55%   9141.22%
                              36         9347     93.32%   9234.54%
                              38         9641     96.26%   9330.80%
                              40        10128    101.12%   9431.93%
                              42         9074     90.60%   9522.52%
                              44         7630     76.18%   9598.71%
                              46         6463     64.53%   9663.23%
                              48         1692     16.89%   9680.13%
                              50          456      4.55%   9684.68%
                              52          383      3.82%   9688.51%
                              54           84      0.84%   9689.34%
                              56           96      0.96%   9690.30%
                              58           77      0.77%   9691.07%
                              60          100      1.00%   9692.07%
                              62          103      1.03%   9693.10%
                              64          127      1.27%   9694.37%
                              66          112      1.12%   9695.48%
                              68          109      1.09%   9696.57%
                              70           93      0.93%   9697.50%
                              72           86      0.86%   9698.36%
                              74           87      0.87%   9699.23%
                              76           86      0.86%   9700.09%
                              78          113      1.13%   9701.22%
                              80           83      0.83%   9702.04%
                              82          144      1.44%   9703.48%
                              84          197      1.97%   9705.45%
                              86          165      1.65%   9707.10%
                              88          158      1.58%   9708.67%
                              90          127      1.27%   9709.94%
                              92          190      1.90%   9711.84%
                              94          176      1.76%   9713.60%
                              96          221      2.21%   9715.80%
                              98          200      2.00%   9717.80%
cpu.IQ:residence:IntAlu.overflows               28264                      
cpu.IQ:residence:IntAlu.max_value                1109                      
cpu.IQ:residence:IntAlu.end_dist

cpu.IQ:residence:IntMult.start_dist                            # cycles from dispatch to issue
cpu.IQ:residence:IntMult.samples                  549                      
cpu.IQ:residence:IntMult.min_value                  1                      
                               0           87   1584.70%   1584.70%
                               2          104   1894.35%   3479.05%
                               4           55   1001.82%   4480.87%
                               6          129   2349.73%   6830.60%
                               8           70   1275.05%   8105.65%
                              10           44    801.46%   8907.10%
                              12           24    437.16%   9344.26%
                              14            7    127.50%   9471.77%
                              16            6    109.29%   9581.06%
                              18            2     36.43%   9617.49%
                              20            0      0.00%   9617.49%
                              22            2     36.43%   9653.92%
                              24            1     18.21%   9672.13%
                              26            1     18.21%   9690.35%
                              28            5     91.07%   9781.42%
                              30            1     18.21%   9799.64%
                              32            5     91.07%   9890.71%
                              34            5     91.07%   9981.79%
                              36            0      0.00%   9981.79%
                              38            0      0.00%   9981.79%
                              40            0      0.00%   9981.79%
                              42            0      0.00%   9981.79%
                              44            0      0.00%   9981.79%
                              46            0      0.00%   9981.79%
                              48            0      0.00%   9981.79%
                              50            0      0.00%   9981.79%
                              52            0      0.00%   9981.79%
                              54            0      0.00%   9981.79%
                              56            0      0.00%   9981.79%
                              58            0      0.00%   9981.79%
                              60            0      0.00%   9981.79%
                              62            0      0.00%   9981.79%
                              64            0      0.00%   9981.79%
                              66            0      0.00%   9981.79%
                              68            0      0.00%   9981.79%
                              70            0      0.00%   9981.79%
                              72            0      0.00%   9981.79%
                              74            0      0.00%   9981.79%
                              76            0      0.00%   9981.79%
                              78            0      0.00%   9981.79%
                              80            0      0.00%   9981.79%
                              82            0      0.00%   9981.79%
                              84            0      0.00%   9981.79%
                              86            0      0.00%   9981.79%
                              88            0      0.00%   9981.79%
                              90            0      0.00%   9981.79%
                              92            0      0.00%   9981.79%
                              94            0      0.00%   9981.79%
                              96            0      0.00%   9981.79%
                              98            0      0.00%   9981.79%
cpu.IQ:residence:IntMult.overflows                  1                      
cpu.IQ:residence:IntMult.max_value                111                      
cpu.IQ:residence:IntMult.end_dist

cpu.IQ:residence:IntDiv.start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:IntDiv.samples                     0                      
cpu.IQ:residence:IntDiv.min_value                   0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:IntDiv.max_value                   0                      
cpu.IQ:residence:IntDiv.end_dist

cpu.IQ:residence:FloatAdd.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatAdd.samples                  48                      
cpu.IQ:residence:FloatAdd.min_value                 2                      
                               0            0      0.00%      0.00%
                               2            7   1458.33%   1458.33%
                               4            5   1041.67%   2500.00%
                               6            1    208.33%   2708.33%
                               8            3    625.00%   3333.33%
                              10           10   2083.33%   5416.67%
                              12            8   1666.67%   7083.33%
                              14            5   1041.67%   8125.00%
                              16            1    208.33%   8333.33%
                              18            1    208.33%   8541.67%
                              20            0      0.00%   8541.67%
                              22            3    625.00%   9166.67%
                              24            0      0.00%   9166.67%
                              26            2    416.67%   9583.33%
                              28            2    416.67%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.IQ:residence:FloatAdd.max_value                29                      
cpu.IQ:residence:FloatAdd.end_dist

cpu.IQ:residence:FloatCmp.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatCmp.samples                   0                      
cpu.IQ:residence:FloatCmp.min_value                 0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:FloatCmp.max_value                 0                      
cpu.IQ:residence:FloatCmp.end_dist

cpu.IQ:residence:FloatCvt.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatCvt.samples                  61                      
cpu.IQ:residence:FloatCvt.min_value                 1                      
                               0           16   2622.95%   2622.95%
                               2            7   1147.54%   3770.49%
                               4            1    163.93%   3934.43%
                               6            3    491.80%   4426.23%
                               8            5    819.67%   5245.90%
                              10           11   1803.28%   7049.18%
                              12            9   1475.41%   8524.59%
                              14            0      0.00%   8524.59%
                              16            0      0.00%   8524.59%
                              18            1    163.93%   8688.52%
                              20            1    163.93%   8852.46%
                              22            1    163.93%   9016.39%
                              24            2    327.87%   9344.26%
                              26            0      0.00%   9344.26%
                              28            2    327.87%   9672.13%
                              30            2    327.87%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.IQ:residence:FloatCvt.max_value                30                      
cpu.IQ:residence:FloatCvt.end_dist

cpu.IQ:residence:FloatMult.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:FloatMult.samples                  0                      
cpu.IQ:residence:FloatMult.min_value                0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:FloatMult.max_value                0                      
cpu.IQ:residence:FloatMult.end_dist

cpu.IQ:residence:FloatDiv.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatDiv.samples                  10                      
cpu.IQ:residence:FloatDiv.min_value                 5                      
                               0            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               4            1   1000.00%   1000.00%
                               6            1   1000.00%   2000.00%
                               8            0      0.00%   2000.00%
                              10            2   2000.00%   4000.00%
                              12            1   1000.00%   5000.00%
                              14            2   2000.00%   7000.00%
                              16            3   3000.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.IQ:residence:FloatDiv.max_value                17                      
cpu.IQ:residence:FloatDiv.end_dist

cpu.IQ:residence:FloatSqrt.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:FloatSqrt.samples                  0                      
cpu.IQ:residence:FloatSqrt.min_value                0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:FloatSqrt.max_value                0                      
cpu.IQ:residence:FloatSqrt.end_dist

cpu.IQ:residence:MemRead.start_dist                            # cycles from dispatch to issue
cpu.IQ:residence:MemRead.samples               958894                      
cpu.IQ:residence:MemRead.min_value                  1                      
                               0       118316   1233.88%   1233.88%
                               2       186531   1945.27%   3179.15%
                               4        98585   1028.11%   4207.26%
                               6       117356   1223.87%   5431.13%
                               8       100674   1049.90%   6481.03%
                              10        79951    833.78%   7314.81%
                              12        44847    467.70%   7782.51%
                              14        41040    427.99%   8210.50%
                              16        19818    206.68%   8417.18%
                              18        14138    147.44%   8564.62%
                              20        16716    174.33%   8738.94%
                              22        12756    133.03%   8871.97%
                              24         9285     96.83%   8968.80%
                              26         7475     77.95%   9046.76%
                              28        11311    117.96%   9164.71%
                              30         8481     88.45%   9253.16%
                              32         8729     91.03%   9344.19%
                              34        13897    144.93%   9489.12%
                              36         9072     94.61%   9583.73%
                              38         5061     52.78%   9636.51%
                              40         4335     45.21%   9681.72%
                              42         4680     48.81%   9730.52%
                              44         2182     22.76%   9753.28%
                              46         1168     12.18%   9765.46%
                              48         1124     11.72%   9777.18%
                              50          282      2.94%   9780.12%
                              52          103      1.07%   9781.20%
                              54           74      0.77%   9781.97%
                              56           69      0.72%   9782.69%
                              58           67      0.70%   9783.39%
                              60           67      0.70%   9784.08%
                              62           82      0.86%   9784.94%
                              64          114      1.19%   9786.13%
                              66           95      0.99%   9787.12%
                              68           94      0.98%   9788.10%
                              70           60      0.63%   9788.73%
                              72           77      0.80%   9789.53%
                              74           92      0.96%   9790.49%
                              76           89      0.93%   9791.42%
                              78           97      1.01%   9792.43%
                              80           85      0.89%   9793.31%
                              82          127      1.32%   9794.64%
                              84          150      1.56%   9796.20%
                              86          147      1.53%   9797.74%
                              88          124      1.29%   9799.03%
                              90          105      1.10%   9800.12%
                              92          136      1.42%   9801.54%
                              94          113      1.18%   9802.72%
                              96          144      1.50%   9804.22%
                              98          117      1.22%   9805.44%
cpu.IQ:residence:MemRead.overflows              18656                      
cpu.IQ:residence:MemRead.max_value                974                      
cpu.IQ:residence:MemRead.end_dist

cpu.IQ:residence:MemWrite.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:MemWrite.samples              354556                      
cpu.IQ:residence:MemWrite.min_value                 1                      
                               0        49281   1389.94%   1389.94%
                               2       100881   2845.28%   4235.21%
                               4        48765   1375.38%   5610.59%
                               6        36501   1029.48%   6640.08%
                               8        29234    824.52%   7464.60%
                              10        23067    650.59%   8115.19%
                              12        14826    418.16%   8533.35%
                              14         9242    260.66%   8794.01%
                              16         6699    188.94%   8982.95%
                              18         9312    262.64%   9245.59%
                              20         3790    106.89%   9352.49%
                              22         2065     58.24%   9410.73%
                              24         4450    125.51%   9536.24%
                              26         1980     55.84%   9592.08%
                              28         1136     32.04%   9624.12%
                              30         1844     52.01%   9676.13%
                              32         2176     61.37%   9737.50%
                              34         1067     30.09%   9767.60%
                              36          874     24.65%   9792.25%
                              38          431     12.16%   9804.40%
                              40          566     15.96%   9820.37%
                              42         1394     39.32%   9859.68%
                              44          721     20.34%   9880.02%
                              46          362     10.21%   9890.23%
                              48          327      9.22%   9899.45%
                              50           79      2.23%   9901.68%
                              52          193      5.44%   9907.12%
                              54          118      3.33%   9910.45%
                              56           22      0.62%   9911.07%
                              58           16      0.45%   9911.52%
                              60           22      0.62%   9912.14%
                              62           15      0.42%   9912.57%
                              64           12      0.34%   9912.91%
                              66           10      0.28%   9913.19%
                              68           16      0.45%   9913.64%
                              70           30      0.85%   9914.48%
                              72           18      0.51%   9914.99%
                              74           28      0.79%   9915.78%
                              76           21      0.59%   9916.37%
                              78           40      1.13%   9917.50%
                              80           44      1.24%   9918.74%
                              82           20      0.56%   9919.31%
                              84           13      0.37%   9919.67%
                              86           25      0.71%   9920.38%
                              88           20      0.56%   9920.94%
                              90           18      0.51%   9921.45%
                              92           15      0.42%   9921.87%
                              94           28      0.79%   9922.66%
                              96           19      0.54%   9923.20%
                              98           29      0.82%   9924.02%
cpu.IQ:residence:MemWrite.overflows              2694                      
cpu.IQ:residence:MemWrite.max_value               763                      
cpu.IQ:residence:MemWrite.end_dist

cpu.IQ:residence:IprAccess.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:IprAccess.samples                  0                      
cpu.IQ:residence:IprAccess.min_value                0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:IprAccess.max_value                0                      
cpu.IQ:residence:IprAccess.end_dist

cpu.IQ:residence:InstPrefetch.start_dist                       # cycles from dispatch to issue
cpu.IQ:residence:InstPrefetch.samples               0                      
cpu.IQ:residence:InstPrefetch.min_value             0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:InstPrefetch.max_value             0                      
cpu.IQ:residence:InstPrefetch.end_dist

cpu.ISSUE:(null)_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:(null)_delay.samples                      0                      
cpu.ISSUE:(null)_delay.min_value                    0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:(null)_delay.max_value                    0                      
cpu.ISSUE:(null)_delay.end_dist

cpu.ISSUE:IntAlu_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:IntAlu_delay.samples                1001558                      
cpu.ISSUE:IntAlu_delay.min_value                    0                      
                               0       838420   8371.16%   8371.16%
                               2        84518    843.87%   9215.02%
                               4        33039    329.88%   9544.90%
                               6        18552    185.23%   9730.13%
                               8        20802    207.70%   9937.83%
                              10         6072     60.63%   9998.45%
                              12          155      1.55%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:IntAlu_delay.max_value                   13                      
cpu.ISSUE:IntAlu_delay.end_dist

cpu.ISSUE:IntMult_delay.start_dist                             # cycles from operands ready to issue
cpu.ISSUE:IntMult_delay.samples                   549                      
cpu.ISSUE:IntMult_delay.min_value                   0                      
                               0          484   8816.03%   8816.03%
                               2           62   1129.33%   9945.36%
                               4            3     54.64%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:IntMult_delay.max_value                   4                      
cpu.ISSUE:IntMult_delay.end_dist

cpu.ISSUE:IntDiv_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:IntDiv_delay.samples                      0                      
cpu.ISSUE:IntDiv_delay.min_value                    0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:IntDiv_delay.max_value                    0                      
cpu.ISSUE:IntDiv_delay.end_dist

cpu.ISSUE:FloatAdd_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatAdd_delay.samples                   48                      
cpu.ISSUE:FloatAdd_delay.min_value                  0                      
                               0           47   9791.67%   9791.67%
                               2            0      0.00%   9791.67%
                               4            0      0.00%   9791.67%
                               6            1    208.33%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatAdd_delay.max_value                  7                      
cpu.ISSUE:FloatAdd_delay.end_dist

cpu.ISSUE:FloatCmp_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatCmp_delay.samples                    0                      
cpu.ISSUE:FloatCmp_delay.min_value                  0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:FloatCmp_delay.max_value                  0                      
cpu.ISSUE:FloatCmp_delay.end_dist

cpu.ISSUE:FloatCvt_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatCvt_delay.samples                   61                      
cpu.ISSUE:FloatCvt_delay.min_value                  0                      
                               0           58   9508.20%   9508.20%
                               2            3    491.80%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatCvt_delay.max_value                  2                      
cpu.ISSUE:FloatCvt_delay.end_dist

cpu.ISSUE:FloatMult_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:FloatMult_delay.samples                   0                      
cpu.ISSUE:FloatMult_delay.min_value                 0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:FloatMult_delay.max_value                 0                      
cpu.ISSUE:FloatMult_delay.end_dist

cpu.ISSUE:FloatDiv_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatDiv_delay.samples                   10                      
cpu.ISSUE:FloatDiv_delay.min_value                  0                      
                               0           10  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatDiv_delay.max_value                  0                      
cpu.ISSUE:FloatDiv_delay.end_dist

cpu.ISSUE:FloatSqrt_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:FloatSqrt_delay.samples                   0                      
cpu.ISSUE:FloatSqrt_delay.min_value                 0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:FloatSqrt_delay.max_value                 0                      
cpu.ISSUE:FloatSqrt_delay.end_dist

cpu.ISSUE:MemRead_delay.start_dist                             # cycles from operands ready to issue
cpu.ISSUE:MemRead_delay.samples                958894                      
cpu.ISSUE:MemRead_delay.min_value                   0                      
                               0       844255   8804.47%   8804.47%
                               2        64601    673.70%   9478.17%
                               4        22033    229.78%   9707.94%
                               6        12676    132.19%   9840.14%
                               8        11807    123.13%   9963.27%
                              10         2978     31.06%   9994.33%
                              12           49      0.51%   9994.84%
                              14            0      0.00%   9994.84%
                              16            0      0.00%   9994.84%
                              18            8      0.08%   9994.92%
                              20            0      0.00%   9994.92%
                              22            0      0.00%   9994.92%
                              24            3      0.03%   9994.95%
                              26            1      0.01%   9994.96%
                              28            0      0.00%   9994.96%
                              30            3      0.03%   9994.99%
                              32           13      0.14%   9995.13%
                              34            8      0.08%   9995.21%
                              36            1      0.01%   9995.22%
                              38            3      0.03%   9995.25%
                              40            1      0.01%   9995.27%
                              42            2      0.02%   9995.29%
                              44            2      0.02%   9995.31%
                              46            4      0.04%   9995.35%
                              48           10      0.10%   9995.45%
                              50            2      0.02%   9995.47%
                              52            2      0.02%   9995.49%
                              54            0      0.00%   9995.49%
                              56            1      0.01%   9995.51%
                              58            2      0.02%   9995.53%
                              60            3      0.03%   9995.56%
                              62            0      0.00%   9995.56%
                              64            3      0.03%   9995.59%
                              66            5      0.05%   9995.64%
                              68            1      0.01%   9995.65%
                              70            2      0.02%   9995.67%
                              72           11      0.11%   9995.79%
                              74           11      0.11%   9995.90%
                              76            6      0.06%   9995.96%
                              78            6      0.06%   9996.03%
                              80           16      0.17%   9996.19%
                              82            7      0.07%   9996.27%
                              84           13      0.14%   9996.40%
                              86           12      0.13%   9996.53%
                              88            6      0.06%   9996.59%
                              90           14      0.15%   9996.74%
                              92           14      0.15%   9996.88%
                              94            7      0.07%   9996.95%
                              96            4      0.04%   9997.00%
                              98            2      0.02%   9997.02%
cpu.ISSUE:MemRead_delay.overflows                 286                      
cpu.ISSUE:MemRead_delay.max_value                 135                      
cpu.ISSUE:MemRead_delay.end_dist

cpu.ISSUE:MemWrite_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:MemWrite_delay.samples               354556                      
cpu.ISSUE:MemWrite_delay.min_value                  0                      
                               0       289946   8177.72%   8177.72%
                               2        34135    962.75%   9140.47%
                               4        11810    333.09%   9473.57%
                               6         7317    206.37%   9679.94%
                               8         8642    243.74%   9923.68%
                              10         2166     61.09%   9984.77%
                              12           22      0.62%   9985.39%
                              14            0      0.00%   9985.39%
                              16            0      0.00%   9985.39%
                              18            0      0.00%   9985.39%
                              20            0      0.00%   9985.39%
                              22            0      0.00%   9985.39%
                              24            0      0.00%   9985.39%
                              26            0      0.00%   9985.39%
                              28            0      0.00%   9985.39%
                              30            0      0.00%   9985.39%
                              32            1      0.03%   9985.42%
                              34            3      0.08%   9985.50%
                              36            0      0.00%   9985.50%
                              38            0      0.00%   9985.50%
                              40            0      0.00%   9985.50%
                              42            0      0.00%   9985.50%
                              44            0      0.00%   9985.50%
                              46            1      0.03%   9985.53%
                              48            0      0.00%   9985.53%
                              50            1      0.03%   9985.56%
                              52            0      0.00%   9985.56%
                              54            1      0.03%   9985.59%
                              56            0      0.00%   9985.59%
                              58            1      0.03%   9985.62%
                              60            3      0.08%   9985.70%
                              62            2      0.06%   9985.76%
                              64            6      0.17%   9985.93%
                              66            5      0.14%   9986.07%
                              68           11      0.31%   9986.38%
                              70            3      0.08%   9986.46%
                              72            8      0.23%   9986.69%
                              74            3      0.08%   9986.77%
                              76           17      0.48%   9987.25%
                              78            6      0.17%   9987.42%
                              80            4      0.11%   9987.53%
                              82            4      0.11%   9987.65%
                              84            4      0.11%   9987.76%
                              86            4      0.11%   9987.87%
                              88            1      0.03%   9987.90%
                              90            3      0.08%   9987.98%
                              92            1      0.03%   9988.01%
                              94            4      0.11%   9988.13%
                              96            3      0.08%   9988.21%
                              98            6      0.17%   9988.38%
cpu.ISSUE:MemWrite_delay.overflows                412                      
cpu.ISSUE:MemWrite_delay.max_value                127                      
cpu.ISSUE:MemWrite_delay.end_dist

cpu.ISSUE:IprAccess_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:IprAccess_delay.samples                   0                      
cpu.ISSUE:IprAccess_delay.min_value                 0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:IprAccess_delay.max_value                 0                      
cpu.ISSUE:IprAccess_delay.end_dist

cpu.ISSUE:InstPrefetch_delay.start_dist                        # cycles from operands ready to issue
cpu.ISSUE:InstPrefetch_delay.samples                0                      
cpu.ISSUE:InstPrefetch_delay.min_value              0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:InstPrefetch_delay.max_value              0                      
cpu.ISSUE:InstPrefetch_delay.end_dist

cpu.ISSUE:FU_type_0                           1667390                       # Type of FU issued
cpu.ISSUE:FU_type_0.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu      1216302     72.95%            # Type of FU issued
                         IntMult            0      0.00%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd            0      0.00%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       355950     21.35%            # Type of FU issued
                        MemWrite        95138      5.71%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_0.end_dist
cpu.ISSUE:FU_type_1                            610993                       # Type of FU issued
cpu.ISSUE:FU_type_1.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu       457737     74.92%            # Type of FU issued
                         IntMult          549      0.09%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd           48      0.01%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt           61      0.01%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv           10      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       114591     18.75%            # Type of FU issued
                        MemWrite        37997      6.22%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_1.end_dist
cpu.ISSUE:FU_type                             2278383                       # Type of FU issued
cpu.ISSUE:FU_type.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu      1674039     73.47%            # Type of FU issued
                         IntMult          549      0.02%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd           48      0.00%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt           61      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv           10      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       470541     20.65%            # Type of FU issued
                        MemWrite       133135      5.84%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type.end_dist
cpu.ISSUE:IQ_0:fu_full.start_dist
                          (null)            0      0.00%           
                          IntAlu       465120     87.32%           
                         IntMult           49      0.01%           
                          IntDiv            0      0.00%           
                        FloatAdd            0      0.00%           
                        FloatCmp            0      0.00%           
                        FloatCvt            0      0.00%           
                       FloatMult            0      0.00%           
                        FloatDiv            0      0.00%           
                       FloatSqrt            0      0.00%           
                         MemRead        60648     11.39%           
                        MemWrite         6855      1.29%           
                       IprAccess            0      0.00%           
                    InstPrefetch            0      0.00%           
cpu.ISSUE:IQ_0:fu_full.end_dist
cpu.ISSUE:MSIPC                              0.563655                       # Misspec issue rate
cpu.ISSUE:MSIPC_0                            0.349433                       # Misspec issue rate
cpu.ISSUE:MSIPC_1                            0.214221                       # Misspec issue rate
cpu.ISSUE:addr_loads                             1159                       # number of invalid-address loads
cpu.ISSUE:addr_loads_0                            107                       # number of invalid-address loads
cpu.ISSUE:addr_loads_1                           1052                       # number of invalid-address loads
cpu.ISSUE:addr_swpfs                               17                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_0                              0                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_1                             17                       # number of invalid-address SW prefetches
cpu.ISSUE:branches                             259767                       # Number of branches issued
cpu.ISSUE:branches_0                           190492                       # Number of branches issued
cpu.ISSUE:branches_1                            69275                       # Number of branches issued
cpu.ISSUE:count                               1672364                       # number of insts issued
cpu.ISSUE:count_0                             1214945                       # number of insts issued
cpu.ISSUE:count_1                              457419                       # number of insts issued
cpu.ISSUE:fu_busy_cnt                          532672                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_0                        333451                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_1                        199221                       # FU busy when requested
cpu.ISSUE:fu_busy_rate                       0.318514                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_0                     0.274458                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_1                     0.435533                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_full.start_dist
                          (null)            0      0.00%            # attempts to use FU when none available
                          IntAlu       465120     87.32%            # attempts to use FU when none available
                         IntMult           49      0.01%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead        60648     11.39%            # attempts to use FU when none available
                        MemWrite         6855      1.29%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
cpu.ISSUE:fu_full.end_dist
cpu.ISSUE:issued_per_cycle                     433767                       # Number of insts issued each cycle
cpu.ISSUE:issued_per_cycle.start_dist
                               0        10221      2.36%            # Number of insts issued each cycle
                               1        34401      7.93%            # Number of insts issued each cycle
                               2        38411      8.86%            # Number of insts issued each cycle
                               3        41196      9.50%            # Number of insts issued each cycle
                               4        29028      6.69%            # Number of insts issued each cycle
                               5        31249      7.20%            # Number of insts issued each cycle
                               6        62704     14.46%            # Number of insts issued each cycle
                               7        60172     13.87%            # Number of insts issued each cycle
                               8       126385     29.14%            # Number of insts issued each cycle
cpu.ISSUE:issued_per_cycle.end_dist
cpu.ISSUE:loads                                488353                       # number of load insts issued
cpu.ISSUE:loads_0                              367523                       # number of load insts issued
cpu.ISSUE:loads_1                              120830                       # number of load insts issued
cpu.ISSUE:lsq_inv_rate                              0                       # Early LSQ issues per cycle
cpu.ISSUE:lsq_invert                                0                       # Number of times LSQ instruction issued early
cpu.ISSUE:misspec_cnt                          346718                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_0                        214945                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_1                        131773                       # Number of misspeculated insts issued
cpu.ISSUE:nop                                  128033                       # number of nop insts issued
cpu.ISSUE:nop_0                                 38789                       # number of nop insts issued
cpu.ISSUE:nop_1                                 89244                       # number of nop insts issued
cpu.ISSUE:op_count                            2315676                       # number of insts issued
cpu.ISSUE:op_count_0                          1692300                       # number of insts issued
cpu.ISSUE:op_count_1                           623376                       # number of insts issued
cpu.ISSUE:op_rate                            3.764562                       # Operation issue rate
cpu.ISSUE:op_rate_0                          2.751148                       # Operation issue rate
cpu.ISSUE:op_rate_1                          1.013414                       # Operation issue rate
cpu.ISSUE:rate                               2.718738                       # Inst issue rate
cpu.ISSUE:rate_0                             1.975119                       # Inst issue rate
cpu.ISSUE:rate_1                             0.743620                       # Inst issue rate
cpu.ISSUE:refs                                 672481                       # number of memory reference insts issued
cpu.ISSUE:refs_0                               496000                       # number of memory reference insts issued
cpu.ISSUE:refs_1                               176481                       # number of memory reference insts issued
cpu.ISSUE:stores                               184128                       # Number of stores issued
cpu.ISSUE:stores_0                             128477                       # Number of stores issued
cpu.ISSUE:stores_1                              55651                       # Number of stores issued
cpu.ISSUE:swp                                    2343                       # number of swp insts issued
cpu.ISSUE:swp_0                                  1357                       # number of swp insts issued
cpu.ISSUE:swp_1                                   986                       # number of swp insts issued
cpu.ISSUE:unissued_cause.start_dist
                          (null)            0      0.00%            # Reason ready instruction not issued
                          IntAlu       465120     87.51%            # Reason ready instruction not issued
                         IntMult           49      0.01%            # Reason ready instruction not issued
                          IntDiv            0      0.00%            # Reason ready instruction not issued
                        FloatAdd            0      0.00%            # Reason ready instruction not issued
                        FloatCmp            0      0.00%            # Reason ready instruction not issued
                        FloatCvt            0      0.00%            # Reason ready instruction not issued
                       FloatMult            0      0.00%            # Reason ready instruction not issued
                        FloatDiv            0      0.00%            # Reason ready instruction not issued
                       FloatSqrt            0      0.00%            # Reason ready instruction not issued
                         MemRead        60648     11.41%            # Reason ready instruction not issued
                        MemWrite            0      0.00%            # Reason ready instruction not issued
                       IprAccess            0      0.00%            # Reason ready instruction not issued
                    InstPrefetch            0      0.00%            # Reason ready instruction not issued
                  DCache_Blocked         5714      1.08%            # Reason ready instruction not issued
                       Too_Young            0      0.00%            # Reason ready instruction not issued
cpu.ISSUE:unissued_cause.end_dist
cpu.LSQ:RQ:rdy_inst                            817527                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_0                          566158                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_1                          251369                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_dist_0_mean              0.920395                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_0_stdev             1.670032                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_0_TOT       615125                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_1_mean              0.408647                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_1_stdev             1.507416                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_1_TOT       615125                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_rate                          1.329042                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_0                        0.920395                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_1                        0.408647                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_x_count                         642045                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_0                       476210                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_1                       165835                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_max                               26                       # largest number of insts that become ready
cpu.LSQ:RQ:rdy_x_rate                        1.043763                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_0                      0.774168                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_1                      0.269596                       # number of insts that become ready per cycle
cpu.LSQ:avg_residency                        6.700439                       # Average IQ residency
cpu.LSQ:avg_residency_0                      6.390828                       # Average IQ residency
cpu.LSQ:avg_residency_1                      7.522792                       # Average IQ residency
cpu.LSQ:blocked_loads                         1261716                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_0                       1148517                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_1                        113199                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:cum_num_insts                        11205573                       # Total occupancy
cpu.LSQ:cum_num_insts_0                       7764505                       # Total occupancy
cpu.LSQ:cum_num_insts_1                       3441068                       # Total occupancy
cpu.LSQ:current_count                               8                       # Occupancy this cycle
cpu.LSQ:empty_count                             55177                       # Number of empty cycles
cpu.LSQ:empty_rate                           8.970047                       # Fraction of cycles empty
cpu.LSQ:forw_loads                                 87                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_0                               27                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_1                               60                       # number of loads forwarded via LSQ
cpu.LSQ:full_count                                  0                       # Number of full cycles
cpu.LSQ:full_rate                                   0                       # Fraction of cycles full
cpu.LSQ:occ_dist_0.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_0.samples                     615125                      
cpu.LSQ:occ_dist_0.min_value                        0                      
                               0       157079              2553.61%
                               2        18493              2854.25%
                               4        30185              3344.96%
                               6        27162              3786.53%
                               8        33203              4326.31%
                              10        30536              4822.73%
                              12        36737              5419.96%
                              14        37320              6026.66%
                              16        30096              6515.93%
                              18        32658              7046.84%
                              20        30307              7539.54%
                              22        19699              7859.78%
                              24        41309              8531.34%
                              26        27890              8984.74%
                              28        21087              9327.55%
                              30        16261              9591.90%
                              32        25103             10000.00%
cpu.LSQ:occ_dist_0.max_value                       32                      
cpu.LSQ:occ_dist_0.end_dist

cpu.LSQ:occ_dist_1.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_1.samples                     615125                      
cpu.LSQ:occ_dist_1.min_value                        0                      
                               0       335289              5450.75%
                               2        33358              5993.04%
                               4        26966              6431.42%
                               6        23755              6817.61%
                               8        23392              7197.89%
                              10        24603              7597.85%
                              12        17152              7876.69%
                              14        23186              8253.62%
                              16        40653              8914.51%
                              18         8859              9058.53%
                              20        50495              9879.42%
                              22         2273              9916.37%
                              24         1831              9946.14%
                              26         1204              9965.71%
                              28          521              9974.18%
                              30          346              9979.81%
                              32         1242             10000.00%
cpu.LSQ:occ_dist_1.max_value                       32                      
cpu.LSQ:occ_dist_1.end_dist

cpu.LSQ:occ_rate                            18.216741                       # Average occupancy
cpu.LSQ:occ_rate_0                          12.622646                       # Average occupancy
cpu.LSQ:occ_rate_1                           5.594096                       # Average occupancy
cpu.LSQ:peak_occupancy                             64                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_0                           32                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_1                           32                       # Peak IQ occupancy
cpu.REG:fp:full                                     0                       # number of cycles where there were no FP registers
cpu.REG:fp:occ                                  12786                       # Cumulative count of FP register usage
cpu.REG:fp:occ_0                                    0                       # Cumulative count of FP register usage
cpu.REG:fp:occ_1                                12786                       # Cumulative count of FP register usage
cpu.REG:fp:occ_rate                                 0                       # Average FP register usage
cpu.REG:fp:occ_rate_0                               0                       # Average FP register usage
cpu.REG:fp:occ_rate_1                               0                       # Average FP register usage
cpu.REG:int:full                                    0                       # number of cycles where there were no INT registers
cpu.REG:int:occ                              40088977                       # Cumulative count of INT register usage
cpu.REG:int:occ_0                            26794012                       # Cumulative count of INT register usage
cpu.REG:int:occ_1                            13294965                       # Cumulative count of INT register usage
cpu.REG:int:occ_rate                               65                       # Average INT register usage
cpu.REG:int:occ_rate_0                             44                       # Average INT register usage
cpu.REG:int:occ_rate_1                             22                       # Average INT register usage
cpu.ROB:cap_events                                  0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_0                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_1                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_inst                                    0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_0                                  0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_1                                  0                       # number of instructions held up by ROB cap
cpu.ROB:current_count                              48                       # Current ROB occupancy
cpu.ROB:full_count                              14851                       # number of cycles where ROB was full
cpu.ROB:full_rate                            0.024143                       # ROB full per cycle
cpu.ROB:occ_dist_0.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_0.samples                     615125                      
cpu.ROB:occ_dist_0.min_value                        0                      
                               0       132220              2149.48%
                               2         2301              2186.89%
                               4         3126              2237.71%
                               6         3343              2292.05%
                               8         7378              2412.00%
                              10         2868              2458.62%
                              12         2165              2493.82%
                              14         2931              2541.47%
                              16         7581              2664.71%
                              18         4114              2731.59%
                              20         3897              2794.94%
                              22         6194              2895.64%
                              24         9059              3042.91%
                              26         4097              3109.51%
                              28         5813              3204.02%
                              30         7072              3318.98%
                              32         7780              3445.46%
                              34         4111              3512.29%
                              36         5570              3602.84%
                              38         5437              3691.23%
                              40         7076              3806.27%
                              42         6244              3907.77%
                              44         9771              4066.62%
                              46         9317              4218.09%
                              48        10401              4387.17%
                              50         9327              4538.80%
                              52        10377              4707.50%
                              54         8390              4843.89%
                              56        10924              5021.48%
                              58         9625              5177.96%
                              60         9864              5338.31%
                              62         6431              5442.86%
                              64         6699              5551.77%
                              66         7018              5665.86%
                              68         6466              5770.97%
                              70         6750              5880.71%
                              72         6987              5994.29%
                              74         7616              6118.11%
                              76        10431              6287.68%
                              78         6968              6400.96%
                              80         7790              6527.60%
                              82         7663              6652.18%
                              84        14202              6883.06%
                              86         8097              7014.69%
                              88        14235              7246.10%
                              90        13637              7467.80%
                              92         7332              7586.99%
                              94         8930              7732.17%
                              96        10602              7904.52%
                              98         8130              8036.69%
                             100         7779              8163.15%
                             102         9708              8320.98%
                             104         8435              8458.10%
                             106         6967              8571.36%
                             108         7572              8694.46%
                             110         8401              8831.03%
                             112        19183              9142.89%
                             114         7218              9260.23%
                             116        14915              9502.70%
                             118         2695              9546.51%
                             120         3334              9600.72%
                             122         2319              9638.41%
                             124         1259              9658.88%
                             126         1430              9682.13%
                             128         1086              9699.78%
                             130         1328              9721.37%
                             132          982              9737.34%
                             134          927              9752.41%
                             136          829              9765.88%
                             138          614              9775.87%
                             140          611              9785.80%
                             142          607              9795.67%
                             144          545              9804.53%
                             146          455              9811.92%
                             148          444              9819.14%
                             150          468              9826.75%
                             152          426              9833.68%
                             154          483              9841.53%
                             156          456              9848.94%
                             158          308              9853.95%
                             160          361              9859.82%
                             162          225              9863.47%
                             164          251              9867.56%
                             166          186              9870.58%
                             168          203              9873.88%
                             170          181              9876.82%
                             172          173              9879.63%
                             174          169              9882.38%
                             176          177              9885.26%
                             178          103              9886.93%
                             180          405              9893.52%
                             182          191              9896.62%
                             184          435              9903.69%
                             186          360              9909.55%
                             188          326              9914.85%
                             190          472              9922.52%
                             192          248              9926.55%
                             194          226              9930.23%
                             196         4292             10000.00%
cpu.ROB:occ_dist_0.max_value                      196                      
cpu.ROB:occ_dist_0.end_dist

cpu.ROB:occ_dist_1.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_1.samples                     615125                      
cpu.ROB:occ_dist_1.min_value                        0                      
                               0       255595              4155.17%
                               2        13938              4381.76%
                               4        11983              4576.57%
                               6        13201              4791.17%
                               8        11765              4982.43%
                              10         8845              5126.23%
                              12         8004              5256.35%
                              14         7855              5384.04%
                              16         6855              5495.48%
                              18         5280              5581.32%
                              20         5427              5669.55%
                              22         5777              5763.46%
                              24         5468              5852.36%
                              26         4393              5923.77%
                              28         5360              6010.91%
                              30         5201              6095.46%
                              32         5161              6179.36%
                              34         4866              6258.47%
                              36         5548              6348.66%
                              38         5873              6444.14%
                              40         6060              6542.65%
                              42         6397              6646.65%
                              44         8714              6788.31%
                              46         5702              6881.01%
                              48         6123              6980.55%
                              50         6522              7086.58%
                              52         6720              7195.82%
                              54        10673              7369.33%
                              56         4569              7443.61%
                              58         6648              7551.68%
                              60         6043              7649.92%
                              62         4507              7723.19%
                              64        21179              8067.50%
                              66         3840              8129.92%
                              68        13266              8345.59%
                              70         7557              8468.44%
                              72         3620              8527.29%
                              74        27592              8975.85%
                              76         2895              9022.91%
                              78        20856              9361.97%
                              80         3011              9410.92%
                              82         1868              9441.28%
                              84         1715              9469.16%
                              86         1802              9498.46%
                              88         1480              9522.52%
                              90          916              9537.41%
                              92         1075              9554.89%
                              94         1030              9571.63%
                              96          900              9586.26%
                              98         1048              9603.30%
                             100          869              9617.43%
                             102          736              9629.39%
                             104         1098              9647.24%
                             106          786              9660.02%
                             108          798              9672.99%
                             110          707              9684.49%
                             112         1149              9703.17%
                             114          735              9715.11%
                             116          730              9726.98%
                             118          404              9733.55%
                             120          717              9745.21%
                             122          437              9752.31%
                             124          487              9760.23%
                             126          779              9772.89%
                             128          971              9788.68%
                             130          438              9795.80%
                             132          421              9802.64%
                             134          390              9808.98%
                             136          482              9816.82%
                             138          277              9821.32%
                             140          604              9831.14%
                             142          535              9839.84%
                             144          424              9846.73%
                             146          598              9856.45%
                             148          486              9864.35%
                             150          532              9873.00%
                             152          463              9880.53%
                             154          412              9887.23%
                             156          437              9894.33%
                             158          506              9902.56%
                             160          255              9906.70%
                             162          439              9913.84%
                             164          409              9920.49%
                             166          479              9928.27%
                             168          392              9934.65%
                             170          220              9938.22%
                             172          352              9943.95%
                             174          215              9947.44%
                             176          206              9950.79%
                             178          318              9955.96%
                             180          273              9960.40%
                             182          148              9962.80%
                             184           83              9964.15%
                             186          152              9966.62%
                             188          165              9969.31%
                             190          458              9976.75%
                             192          364              9982.67%
                             194           72              9983.84%
                             196          994             10000.00%
cpu.ROB:occ_dist_1.max_value                      196                      
cpu.ROB:occ_dist_1.end_dist

cpu.ROB:occ_rate                            87.271667                       # ROB occupancy rate
cpu.ROB:occ_rate_0                          57.455164                       # ROB occupancy rate
cpu.ROB:occ_rate_1                          29.816502                       # ROB occupancy rate
cpu.ROB:occupancy                            53682984                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_0                          35342108                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_1                          18340876                       # cpu.ROB occupancy (cumulative)
cpu.SB:RQ:rdy_inst                             199768                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_0                           109589                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_1                            90179                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_dist_0_mean               0.178157                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_0_stdev              0.708605                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_0_TOT        615125                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_1_mean               0.146603                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_1_stdev              1.049058                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_1_TOT        615125                       # standard deviation of ready rate
cpu.SB:RQ:rdy_rate                           0.324760                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_0                         0.178157                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_1                         0.146603                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_x_count                          133135                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_0                         95138                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_1                         37997                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_max                                 8                       # largest number of insts that become ready
cpu.SB:RQ:rdy_x_rate                         0.216436                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_0                       0.154664                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_1                       0.061771                       # number of insts that become ready per cycle
cpu.SB:full_count                                3114                       # store buffer full events (cumulative)
cpu.SB:full_rate                             0.005062                       # store buffer full rate
cpu.SB:occ_rate                              1.350643                       # store buffer occupancy rate
cpu.SB:occ_rate_0                            0.661028                       # store buffer occupancy rate
cpu.SB:occ_rate_1                            0.689614                       # store buffer occupancy rate
cpu.SB:occupancy                               830814                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_0                             406615                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_1                             424199                       # store buffer occupancy (cumulative)
cpu.SB:write_barrier_pending_cycles_0               0                       # number of cycles write barriers were pending
cpu.SB:write_barrier_pending_cycles_1               0                       # number of cycles write barriers were pending
cpu.SB:write_barriers                               0                       # number of write barrier operations
cpu.SB:write_barriers_0                             0                       # number of write barrier operations
cpu.SB:write_barriers_1                             0                       # number of write barrier operations
cpu.WB:consumers                              2147761                       # num instructions consuming a value
cpu.WB:consumers_0                            1622239                       # num instructions consuming a value
cpu.WB:consumers_1                             525522                       # num instructions consuming a value
cpu.WB:count                                  2252996                       # cumulative count of insts written-back
cpu.WB:count_0                                1655788                       # cumulative count of insts written-back
cpu.WB:count_1                                 597208                       # cumulative count of insts written-back
cpu.WB:fanout                                0.860470                       # average fanout of values written-back
cpu.WB:fanout_0                              0.839010                       # average fanout of values written-back
cpu.WB:fanout_1                              0.926715                       # average fanout of values written-back
cpu.WB:penalized                                    0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_0                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_1                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_rate                               0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_0                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_1                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:pred_error.start_dist                                   # error in predicted writeback times
cpu.WB:pred_error.samples                     2252996                      
cpu.WB:pred_error.min_value                       147                      
                             -10            0      0.00%      0.00%
                              -9            0      0.00%      0.00%
                              -8            0      0.00%      0.00%
                              -7            0      0.00%      0.00%
                              -6            0      0.00%      0.00%
                              -5            0      0.00%      0.00%
                              -4            0      0.00%      0.00%
                              -3            0      0.00%      0.00%
                              -2            0      0.00%      0.00%
                              -1            0      0.00%      0.00%
                               0            0      0.00%      0.00%
                               1            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               3            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               5            0      0.00%      0.00%
                               6            0      0.00%      0.00%
                               7            0      0.00%      0.00%
                               8            0      0.00%      0.00%
                               9            0      0.00%      0.00%
                              10            0      0.00%      0.00%
                              11            0      0.00%      0.00%
                              12            0      0.00%      0.00%
                              13            0      0.00%      0.00%
                              14            0      0.00%      0.00%
                              15            0      0.00%      0.00%
                              16            0      0.00%      0.00%
                              17            0      0.00%      0.00%
                              18            0      0.00%      0.00%
                              19            0      0.00%      0.00%
                              20            0      0.00%      0.00%
                              21            0      0.00%      0.00%
                              22            0      0.00%      0.00%
                              23            0      0.00%      0.00%
                              24            0      0.00%      0.00%
                              25            0      0.00%      0.00%
                              26            0      0.00%      0.00%
                              27            0      0.00%      0.00%
                              28            0      0.00%      0.00%
                              29            0      0.00%      0.00%
                              30            0      0.00%      0.00%
                              31            0      0.00%      0.00%
                              32            0      0.00%      0.00%
                              33            0      0.00%      0.00%
                              34            0      0.00%      0.00%
                              35            0      0.00%      0.00%
                              36            0      0.00%      0.00%
                              37            0      0.00%      0.00%
                              38            0      0.00%      0.00%
                              39            0      0.00%      0.00%
                              40            0      0.00%      0.00%
                              41            0      0.00%      0.00%
                              42            0      0.00%      0.00%
                              43            0      0.00%      0.00%
                              44            0      0.00%      0.00%
                              45            0      0.00%      0.00%
                              46            0      0.00%      0.00%
                              47            0      0.00%      0.00%
                              48            0      0.00%      0.00%
                              49            0      0.00%      0.00%
                              50            0      0.00%      0.00%
                              51            0      0.00%      0.00%
                              52            0      0.00%      0.00%
                              53            0      0.00%      0.00%
                              54            0      0.00%      0.00%
                              55            0      0.00%      0.00%
                              56            0      0.00%      0.00%
                              57            0      0.00%      0.00%
                              58            0      0.00%      0.00%
                              59            0      0.00%      0.00%
                              60            0      0.00%      0.00%
                              61            0      0.00%      0.00%
                              62            0      0.00%      0.00%
                              63            0      0.00%      0.00%
                              64            0      0.00%      0.00%
                              65            0      0.00%      0.00%
                              66            0      0.00%      0.00%
                              67            0      0.00%      0.00%
                              68            0      0.00%      0.00%
                              69            0      0.00%      0.00%
                              70            0      0.00%      0.00%
                              71            0      0.00%      0.00%
                              72            0      0.00%      0.00%
                              73            0      0.00%      0.00%
                              74            0      0.00%      0.00%
                              75            0      0.00%      0.00%
                              76            0      0.00%      0.00%
                              77            0      0.00%      0.00%
                              78            0      0.00%      0.00%
                              79            0      0.00%      0.00%
                              80            0      0.00%      0.00%
                              81            0      0.00%      0.00%
                              82            0      0.00%      0.00%
                              83            0      0.00%      0.00%
                              84            0      0.00%      0.00%
                              85            0      0.00%      0.00%
                              86            0      0.00%      0.00%
                              87            0      0.00%      0.00%
                              88            0      0.00%      0.00%
                              89            0      0.00%      0.00%
                              90            0      0.00%      0.00%
                              91            0      0.00%      0.00%
                              92            0      0.00%      0.00%
                              93            0      0.00%      0.00%
                              94            0      0.00%      0.00%
                              95            0      0.00%      0.00%
                              96            0      0.00%      0.00%
                              97            0      0.00%      0.00%
                              98            0      0.00%      0.00%
                              99            0      0.00%      0.00%
                             100            0      0.00%      0.00%
cpu.WB:pred_error.overflows                   2252996                      
cpu.WB:pred_error.max_value                    615124                      
cpu.WB:pred_error.end_dist

cpu.WB:producers                              1848084                       # num instructions producing a value
cpu.WB:producers_0                            1361075                       # num instructions producing a value
cpu.WB:producers_1                             487009                       # num instructions producing a value
cpu.WB:rate                                  3.662664                       # insts written-back per cycle
cpu.WB:rate_0                                2.691791                       # insts written-back per cycle
cpu.WB:rate_1                                0.970873                       # insts written-back per cycle
cpu.branch_pred.btb_accuracy                 0.994690                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_0                      1                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_1               0.977102                       # fraction of BTB targets correct
cpu.branch_pred.btb_correct                    122512                       # num correct BTB predictions
cpu.branch_pred.btb_correct_0                   94605                       # num correct BTB predictions
cpu.branch_pred.btb_correct_1                   27907                       # num correct BTB predictions
cpu.branch_pred.btb_hit_rate                 0.910278                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_0               0.969551                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_1               0.785583                       # BTB hit ratio
cpu.branch_pred.btb_hits                       281924                       # Number of BTB hits
cpu.branch_pred.btb_hits_0                     203533                       # Number of BTB hits
cpu.branch_pred.btb_hits_1                      78391                       # Number of BTB hits
cpu.branch_pred.btb_lookups                    309712                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_0                  209925                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_1                   99787                       # Number of BTB lookups
cpu.branch_pred.cond_correct                   145096                       # num correct dir predictions
cpu.branch_pred.cond_correct_0                 109015                       # num correct dir predictions
cpu.branch_pred.cond_correct_1                  36081                       # num correct dir predictions
cpu.branch_pred.cond_predicted                 155116                       # num committed conditional branches
cpu.branch_pred.cond_predicted_0               114188                       # num committed conditional branches
cpu.branch_pred.cond_predicted_1                40928                       # num committed conditional branches
cpu.branch_pred.dir_accuracy                 0.935403                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_0               0.954698                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_1               0.881573                       # fraction of predictions correct
cpu.branch_pred.lookup_rate                  0.795170                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_0                0.553161                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_1                0.242009                       # Rate of bpred lookups
cpu.branch_pred.lookups                        489129                       # num BP lookups
cpu.branch_pred.lookups_0                      340263                       # num BP lookups
cpu.branch_pred.lookups_1                      148866                       # num BP lookups
cpu.branch_pred.ras_accuracy                 0.930365                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_0               0.959344                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_1               0.864284                       # fraction of RAS targets correct
cpu.branch_pred.ras_correct                     10929                       # num correct RAS predictions
cpu.branch_pred.ras_correct_0                    7834                       # num correct RAS predictions
cpu.branch_pred.ras_correct_1                    3095                       # num correct RAS predictions
cpu.branch_pred.used_btb                       123166                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_0                      94605                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_1                      28561                       # num committed branches using target from BTB
cpu.branch_pred.used_ras                        11747                       # num returns predicted using RAS
cpu.branch_pred.used_ras_0                       8166                       # num returns predicted using RAS
cpu.branch_pred.used_ras_1                       3581                       # num returns predicted using RAS
cpu.dcache.advance_pool_dist.start_dist                        # Dist. of Repl. across pools
cpu.dcache.advance_pool_dist.samples            29112                      
cpu.dcache.advance_pool_dist.min_value              0                      
                               0         4680   1607.58%           
                               1         2138    734.41%           
                               2         1402    481.59%           
                               3         1062    364.80%           
                               4          935    321.17%           
                               5          902    309.84%           
                               6          831    285.45%           
                               7          900    309.15%           
                               8          977    335.60%           
                               9          778    267.24%           
                              10          721    247.66%           
                              11          766    263.12%           
                              12          763    262.09%           
                              13          919    315.68%           
                              14         1472    505.63%           
                              15         8188   2812.59%           
                              16         1678    576.39%           
cpu.dcache.advance_pool_dist.max_value             16                      
cpu.dcache.advance_pool_dist.end_dist

cpu.dcache.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
cpu.dcache.avg_blocked_cycles_no_targets   102.152542                       # average number of cycles each access was blocked
cpu.dcache.avg_refs                        132.958081                       # Average number of references to valid blocks.
cpu.dcache.blocked_no_mshrs                         0                       # number of cycles access was blocked
cpu.dcache.blocked_no_targets                      59                       # number of cycles access was blocked
cpu.dcache.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
cpu.dcache.blocked_cycles_no_targets             6027                       # number of cycles access was blocked
cpu.dcache.cache_copies                             0                       # number of cache copies performed
cpu.dcache.demand_accesses                     600918                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_0                   449614                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_1                   151304                       # number of demand (read+write) accesses
cpu.dcache.demand_avg_miss_latency          97.188193                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_0       110.562678                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_1        93.216582                       # average overall miss latency
cpu.dcache.demand_avg_mshr_miss_latency     91.055075                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_0   116.145540                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_1    85.019763                       # average overall mshr miss latency
cpu.dcache.demand_hits                         591720                       # number of demand (read+write) hits
cpu.dcache.demand_hits_0                       447508                       # number of demand (read+write) hits
cpu.dcache.demand_hits_1                       144212                       # number of demand (read+write) hits
cpu.dcache.demand_miss_latency                 893937                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_0               232845                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_1               661092                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_rate                  0.015307                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_0                0.004684                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_1                0.046873                       # miss rate for demand accesses
cpu.dcache.demand_misses                         9198                       # number of demand (read+write) misses
cpu.dcache.demand_misses_0                       2106                       # number of demand (read+write) misses
cpu.dcache.demand_misses_1                       7092                       # number of demand (read+write) misses
cpu.dcache.demand_mshr_hits                      4804                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_0                    1254                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_1                    3550                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_miss_latency            400096                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_0           98956                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_1          301140                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_rate             0.007312                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_0           0.001895                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_1           0.023410                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_misses                    4394                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_0                   852                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_1                  3542                       # number of demand (read+write) MSHR misses
cpu.dcache.demote_pool_dist.start_dist                         # Dist. of Repl. across pools
cpu.dcache.demote_pool_dist.samples            276453                      
cpu.dcache.demote_pool_dist.min_value               0                      
                               0       223768   8094.25%           
                               1         8786    317.81%           
                               2         6326    228.83%           
                               3         5635    203.83%           
                               4         5321    192.47%           
                               5         5207    188.35%           
                               6         5190    187.74%           
                               7         5141    185.96%           
                               8         2476     89.56%           
                               9          889     32.16%           
                              10          693     25.07%           
                              11          639     23.11%           
                              12          686     24.81%           
                              13          692     25.03%           
                              14          848     30.67%           
                              15         1403     50.75%           
                              16         2753     99.58%           
cpu.dcache.demote_pool_dist.max_value              16                      
cpu.dcache.demote_pool_dist.end_dist

cpu.dcache.fast_writes                             31                       # number of fast writes performed
cpu.dcache.hash_hit                            593126                       # Total of hites in hash table
cpu.dcache.hash_miss                             9287                       # Total of misses in hash table
cpu.dcache.hit_depth_total                     593126                       # Total of hit depths
cpu.dcache.hit_hash_depth_dist.start_dist                      # Dist. of Hash lookup depths
cpu.dcache.hit_hash_depth_dist.samples         593126                      
cpu.dcache.hit_hash_depth_dist.min_value            1                      
                               0            0      0.00%           
                               1       593126  10000.00%           
                               2            0      0.00%           
                               3            0      0.00%           
                               4            0      0.00%           
                               5            0      0.00%           
                               6            0      0.00%           
                               7            0      0.00%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
                              17            0      0.00%           
                              18            0      0.00%           
                              19            0      0.00%           
                              20            0      0.00%           
cpu.dcache.hit_hash_depth_dist.max_value            1                      
cpu.dcache.hit_hash_depth_dist.end_dist

cpu.dcache.miss_depth_total                     12370                       # Total of miss depths
cpu.dcache.miss_hash_depth_dist.start_dist                     # Dist. of Hash lookup depths
cpu.dcache.miss_hash_depth_dist.samples          9287                      
cpu.dcache.miss_hash_depth_dist.min_value            1                      
                               0            0      0.00%           
                               1         7158   7707.55%           
                               2         1375   1480.56%           
                               3          589    634.22%           
                               4          137    147.52%           
                               5           21     22.61%           
                               6            7      7.54%           
                               7            0      0.00%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
                              17            0      0.00%           
                              18            0      0.00%           
                              19            0      0.00%           
                              20            0      0.00%           
cpu.dcache.miss_hash_depth_dist.max_value            6                      
cpu.dcache.miss_hash_depth_dist.end_dist

cpu.dcache.mshr_cap_events                          0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_0                        0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_1                        0                       # number of times MSHR cap was activated
cpu.dcache.no_allocate_misses                       0                       # Number of misses that were no-allocate
cpu.dcache.overall_accesses                    602413                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_0                  450954                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_1                  151459                       # number of overall (read+write) accesses
cpu.dcache.overall_avg_miss_latency         97.211863                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_0      110.441232                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_1       93.305626                       # average overall miss latency
cpu.dcache.overall_avg_mshr_miss_latency    91.218962                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_0   115.929825                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_1    85.309091                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_hits                        593157                       # number of overall hits
cpu.dcache.overall_hits_0                      448844                       # number of overall hits
cpu.dcache.overall_hits_1                      144313                       # number of overall hits
cpu.dcache.overall_miss_latency                899793                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_0              233031                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_1              666762                       # number of overall miss cycles
cpu.dcache.overall_miss_rate                 0.015365                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_0               0.004679                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_1               0.047181                       # miss rate for overall accesses
cpu.dcache.overall_misses                        9256                       # number of overall misses
cpu.dcache.overall_misses_0                      2110                       # number of overall misses
cpu.dcache.overall_misses_1                      7146                       # number of overall misses
cpu.dcache.overall_mshr_hits                     4826                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_0                   1255                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_1                   3571                       # number of overall MSHR hits
cpu.dcache.overall_mshr_miss_latency           404100                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_0          99120                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_1         304980                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_rate            0.007354                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_0          0.001896                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_1          0.023604                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_misses                   4430                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_0                  855                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_1                 3575                       # number of overall MSHR misses
cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.dcache.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
cpu.dcache.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.dcache.read_accesses                       467783                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_0                     354476                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_1                     113307                       # number of read accesses(hits+misses)
cpu.dcache.read_avg_miss_latency            93.210354                       # average read miss latency
cpu.dcache.read_avg_miss_latency_0         117.985538                       # average read miss latency
cpu.dcache.read_avg_miss_latency_1          84.220019                       # average read miss latency
cpu.dcache.read_avg_mshr_miss_latency       89.667077                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_0    121.984694                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_1     81.942378                       # average read mshr miss latency
cpu.dcache.read_hits                           460771                       # number of read hits
cpu.dcache.read_hits_0                         352609                       # number of read hits
cpu.dcache.read_hits_1                         108162                       # number of read hits
cpu.dcache.read_miss_latency                   653591                       # number of read miss cycles
cpu.dcache.read_miss_latency_0                 220279                       # number of read miss cycles
cpu.dcache.read_miss_latency_1                 433312                       # number of read miss cycles
cpu.dcache.read_miss_rate                    0.014990                       # miss rate for read accesses
cpu.dcache.read_miss_rate_0                  0.005267                       # miss rate for read accesses
cpu.dcache.read_miss_rate_1                  0.045408                       # miss rate for read accesses
cpu.dcache.read_misses                           7012                       # number of read misses
cpu.dcache.read_misses_0                         1867                       # number of read misses
cpu.dcache.read_misses_1                         5145                       # number of read misses
cpu.dcache.read_mshr_hits                        2948                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_0                      1083                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_1                      1865                       # number of read MSHR hits
cpu.dcache.read_mshr_miss_latency              364407                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_0             95636                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_1            268771                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_rate               0.008688                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_0             0.002212                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_1             0.028948                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_misses                      4064                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_0                     784                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_1                    3280                       # number of read MSHR misses
cpu.dcache.repl_pool_dist.start_dist                           # Dist. of Repl. across pools
cpu.dcache.repl_pool_dist.samples                3437                      
cpu.dcache.repl_pool_dist.min_value                 0                      
                               0         3437  10000.00%           
                               1            0      0.00%           
                               2            0      0.00%           
                               3            0      0.00%           
                               4            0      0.00%           
                               5            0      0.00%           
                               6            0      0.00%           
                               7            0      0.00%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
cpu.dcache.repl_pool_dist.max_value                 0                      
cpu.dcache.repl_pool_dist.end_dist

cpu.dcache.replacements                          3437                       # number of replacements
cpu.dcache.replacements_0                         529                       # number of replacements
cpu.dcache.replacements_1                        2908                       # number of replacements
cpu.dcache.sampled_refs                          4461                       # Sample count of references to valid blocks.
cpu.dcache.set_access_dist.start_dist                          # Dist. of Accesses across sets
cpu.dcache.set_access_dist.samples             602413                      
cpu.dcache.set_access_dist.min_value                0                      
                               0          162      2.69%           
                               1          152      2.52%           
                               2          165      2.74%           
                               3          126      2.09%           
                               4          149      2.47%           
                               5          177      2.94%           
                               6          194      3.22%           
                               7         9208    152.85%           
                               8         7015    116.45%           
                               9          159      2.64%           
                              10          182      3.02%           
                              11          209      3.47%           
                              12          146      2.42%           
                              13          198      3.29%           
                              14          109      1.81%           
                              15          203      3.37%           
                              16          112      1.86%           
                              17          134      2.22%           
                              18          160      2.66%           
                              19          236      3.92%           
                              20          180      2.99%           
                              21          144      2.39%           
                              22          179      2.97%           
                              23          142      2.36%           
                              24          123      2.04%           
                              25          137      2.27%           
                              26           90      1.49%           
                              27         2615     43.41%           
                              28          266      4.42%           
                              29          225      3.73%           
                              30          203      3.37%           
                              31          136      2.26%           
                              32           69      1.15%           
                              33          152      2.52%           
                              34          956     15.87%           
                              35           88      1.46%           
                              36           75      1.24%           
                              37          119      1.98%           
                              38          117      1.94%           
                              39           65      1.08%           
                              40           97      1.61%           
                              41          804     13.35%           
                              42           77      1.28%           
                              43          113      1.88%           
                              44          201      3.34%           
                              45          227      3.77%           
                              46          263      4.37%           
                              47          153      2.54%           
                              48          104      1.73%           
                              49          209      3.47%           
                              50         7616    126.42%           
                              51         1336     22.18%           
                              52           65      1.08%           
                              53            2      0.03%           
                              54           87      1.44%           
                              55          118      1.96%           
                              56          698     11.59%           
                              57          117      1.94%           
                              58          325      5.39%           
                              59         1069     17.75%           
                              60          178      2.95%           
                              61          139      2.31%           
                              62          768     12.75%           
                              63          138      2.29%           
                              64          129      2.14%           
                              65          100      1.66%           
                              66           62      1.03%           
                              67           84      1.39%           
                              68         5342     88.68%           
                              69         6572    109.09%           
                              70           34      0.56%           
                              71          105      1.74%           
                              72         4982     82.70%           
                              73        41525    689.31%           
                              74        18130    300.96%           
                              75        16648    276.36%           
                              76        11433    189.79%           
                              77           83      1.38%           
                              78        48606    806.86%           
                              79        37743    626.53%           
                              80           68      1.13%           
                              81          495      8.22%           
                              82          677     11.24%           
                              83          112      1.86%           
                              84         3522     58.46%           
                              85         2916     48.41%           
                              86         1160     19.26%           
                              87          895     14.86%           
                              88          166      2.76%           
                              89          108      1.79%           
                              90        16250    269.75%           
                              91         3918     65.04%           
                              92         2385     39.59%           
                              93           73      1.21%           
                              94          113      1.88%           
                              95          112      1.86%           
                              96        10146    168.42%           
                              97         2037     33.81%           
                              98         2118     35.16%           
                              99         5641     93.64%           
                             100         6349    105.39%           
                             101         8897    147.69%           
                             102         3679     61.07%           
                             103         4963     82.39%           
                             104          187      3.10%           
                             105        10238    169.95%           
                             106         3716     61.69%           
                             107         2392     39.71%           
                             108          112      1.86%           
                             109          140      2.32%           
                             110         5612     93.16%           
                             111         1074     17.83%           
                             112          113      1.88%           
                             113          100      1.66%           
                             114          191      3.17%           
                             115          312      5.18%           
                             116          334      5.54%           
                             117          683     11.34%           
                             118          131      2.17%           
                             119          124      2.06%           
                             120         2943     48.85%           
                             121          235      3.90%           
                             122          907     15.06%           
                             123         3098     51.43%           
                             124          941     15.62%           
                             125         1263     20.97%           
                             126          649     10.77%           
                             127          871     14.46%           
                             128          715     11.87%           
                             129          364      6.04%           
                             130          407      6.76%           
                             131          485      8.05%           
                             132          208      3.45%           
                             133          206      3.42%           
                             134          238      3.95%           
                             135          220      3.65%           
                             136          224      3.72%           
                             137          171      2.84%           
                             138          564      9.36%           
                             139          600      9.96%           
                             140           50      0.83%           
                             141          102      1.69%           
                             142          507      8.42%           
                             143           52      0.86%           
                             144          201      3.34%           
                             145          522      8.67%           
                             146          131      2.17%           
                             147          219      3.64%           
                             148           54      0.90%           
                             149          177      2.94%           
                             150          313      5.20%           
                             151          388      6.44%           
                             152          187      3.10%           
                             153          173      2.87%           
                             154           87      1.44%           
                             155           43      0.71%           
                             156          338      5.61%           
                             157          704     11.69%           
                             158         1283     21.30%           
                             159          998     16.57%           
                             160         1099     18.24%           
                             161         1505     24.98%           
                             162         2005     33.28%           
                             163         1574     26.13%           
                             164         2197     36.47%           
                             165         1971     32.72%           
                             166         3220     53.45%           
                             167         2467     40.95%           
                             168         4092     67.93%           
                             169         3783     62.80%           
                             170         5878     97.57%           
                             171         5028     83.46%           
                             172          161      2.67%           
                             173           64      1.06%           
                             174          130      2.16%           
                             175           88      1.46%           
                             176           42      0.70%           
                             177          190      3.15%           
                             178           39      0.65%           
                             179           44      0.73%           
                             180           40      0.66%           
                             181          190      3.15%           
                             182          345      5.73%           
                             183          171      2.84%           
                             184          101      1.68%           
                             185           61      1.01%           
                             186           81      1.34%           
                             187           81      1.34%           
                             188           74      1.23%           
                             189          104      1.73%           
                             190          114      1.89%           
                             191          391      6.49%           
                             192           70      1.16%           
                             193           82      1.36%           
                             194           70      1.16%           
                             195          101      1.68%           
                             196          124      2.06%           
                             197          117      1.94%           
                             198           84      1.39%           
                             199           60      1.00%           
                             200          105      1.74%           
                             201           89      1.48%           
                             202          150      2.49%           
                             203           82      1.36%           
                             204          126      2.09%           
                             205           81      1.34%           
                             206           91      1.51%           
                             207          117      1.94%           
                             208          218      3.62%           
                             209          483      8.02%           
                             210          128      2.12%           
                             211          218      3.62%           
                             212          277      4.60%           
                             213           79      1.31%           
                             214           89      1.48%           
                             215          130      2.16%           
                             216          100      1.66%           
                             217           97      1.61%           
                             218          432      7.17%           
                             219          210      3.49%           
                             220          198      3.29%           
                             221          636     10.56%           
                             222           55      0.91%           
                             223          152      2.52%           
                             224          158      2.62%           
                             225           86      1.43%           
                             226           79      1.31%           
                             227           81      1.34%           
                             228          229      3.80%           
                             229          184      3.05%           
                             230          262      4.35%           
                             231          188      3.12%           
                             232          101      1.68%           
                             233          160      2.66%           
                             234           90      1.49%           
                             235          179      2.97%           
                             236           59      0.98%           
                             237           90      1.49%           
                             238           59      0.98%           
                             239           83      1.38%           
                             240           49      0.81%           
                             241          123      2.04%           
                             242          128      2.12%           
                             243           81      1.34%           
                             244          140      2.32%           
                             245          450      7.47%           
                             246         3201     53.14%           
                             247           59      0.98%           
                             248          453      7.52%           
                             249          327      5.43%           
                             250         1021     16.95%           
                             251          109      1.81%           
                             252           90      1.49%           
                             253          156      2.59%           
                             254          146      2.42%           
                             255          133      2.21%           
                             256         3634     60.32%           
                             257          236      3.92%           
                             258          106      1.76%           
                             259           93      1.54%           
                             260           75      1.24%           
                             261           97      1.61%           
                             262          283      4.70%           
                             263         4783     79.40%           
                             264          148      2.46%           
                             265         2848     47.28%           
                             266          218      3.62%           
                             267          323      5.36%           
                             268         1670     27.72%           
                             269         2786     46.25%           
                             270         3706     61.52%           
                             271         2505     41.58%           
                             272        35450    588.47%           
                             273         2798     46.45%           
                             274         3351     55.63%           
                             275         1360     22.58%           
                             276          269      4.47%           
                             277          202      3.35%           
                             278         4398     73.01%           
                             279         1253     20.80%           
                             280           96      1.59%           
                             281          837     13.89%           
                             282          732     12.15%           
                             283           86      1.43%           
                             284          159      2.64%           
                             285          260      4.32%           
                             286          203      3.37%           
                             287           86      1.43%           
                             288          637     10.57%           
                             289          141      2.34%           
                             290          593      9.84%           
                             291          744     12.35%           
                             292          824     13.68%           
                             293          185      3.07%           
                             294          204      3.39%           
                             295          255      4.23%           
                             296         1096     18.19%           
                             297          551      9.15%           
                             298          640     10.62%           
                             299         1204     19.99%           
                             300          640     10.62%           
                             301         2018     33.50%           
                             302          232      3.85%           
                             303          609     10.11%           
                             304          682     11.32%           
                             305          335      5.56%           
                             306          777     12.90%           
                             307          856     14.21%           
                             308         1632     27.09%           
                             309          974     16.17%           
                             310          313      5.20%           
                             311          735     12.20%           
                             312          734     12.18%           
                             313          233      3.87%           
                             314          812     13.48%           
                             315          513      8.52%           
                             316          614     10.19%           
                             317          696     11.55%           
                             318          817     13.56%           
                             319          384      6.37%           
                             320          211      3.50%           
                             321          553      9.18%           
                             322          245      4.07%           
                             323          570      9.46%           
                             324          226      3.75%           
                             325          286      4.75%           
                             326          547      9.08%           
                             327          312      5.18%           
                             328          856     14.21%           
                             329          383      6.36%           
                             330         1207     20.04%           
                             331          694     11.52%           
                             332          948     15.74%           
                             333          492      8.17%           
                             334          576      9.56%           
                             335          903     14.99%           
                             336          330      5.48%           
                             337          197      3.27%           
                             338          484      8.03%           
                             339          674     11.19%           
                             340          634     10.52%           
                             341          850     14.11%           
                             342          234      3.88%           
                             343          848     14.08%           
                             344          995     16.52%           
                             345          194      3.22%           
                             346          313      5.20%           
                             347          565      9.38%           
                             348          358      5.94%           
                             349          791     13.13%           
                             350          543      9.01%           
                             351          346      5.74%           
                             352          253      4.20%           
                             353        17021    282.55%           
                             354        16175    268.50%           
                             355         2969     49.29%           
                             356          746     12.38%           
                             357         1188     19.72%           
                             358          329      5.46%           
                             359          821     13.63%           
                             360          362      6.01%           
                             361          518      8.60%           
                             362          657     10.91%           
                             363         1178     19.55%           
                             364          230      3.82%           
                             365          165      2.74%           
                             366          779     12.93%           
                             367          551      9.15%           
                             368          462      7.67%           
                             369          950     15.77%           
                             370          102      1.69%           
                             371          650     10.79%           
                             372          342      5.68%           
                             373          440      7.30%           
                             374         5049     83.81%           
                             375         3171     52.64%           
                             376          232      3.85%           
                             377          710     11.79%           
                             378          675     11.20%           
                             379          400      6.64%           
                             380          907     15.06%           
                             381          605     10.04%           
                             382          705     11.70%           
                             383          541      8.98%           
                             384           64      1.06%           
                             385           61      1.01%           
                             386           59      0.98%           
                             387           79      1.31%           
                             388           53      0.88%           
                             389           74      1.23%           
                             390         2688     44.62%           
                             391         1711     28.40%           
                             392          252      4.18%           
                             393          289      4.80%           
                             394          278      4.61%           
                             395          469      7.79%           
                             396           65      1.08%           
                             397           52      0.86%           
                             398          121      2.01%           
                             399          125      2.07%           
                             400           63      1.05%           
                             401          106      1.76%           
                             402           83      1.38%           
                             403          418      6.94%           
                             404          121      2.01%           
                             405           71      1.18%           
                             406           79      1.31%           
                             407          114      1.89%           
                             408           55      0.91%           
                             409           81      1.34%           
                             410           62      1.03%           
                             411           97      1.61%           
                             412           57      0.95%           
                             413          106      1.76%           
                             414          100      1.66%           
                             415           62      1.03%           
                             416           54      0.90%           
                             417           55      0.91%           
                             418           37      0.61%           
                             419           36      0.60%           
                             420           46      0.76%           
                             421           42      0.70%           
                             422           51      0.85%           
                             423           75      1.24%           
                             424         2956     49.07%           
                             425           52      0.86%           
                             426           66      1.10%           
                             427           55      0.91%           
                             428           46      0.76%           
                             429           41      0.68%           
                             430           78      1.29%           
                             431           62      1.03%           
                             432           47      0.78%           
                             433           62      1.03%           
                             434          114      1.89%           
                             435           62      1.03%           
                             436          130      2.16%           
                             437           70      1.16%           
                             438           48      0.80%           
                             439          115      1.91%           
                             440           48      0.80%           
                             441          153      2.54%           
                             442          102      1.69%           
                             443           51      0.85%           
                             444           47      0.78%           
                             445           69      1.15%           
                             446           78      1.29%           
                             447           82      1.36%           
                             448           90      1.49%           
                             449          124      2.06%           
                             450           61      1.01%           
                             451           62      1.03%           
                             452           68      1.13%           
                             453           87      1.44%           
                             454           93      1.54%           
                             455           66      1.10%           
                             456          158      2.62%           
                             457          187      3.10%           
                             458           95      1.58%           
                             459          106      1.76%           
                             460          102      1.69%           
                             461           98      1.63%           
                             462          107      1.78%           
                             463          104      1.73%           
                             464           68      1.13%           
                             465          115      1.91%           
                             466           50      0.83%           
                             467           61      1.01%           
                             468           32      0.53%           
                             469           41      0.68%           
                             470           28      0.46%           
                             471           46      0.76%           
                             472           47      0.78%           
                             473          182      3.02%           
                             474           42      0.70%           
                             475           33      0.55%           
                             476           58      0.96%           
                             477           65      1.08%           
                             478           53      0.88%           
                             479           57      0.95%           
                             480           35      0.58%           
                             481          559      9.28%           
                             482           72      1.20%           
                             483           73      1.21%           
                             484           57      0.95%           
                             485           80      1.33%           
                             486           53      0.88%           
                             487           69      1.15%           
                             488           47      0.78%           
                             489          155      2.57%           
                             490           54      0.90%           
                             491           80      1.33%           
                             492           36      0.60%           
                             493           56      0.93%           
                             494           99      1.64%           
                             495           63      1.05%           
                             496           52      0.86%           
                             497           99      1.64%           
                             498           61      1.01%           
                             499           65      1.08%           
                             500          166      2.76%           
                             501          252      4.18%           
                             502           76      1.26%           
                             503           32      0.53%           
                             504          245      4.07%           
                             505          191      3.17%           
                             506           71      1.18%           
                             507           85      1.41%           
                             508         2339     38.83%           
                             509          154      2.56%           
                             510          145      2.41%           
                             511           91      1.51%           
                             512            0      0.00%           
cpu.dcache.set_access_dist.max_value              511                      
cpu.dcache.set_access_dist.end_dist

cpu.dcache.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_0                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_1                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.swpf_accesses                         1495                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_0                       1340                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_1                        155                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_avg_miss_latency           100.965517                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_0          46.500000                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_1                105                       # average swpf miss latency
cpu.dcache.swpf_avg_mshr_miss_latency      111.222222                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_0     54.666667                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_1    116.363636                       # average swpf mshr miss latency
cpu.dcache.swpf_hits                             1437                       # number of swpf hits
cpu.dcache.swpf_hits_0                           1336                       # number of swpf hits
cpu.dcache.swpf_hits_1                            101                       # number of swpf hits
cpu.dcache.swpf_miss_latency                     5856                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_0                    186                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_1                   5670                       # number of swpf miss cycles
cpu.dcache.swpf_miss_rate                    0.038796                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_0                  0.002985                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_1                  0.348387                       # miss rate for swpf accesses
cpu.dcache.swpf_misses                             58                       # number of swpf misses
cpu.dcache.swpf_misses_0                            4                       # number of swpf misses
cpu.dcache.swpf_misses_1                           54                       # number of swpf misses
cpu.dcache.swpf_mshr_hits                          22                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_0                         1                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_1                        21                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_miss_latency                4004                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_0               164                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_1              3840                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_rate               0.024080                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_0             0.002239                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_1             0.212903                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_misses                        36                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_0                       3                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_1                      33                       # number of swpf MSHR misses
cpu.dcache.tagsinuse                       918.058198                       # Cycle average of tags in use
cpu.dcache.total_refs                          593126                       # Total number of references to valid blocks.
cpu.dcache.warmup_cycle                        127582                       # Cycle when the warmup percentage was hit.
cpu.dcache.write_accesses                      133135                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_0                     95138                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_1                     37997                       # number of write accesses(hits+misses)
cpu.dcache.write_avg_miss_latency          109.947850                       # average write miss latency
cpu.dcache.write_avg_miss_latency_0         52.577406                       # average write miss latency
cpu.dcache.write_avg_miss_latency_1        116.990241                       # average write miss latency
cpu.dcache.write_avg_mshr_miss_latency     108.148485                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_0    48.823529                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_1   123.545802                       # average write mshr miss latency
cpu.dcache.write_hits                          130949                       # number of write hits
cpu.dcache.write_hits_0                         94899                       # number of write hits
cpu.dcache.write_hits_1                         36050                       # number of write hits
cpu.dcache.write_miss_latency                  240346                       # number of write miss cycles
cpu.dcache.write_miss_latency_0                 12566                       # number of write miss cycles
cpu.dcache.write_miss_latency_1                227780                       # number of write miss cycles
cpu.dcache.write_miss_rate                   0.016419                       # miss rate for write accesses
cpu.dcache.write_miss_rate_0                 0.002512                       # miss rate for write accesses
cpu.dcache.write_miss_rate_1                 0.051241                       # miss rate for write accesses
cpu.dcache.write_misses                          2186                       # number of write misses
cpu.dcache.write_misses_0                         239                       # number of write misses
cpu.dcache.write_misses_1                        1947                       # number of write misses
cpu.dcache.write_mshr_hits                       1856                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_0                      171                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_1                     1685                       # number of write MSHR hits
cpu.dcache.write_mshr_miss_latency              35689                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_0             3320                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_1            32369                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_rate              0.002479                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_0            0.000715                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_1            0.006895                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_misses                      330                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_0                     68                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_1                    262                       # number of write MSHR misses
cpu.dcache.writebacks                             311                       # number of writebacks
cpu.dcache.writebacks_0                            55                       # number of writebacks
cpu.dcache.writebacks_1                           256                       # number of writebacks
cpu.floss.fetch_0.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_0.end_dist
cpu.floss.fetch_1.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_1.end_dist
cpu.floss.icache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_0.end_dist
cpu.floss.icache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_1.end_dist
cpu.floss.iq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_0.end_dist
cpu.floss.iq_full_1.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_1.end_dist
cpu.floss.iq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_0.end_dist
cpu.floss.iq_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_1.end_dist
cpu.floss.iq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_0.end_dist
cpu.floss.iq_full_deps_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_1.end_dist
cpu.floss.iq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_0.end_dist
cpu.floss.iq_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_1.end_dist
cpu.floss.lsq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_0.end_dist
cpu.floss.lsq_full_1.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_1.end_dist
cpu.floss.lsq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_0.end_dist
cpu.floss.lsq_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_1.end_dist
cpu.floss.lsq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_0.end_dist
cpu.floss.lsq_full_deps_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_1.end_dist
cpu.floss.lsq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_0.end_dist
cpu.floss.lsq_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_1.end_dist
cpu.floss.qfull_0.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_0.end_dist
cpu.floss.qfull_1.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_1.end_dist
cpu.floss.rob_full_0.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_0.end_dist
cpu.floss.rob_full_1.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_1.end_dist
cpu.floss.rob_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_0.end_dist
cpu.floss.rob_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_1.end_dist
cpu.floss.rob_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_0.end_dist
cpu.floss.rob_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_1.end_dist
cpu.icache.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
cpu.icache.avg_refs                         82.700061                       # Average number of references to valid blocks.
cpu.icache.blocked_no_mshrs                         0                       # number of cycles access was blocked
cpu.icache.blocked_no_targets                       0                       # number of cycles access was blocked
cpu.icache.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
cpu.icache.blocked_cycles_no_targets                0                       # number of cycles access was blocked
cpu.icache.cache_copies                             0                       # number of cache copies performed
cpu.icache.demand_accesses                     823593                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_0                   571422                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_1                   252171                       # number of demand (read+write) accesses
cpu.icache.demand_avg_miss_latency          24.754442                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_0        23.592105                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_1        24.847189                       # average overall miss latency
cpu.icache.demand_avg_mshr_miss_latency     37.219682                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_0    37.241206                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_1    37.217940                       # average overall mshr miss latency
cpu.icache.demand_hits                         812280                       # number of demand (read+write) hits
cpu.icache.demand_hits_0                       570586                       # number of demand (read+write) hits
cpu.icache.demand_hits_1                       241694                       # number of demand (read+write) hits
cpu.icache.demand_miss_latency                 280047                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_0                19723                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_1               260324                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_rate                  0.013736                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_0                0.001463                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_1                0.041547                       # miss rate for demand accesses
cpu.icache.demand_misses                        11313                       # number of demand (read+write) misses
cpu.icache.demand_misses_0                        836                       # number of demand (read+write) misses
cpu.icache.demand_misses_1                      10477                       # number of demand (read+write) misses
cpu.icache.demand_mshr_hits                       684                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_0                      40                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_1                     644                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_miss_latency            395608                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_0           29644                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_1          365964                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_rate             0.012906                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_0           0.001393                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_1           0.038993                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_misses                   10629                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_0                   796                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_1                  9833                       # number of demand (read+write) MSHR misses
cpu.icache.fast_writes                              0                       # number of fast writes performed
cpu.icache.mshr_cap_events                          0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_0                        0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_1                        0                       # number of times MSHR cap was activated
cpu.icache.no_allocate_misses                       0                       # Number of misses that were no-allocate
cpu.icache.overall_accesses                    823593                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_0                  571422                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_1                  252171                       # number of overall (read+write) accesses
cpu.icache.overall_avg_miss_latency         24.754442                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_0       23.592105                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_1       24.847189                       # average overall miss latency
cpu.icache.overall_avg_mshr_miss_latency    37.219682                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_0    37.241206                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_1    37.217940                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_hits                        812280                       # number of overall hits
cpu.icache.overall_hits_0                      570586                       # number of overall hits
cpu.icache.overall_hits_1                      241694                       # number of overall hits
cpu.icache.overall_miss_latency                280047                       # number of overall miss cycles
cpu.icache.overall_miss_latency_0               19723                       # number of overall miss cycles
cpu.icache.overall_miss_latency_1              260324                       # number of overall miss cycles
cpu.icache.overall_miss_rate                 0.013736                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_0               0.001463                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_1               0.041547                       # miss rate for overall accesses
cpu.icache.overall_misses                       11313                       # number of overall misses
cpu.icache.overall_misses_0                       836                       # number of overall misses
cpu.icache.overall_misses_1                     10477                       # number of overall misses
cpu.icache.overall_mshr_hits                      684                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_0                     40                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_1                    644                       # number of overall MSHR hits
cpu.icache.overall_mshr_miss_latency           395608                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_0          29644                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_1         365964                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_rate            0.012906                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_0          0.001393                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_1          0.038993                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_misses                  10629                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_0                  796                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_1                 9833                       # number of overall MSHR misses
cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.icache.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
cpu.icache.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.icache.read_accesses                       823593                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_0                     571422                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_1                     252171                       # number of read accesses(hits+misses)
cpu.icache.read_avg_miss_latency            24.754442                       # average read miss latency
cpu.icache.read_avg_miss_latency_0          23.592105                       # average read miss latency
cpu.icache.read_avg_miss_latency_1          24.847189                       # average read miss latency
cpu.icache.read_avg_mshr_miss_latency       37.219682                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_0     37.241206                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_1     37.217940                       # average read mshr miss latency
cpu.icache.read_hits                           812280                       # number of read hits
cpu.icache.read_hits_0                         570586                       # number of read hits
cpu.icache.read_hits_1                         241694                       # number of read hits
cpu.icache.read_miss_latency                   280047                       # number of read miss cycles
cpu.icache.read_miss_latency_0                  19723                       # number of read miss cycles
cpu.icache.read_miss_latency_1                 260324                       # number of read miss cycles
cpu.icache.read_miss_rate                    0.013736                       # miss rate for read accesses
cpu.icache.read_miss_rate_0                  0.001463                       # miss rate for read accesses
cpu.icache.read_miss_rate_1                  0.041547                       # miss rate for read accesses
cpu.icache.read_misses                          11313                       # number of read misses
cpu.icache.read_misses_0                          836                       # number of read misses
cpu.icache.read_misses_1                        10477                       # number of read misses
cpu.icache.read_mshr_hits                         684                       # number of read MSHR hits
cpu.icache.read_mshr_hits_0                        40                       # number of read MSHR hits
cpu.icache.read_mshr_hits_1                       644                       # number of read MSHR hits
cpu.icache.read_mshr_miss_latency              395608                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_0             29644                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_1            365964                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_rate               0.012906                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_0             0.001393                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_1             0.038993                       # mshr miss rate for read accesses
cpu.icache.read_mshr_misses                     10629                       # number of read MSHR misses
cpu.icache.read_mshr_misses_0                     796                       # number of read MSHR misses
cpu.icache.read_mshr_misses_1                    9833                       # number of read MSHR misses
cpu.icache.replacements                          8816                       # number of replacements
cpu.icache.replacements_0                         627                       # number of replacements
cpu.icache.replacements_1                        8189                       # number of replacements
cpu.icache.sampled_refs                          9822                       # Sample count of references to valid blocks.
cpu.icache.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_0                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_1                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.tagsinuse                       784.233331                       # Cycle average of tags in use
cpu.icache.total_refs                          812280                       # Total number of references to valid blocks.
cpu.icache.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
cpu.icache.writebacks                               0                       # number of writebacks
cpu.icache.writebacks_0                             0                       # number of writebacks
cpu.icache.writebacks_1                             0                       # number of writebacks
cpu.iq:RQ:rdy_inst                            2974250                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_0                          2067497                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_1                           906753                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_dist_0_mean               3.361101                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_0_stdev              4.637883                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_0_TOT        615125                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_1_mean               1.474096                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_1_stdev              3.246001                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_1_TOT        615125                       # standard deviation of ready rate
cpu.iq:RQ:rdy_rate                           4.835196                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_0                         3.361101                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_1                         1.474096                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_x_count                         1715794                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_0                       1237425                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_1                        478369                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_max                                30                       # largest number of insts that become ready
cpu.iq:RQ:rdy_x_rate                         2.789342                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_0                       2.011664                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_1                       0.777678                       # number of insts that become ready per cycle
cpu.iq:avg_residency                        17.454561                       # Average IQ residency
cpu.iq:avg_residency_0                      15.877265                       # Average IQ residency
cpu.iq:avg_residency_1                      21.643998                       # Average IQ residency
cpu.iq:cum_num_insts                         29190380                       # Total occupancy
cpu.iq:cum_num_insts_0                       19290004                       # Total occupancy
cpu.iq:cum_num_insts_1                        9900376                       # Total occupancy
cpu.iq:current_count                               24                       # Occupancy this cycle
cpu.iq:empty_count                              45073                       # Number of empty cycles
cpu.iq:empty_rate                            7.327454                       # Fraction of cycles empty
cpu.iq:full_count                              295611                       # Number of full cycles
cpu.iq:full_rate                            48.057062                       # Fraction of cycles full
cpu.iq:occ_dist_0.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_0.samples                      615125                      
cpu.iq:occ_dist_0.min_value                         0                      
                               0       141632              2302.49%
                               2         5607              2393.64%
                               4         4716              2470.31%
                               6         4573              2544.65%
                               8        33750              3093.32%
                              10         9149              3242.06%
                              12         7275              3360.33%
                              14         7369              3480.12%
                              16        10772              3655.24%
                              18        14759              3895.18%
                              20         8974              4041.06%
                              22         8317              4176.27%
                              24        10053              4339.70%
                              26        11890              4533.00%
                              28        11016              4712.08%
                              30        23282              5090.58%
                              32        23829              5477.96%
                              34        15134              5723.99%
                              36         8032              5854.57%
                              38         7653              5978.98%
                              40         8831              6122.54%
                              42         9076              6270.09%
                              44         9107              6418.14%
                              46         8757              6560.50%
                              48         8364              6696.48%
                              50        11375              6881.40%
                              52        10591              7053.57%
                              54        10786              7228.92%
                              56        11824              7421.14%
                              58        14510              7657.03%
                              60        15998              7917.11%
                              62        15682              8172.05%
                              64       112442             10000.00%
cpu.iq:occ_dist_0.max_value                        64                      
cpu.iq:occ_dist_0.end_dist

cpu.iq:occ_dist_1.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_1.samples                      615125                      
cpu.iq:occ_dist_1.min_value                         0                      
                               0       290193              4717.63%
                               2        30933              5220.50%
                               4        17126              5498.91%
                               6        15082              5744.10%
                               8        13548              5964.35%
                              10        10588              6136.48%
                              12        10357              6304.85%
                              14         9584              6460.65%
                              16         8796              6603.65%
                              18         9066              6751.03%
                              20         8269              6885.46%
                              22         7915              7014.14%
                              24         7549              7136.86%
                              26         7611              7260.59%
                              28         9452              7414.25%
                              30        17587              7700.16%
                              32        20334              8030.73%
                              34         8932              8175.93%
                              36         4950              8256.40%
                              38         2365              8294.85%
                              40         2167              8330.08%
                              42         1277              8350.84%
                              44         2206              8386.70%
                              46        10200              8552.52%
                              48         1078              8570.05%
                              50         1422              8593.16%
                              52         1269              8613.79%
                              54        27849              9066.53%
                              56         4707              9143.05%
                              58         1163              9161.96%
                              60         1872              9192.39%
                              62         3430              9248.15%
                              64        46248             10000.00%
cpu.iq:occ_dist_1.max_value                        64                      
cpu.iq:occ_dist_1.end_dist

cpu.iq:occ_rate                             47.454387                       # Average occupancy
cpu.iq:occ_rate_0                           31.359486                       # Average occupancy
cpu.iq:occ_rate_1                           16.094901                       # Average occupancy
cpu.iq:peak_occupancy                             128                       # Peak IQ occupancy
cpu.iq:peak_occupancy_0                            64                       # Peak IQ occupancy
cpu.iq:peak_occupancy_1                            64                       # Peak IQ occupancy
cpu.l2.avg_blocked_cycles_no_mshrs       <err: div-0>                       # average number of cycles each access was blocked
cpu.l2.avg_blocked_cycles_no_targets     <err: div-0>                       # average number of cycles each access was blocked
cpu.l2.avg_refs                          <err: div-0>                       # Average number of references to valid blocks.
cpu.l2.blocked_no_mshrs                             0                       # number of cycles access was blocked
cpu.l2.blocked_no_targets                           0                       # number of cycles access was blocked
cpu.l2.blocked_cycles_no_mshrs                      0                       # number of cycles access was blocked
cpu.l2.blocked_cycles_no_targets                    0                       # number of cycles access was blocked
cpu.l2.cache_copies                                 0                       # number of cache copies performed
cpu.l2.demand_accesses                          14252                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_0                         1515                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_1                        12737                       # number of demand (read+write) accesses
cpu.l2.demand_avg_miss_latency             128.530531                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_0           129.313187                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_1           128.358249                       # average overall miss latency
cpu.l2.demand_avg_mshr_miss_latency        114.402062                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_0      114.620879                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_1      114.353895                       # average overall mshr miss latency
cpu.l2.demand_hits                               9208                       # number of demand (read+write) hits
cpu.l2.demand_hits_0                              605                       # number of demand (read+write) hits
cpu.l2.demand_hits_1                             8603                       # number of demand (read+write) hits
cpu.l2.demand_miss_latency                     648308                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_0                   117675                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_1                   530633                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_rate                      0.353915                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_0                    0.600660                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_1                    0.324566                       # miss rate for demand accesses
cpu.l2.demand_misses                             5044                       # number of demand (read+write) misses
cpu.l2.demand_misses_0                            910                       # number of demand (read+write) misses
cpu.l2.demand_misses_1                           4134                       # number of demand (read+write) misses
cpu.l2.demand_mshr_hits                             0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_0                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_1                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_miss_latency                577044                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_0              104305                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_1              472739                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_rate                 0.353915                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_0               0.600660                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_1               0.324566                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_misses                        5044                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_0                       910                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_1                      4134                       # number of demand (read+write) MSHR misses
cpu.l2.falru_accesses                           14563                       # The number of accesses to the FA LRU cache.
cpu.l2.falru_hits_128K                           7459                       # Hits in a 128K cache
cpu.l2.falru_hits_256K                           9404                       # Hits in a 256K cache
cpu.l2.falru_hits_512K                           9502                       # Hits in a 512K cache
cpu.l2.falru_hits_1M                             9502                       # Hits in a 1M cache
cpu.l2.falru_hits_2M                             9502                       # Hits in a 2M cache
cpu.l2.falru_misses_128K                         7104                       # Misses in a 128K cache
cpu.l2.falru_misses_256K                         5159                       # Misses in a 256K cache
cpu.l2.falru_misses_512K                         5061                       # Misses in a 512K cache
cpu.l2.falru_misses_1M                           5061                       # Misses in a 1M cache
cpu.l2.falru_misses_2M                           5061                       # Misses in a 2M cache
cpu.l2.fast_writes                                  0                       # number of fast writes performed
cpu.l2.mshr_cap_events                              0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_0                            0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_1                            0                       # number of times MSHR cap was activated
cpu.l2.no_allocate_misses                           0                       # Number of misses that were no-allocate
cpu.l2.overall_accesses                         14563                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_0                        1570                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_1                       12993                       # number of overall (read+write) accesses
cpu.l2.overall_avg_miss_latency            128.098795                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_0          129.313187                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_1          127.832570                       # average overall miss latency
cpu.l2.overall_avg_mshr_miss_latency       114.402062                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_0     114.620879                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_1     114.353895                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_hits                              9502                       # number of overall hits
cpu.l2.overall_hits_0                             660                       # number of overall hits
cpu.l2.overall_hits_1                            8842                       # number of overall hits
cpu.l2.overall_miss_latency                    648308                       # number of overall miss cycles
cpu.l2.overall_miss_latency_0                  117675                       # number of overall miss cycles
cpu.l2.overall_miss_latency_1                  530633                       # number of overall miss cycles
cpu.l2.overall_miss_rate                     0.347525                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_0                   0.579618                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_1                   0.319480                       # miss rate for overall accesses
cpu.l2.overall_misses                            5061                       # number of overall misses
cpu.l2.overall_misses_0                           910                       # number of overall misses
cpu.l2.overall_misses_1                          4151                       # number of overall misses
cpu.l2.overall_mshr_hits                            0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_0                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_1                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_miss_latency               577044                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_0             104305                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_1             472739                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_rate                0.346357                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_0              0.579618                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_1              0.318171                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_misses                       5044                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_0                      910                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_1                     4134                       # number of overall MSHR misses
cpu.l2.overall_mshr_uncacheable_latency             0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_misses              0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.l2.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.l2.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.l2.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.l2.prefetcher.num_hwpf_evicted                  0                       # number of hwpf removed due to no buffer left
cpu.l2.prefetcher.num_hwpf_identified               0                       # number of hwpf identified
cpu.l2.prefetcher.num_hwpf_issued                   0                       # number of hwpf issued
cpu.l2.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.l2.prefetcher.num_hwpf_span_page                0                       # number of hwpf spanning a virtual page
cpu.l2.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.l2.read_accesses                            14252                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_0                           1515                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_1                          12737                       # number of read accesses(hits+misses)
cpu.l2.read_avg_miss_latency               128.530531                       # average read miss latency
cpu.l2.read_avg_miss_latency_0             129.313187                       # average read miss latency
cpu.l2.read_avg_miss_latency_1             128.358249                       # average read miss latency
cpu.l2.read_avg_mshr_miss_latency          114.402062                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_0        114.620879                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_1        114.353895                       # average read mshr miss latency
cpu.l2.read_hits                                 9208                       # number of read hits
cpu.l2.read_hits_0                                605                       # number of read hits
cpu.l2.read_hits_1                               8603                       # number of read hits
cpu.l2.read_miss_latency                       648308                       # number of read miss cycles
cpu.l2.read_miss_latency_0                     117675                       # number of read miss cycles
cpu.l2.read_miss_latency_1                     530633                       # number of read miss cycles
cpu.l2.read_miss_rate                        0.353915                       # miss rate for read accesses
cpu.l2.read_miss_rate_0                      0.600660                       # miss rate for read accesses
cpu.l2.read_miss_rate_1                      0.324566                       # miss rate for read accesses
cpu.l2.read_misses                               5044                       # number of read misses
cpu.l2.read_misses_0                              910                       # number of read misses
cpu.l2.read_misses_1                             4134                       # number of read misses
cpu.l2.read_mshr_miss_latency                  577044                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_0                104305                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_1                472739                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_rate                   0.353915                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_0                 0.600660                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_1                 0.324566                       # mshr miss rate for read accesses
cpu.l2.read_mshr_misses                          5044                       # number of read MSHR misses
cpu.l2.read_mshr_misses_0                         910                       # number of read MSHR misses
cpu.l2.read_mshr_misses_1                        4134                       # number of read MSHR misses
cpu.l2.replacements                                 0                       # number of replacements
cpu.l2.replacements_0                               0                       # number of replacements
cpu.l2.replacements_1                               0                       # number of replacements
cpu.l2.sampled_refs                                 0                       # Sample count of references to valid blocks.
cpu.l2.soft_prefetch_mshr_full                      0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_0                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_1                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.tagsinuse                          3100.333191                       # Cycle average of tags in use
cpu.l2.total_refs                                   0                       # Total number of references to valid blocks.
cpu.l2.warmup_cycle                                 0                       # Cycle when the warmup percentage was hit.
cpu.l2.writeback_accesses                         311                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_0                        55                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_1                       256                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_hits                             294                       # number of writeback hits
cpu.l2.writeback_hits_0                            55                       # number of writeback hits
cpu.l2.writeback_hits_1                           239                       # number of writeback hits
cpu.l2.writeback_miss_rate                   0.054662                       # miss rate for writeback accesses
cpu.l2.writeback_miss_rate_1                 0.066406                       # miss rate for writeback accesses
cpu.l2.writeback_misses                            17                       # number of writeback misses
cpu.l2.writeback_misses_1                          17                       # number of writeback misses
cpu.l2.writeback_mshr_miss_rate              0.054662                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_miss_rate_1            0.066406                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_misses                       17                       # number of writeback MSHR misses
cpu.l2.writeback_mshr_misses_1                     17                       # number of writeback MSHR misses
cpu.l2.writebacks                                   0                       # number of writebacks
cpu.l2.writebacks_0                                 0                       # number of writebacks
cpu.l2.writebacks_1                                 0                       # number of writebacks
cpu.numCycles                                  615125                       # number of cpu cycles simulated
cpu.toL2Bus.addr_idle_cycles                   600491                       # number of cycles bus was idle
cpu.toL2Bus.addr_idle_fraction               0.976211                       # fraction of time addr bus was idle
cpu.toL2Bus.addr_queued                      3.584426                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_0                    4.066242                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_1                    3.526206                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_cycles                  52200                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_0                 6384                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_1                45816                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_requests                       14563                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_0                      1570                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_1                     12993                       # number of transmissions on bus
cpu.toL2Bus.bus_blocked                             0                       # number of times bus was blocked
cpu.toL2Bus.bus_blocked_cycles                      0                       # number of cycles bus was blocked
cpu.toL2Bus.bus_blocked_fraction                    0                       # fraction of time bus was blocked
cpu.toL2Bus.data_idle_cycles                   600502                       # number of cycles bus was idle
cpu.toL2Bus.data_idle_fraction               0.976229                       # fraction of time data bus was idle
cpu.toL2Bus.data_queued                      1.005473                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_0                    1.003960                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_1                    1.005653                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_cycles                  14330                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_0                 1521                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_1                12809                       # total number of queued cycles for all requests
cpu.toL2Bus.data_requests                       14252                       # number of transmissions on bus
cpu.toL2Bus.data_requests_0                      1515                       # number of transmissions on bus
cpu.toL2Bus.data_requests_1                     12737                       # number of transmissions on bus
cpu.toL2Bus.null_grants                           578                       # number of null grants (wasted cycles)
cpu.workload0.MainMem.page_count                    0                       # total number of pages allocated
cpu.workload0.MainMem.page_mem                      0                       # total size of memory pages allocated
cpu.workload0.MainMem.ptab_accesses           2900766                       # total page table accessess
cpu.workload0.MainMem.ptab_miss_rate           0.0096                       # first level page table miss rate
cpu.workload0.MainMem.ptab_misses               27990                       # total first level page table misses
cpu.workload0.PROG:num_syscalls                   639                       # Number of system calls
cpu.workload1.MainMem.page_count                    1                       # total number of pages allocated
cpu.workload1.MainMem.page_mem                      8                       # total size of memory pages allocated
cpu.workload1.MainMem.ptab_accesses           1334149                       # total page table accessess
cpu.workload1.MainMem.ptab_miss_rate           0.0105                       # first level page table miss rate
cpu.workload1.MainMem.ptab_misses               13988                       # total first level page table misses
cpu.workload1.PROG:num_syscalls                    79                       # Number of system calls
cpuinst_class_dist.start_dist
                   All ops ready            0      0.00%            # Operand status at dispatch
                One op not ready            0      0.00%            # Operand status at dispatch
           None rdy, mult chains            0      0.00%            # Operand status at dispatch
           None rdy, one chained            0      0.00%            # Operand status at dispatch
        None rdy, all self-timed            0      0.00%            # Operand status at dispatch
cpuinst_class_dist.end_dist
host_inst_rate                                  63795                       # Simulator instruction rate (inst/s)
host_mem_usage                                  18968                       # Number of bytes of host memory used
host_seconds                                    20.78                       # Real time elapsed on the host
host_tick_rate                                  29601                       # Simulator tick rate (ticks/s)
ram.accesses                                     5061                       # total number of accesses
ram.accesses_0                                    910                       # total number of accesses
ram.accesses_1                                   4151                       # total number of accesses
ram.bytes_requested                                 0                       # total number of bytes requested
ram.bytes_requested_0                               0                       # total number of bytes requested
ram.bytes_requested_1                               0                       # total number of bytes requested
ram.bytes_sent                                      0                       # total number of bytes sent
ram.bytes_sent_0                                    0                       # total number of bytes sent
ram.bytes_sent_1                                    0                       # total number of bytes sent
ram.compressed_responses                            0                       # total number of accesses that are compressed
ram.compressed_responses_0                          0                       # total number of accesses that are compressed
ram.compressed_responses_1                          0                       # total number of accesses that are compressed
sim_freq                                    200000000                       # Frequency of simulated ticks
sim_insts                                     1325646                       # Number of instructions simulated
sim_seconds                                  0.003076                       # Number of seconds simulated
sim_ticks                                      615124                       # Number of ticks simulated
toMemBus.addr_idle_cycles                      609788                       # number of cycles bus was idle
toMemBus.addr_idle_fraction                  0.991325                       # fraction of time addr bus was idle
toMemBus.addr_queued                        11.653231                       # average queueing delay seen by bus request
toMemBus.addr_queued_0                      11.398901                       # average queueing delay seen by bus request
toMemBus.addr_queued_1                      11.708986                       # average queueing delay seen by bus request
toMemBus.addr_queued_cycles                     58977                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_0                   10373                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_1                   48604                       # total number of queued cycles for all requests
toMemBus.addr_requests                           5061                       # number of transmissions on bus
toMemBus.addr_requests_0                          910                       # number of transmissions on bus
toMemBus.addr_requests_1                         4151                       # number of transmissions on bus
toMemBus.bus_blocked                                0                       # number of times bus was blocked
toMemBus.bus_blocked_cycles                         0                       # number of cycles bus was blocked
toMemBus.bus_blocked_fraction                       0                       # fraction of time bus was blocked
toMemBus.data_idle_cycles                      594709                       # number of cycles bus was idle
toMemBus.data_idle_fraction                  0.966812                       # fraction of time data bus was idle
toMemBus.data_queued                         1.749603                       # average queueing delay seen by bus request
toMemBus.data_queued_0                       2.221978                       # average queueing delay seen by bus request
toMemBus.data_queued_1                       1.645622                       # average queueing delay seen by bus request
toMemBus.data_queued_cycles                      8825                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_0                    2022                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_1                    6803                       # total number of queued cycles for all requests
toMemBus.data_requests                           5044                       # number of transmissions on bus
toMemBus.data_requests_0                          910                       # number of transmissions on bus
toMemBus.data_requests_1                         4134                       # number of transmissions on bus
toMemBus.null_grants                                0                       # number of null grants (wasted cycles)

---------- End Simulation Statistics   ----------
