
---------- Begin Simulation Statistics ----------
cpu.COM:IPB                                  6.578497                       # Committed instructions per branch
cpu.COM:IPB_0                                5.986997                       # Committed instructions per branch
cpu.COM:IPB_1                                6.177443                       # Committed instructions per branch
cpu.COM:IPB_2                                7.872784                       # Committed instructions per branch
cpu.COM:IPB_3                                5.952051                       # Committed instructions per branch
cpu.COM:IPC                                  4.123961                       # Committed instructions per cycle
cpu.COM:IPC_0                                1.267507                       # Committed instructions per cycle
cpu.COM:IPC_1                                0.446382                       # Committed instructions per cycle
cpu.COM:IPC_2                                1.512572                       # Committed instructions per cycle
cpu.COM:IPC_3                                0.897499                       # Committed instructions per cycle
cpu.COM:branches                               414450                       # Number of branches committed
cpu.COM:branches_0                             139967                       # Number of branches committed
cpu.COM:branches_1                              47773                       # Number of branches committed
cpu.COM:branches_2                             127020                       # Number of branches committed
cpu.COM:branches_3                              99690                       # Number of branches committed
cpu.COM:bw_lim_avg                            17.6299                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_0                           4.1713                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_1                           2.0629                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_2                           7.8557                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_3                           3.5400                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_events                          174593                       # number cycles where commit BW limit reached
cpu.COM:bw_lim_rate                            4.6558                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_0                          1.1016                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_1                          0.5448                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_2                          2.0746                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_3                          0.9349                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_stdev_0_mean                    4.1713                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_0_stdev                   6.7612                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_0_TOT      174593.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_1_mean                    2.0629                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_1_stdev                   7.3270                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_1_TOT      174593.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_2_mean                    7.8557                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_2_stdev                  16.6279                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_2_TOT      174593.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_3_mean                    3.5400                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_3_stdev                   9.3431                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_3_TOT      174593.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_limited                            3078053                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_0                           728273                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_1                           360168                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_2                          1371557                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_3                           618055                       # number of insts not committed due to BW limits
cpu.COM:committed_per_cycle.start_dist                         # Number of insts commited each cycle
cpu.COM:committed_per_cycle.samples            554662                      
cpu.COM:committed_per_cycle.min_value               0                      
                               0         1667     30.05%           
                               1        78886   1422.24%           
                               2        66829   1204.86%           
                               3        60782   1095.84%           
                               4        55126    993.87%           
                               5        40107    723.09%           
                               6        33758    608.62%           
                               7        26080    470.20%           
                               8       191427   3451.24%           
cpu.COM:committed_per_cycle.max_value               8                      
cpu.COM:committed_per_cycle.end_dist

cpu.COM:count                                 2726458                       # Number of instructions committed
cpu.COM:count_0                                837982                       # Number of instructions committed
cpu.COM:count_1                                295115                       # Number of instructions committed
cpu.COM:count_2                               1000001                       # Number of instructions committed
cpu.COM:count_3                                593360                       # Number of instructions committed
cpu.COM:loads                                  698784                       # Number of loads committed
cpu.COM:loads_0                                250749                       # Number of loads committed
cpu.COM:loads_1                                 73254                       # Number of loads committed
cpu.COM:loads_2                                255902                       # Number of loads committed
cpu.COM:loads_3                                118879                       # Number of loads committed
cpu.COM:membars                                     0                       # Number of memory barriers committed
cpu.COM:membars_0                                   0                       # Number of memory barriers committed
cpu.COM:membars_1                                   0                       # Number of memory barriers committed
cpu.COM:membars_2                                   0                       # Number of memory barriers committed
cpu.COM:membars_3                                   0                       # Number of memory barriers committed
cpu.COM:refs                                  1021369                       # Number of memory references committed
cpu.COM:refs_0                                 331697                       # Number of memory references committed
cpu.COM:refs_1                                 107338                       # Number of memory references committed
cpu.COM:refs_2                                 371156                       # Number of memory references committed
cpu.COM:refs_3                                 211178                       # Number of memory references committed
cpu.COM:stores                                 322585                       # Number of stores committed
cpu.COM:stores_0                                80948                       # Number of stores committed
cpu.COM:stores_1                                34084                       # Number of stores committed
cpu.COM:stores_2                               115254                       # Number of stores committed
cpu.COM:stores_3                                92299                       # Number of stores committed
cpu.COM:swp_count                                5995                       # Number of s/w prefetches committed
cpu.COM:swp_count_0                               524                       # Number of s/w prefetches committed
cpu.COM:swp_count_1                               725                       # Number of s/w prefetches committed
cpu.COM:swp_count_2                                16                       # Number of s/w prefetches committed
cpu.COM:swp_count_3                              4730                       # Number of s/w prefetches committed
cpu.DDQ:count                               167468371                       # cum count of instructions
cpu.DDQ:count_0                              50257445                       # cum count of instructions
cpu.DDQ:count_1                              29808507                       # cum count of instructions
cpu.DDQ:count_2                              49898955                       # cum count of instructions
cpu.DDQ:count_3                              37503464                       # cum count of instructions
cpu.DDQ:rate                                      253                       # average number of instructions
cpu.DDQ:rate_0                                     76                       # average number of instructions
cpu.DDQ:rate_1                                     45                       # average number of instructions
cpu.DDQ:rate_2                                     75                       # average number of instructions
cpu.DDQ:rate_3                                     57                       # average number of instructions
cpu.DIS:chain_creation.start_dist
     Inst has no outstanding IDEPS            0      0.00%            # Reason that chain head was created
      IDEP chain reached max depth            0      0.00%            # Reason that chain head was created
                    Inst is a load            0      0.00%            # Reason that chain head was created
  Chain has multiple chained IDEPS            0      0.00%            # Reason that chain head was created
cpu.DIS:chain_creation.end_dist
cpu.DIS:chain_head_frac                             0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_0                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_1                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_2                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_3                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_heads                                 0                       # number insts that are chain heads
cpu.DIS:chain_heads_0                               0                       # number insts that are chain heads
cpu.DIS:chain_heads_1                               0                       # number insts that are chain heads
cpu.DIS:chain_heads_2                               0                       # number insts that are chain heads
cpu.DIS:chain_heads_3                               0                       # number insts that are chain heads
cpu.DIS:chains_insuf                                0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_0                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_1                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_2                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_3                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_rate                           0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_0                         0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_1                         0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_2                         0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_3                         0                       # rate that thread had insuf chains
cpu.DIS:count                                 3237103                       # cumulative count of dispatched insts
cpu.DIS:count_0                                992895                       # cumulative count of dispatched insts
cpu.DIS:count_1                                416850                       # cumulative count of dispatched insts
cpu.DIS:count_2                               1079703                       # cumulative count of dispatched insts
cpu.DIS:count_3                                747655                       # cumulative count of dispatched insts
cpu.DIS:insufficient_chains                         0                       # Number of instances where dispatch stopped
cpu.DIS:mod_n_stall_avg_free                 no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_0               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_1               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_2               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_3               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_frac                            0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_0                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_1                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_2                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_3                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_free                            0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_0                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_1                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_2                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_3                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls                                0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_0                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_1                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_2                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_3                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:one_rdy_insts                               0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_0                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_1                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_2                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_3                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_ratio                        no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_0                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_1                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_2                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_3                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:op_count                              4448321                       # number of operations dispatched
cpu.DIS:op_count_0                            1388342                       # number of operations dispatched
cpu.DIS:op_count_1                             570006                       # number of operations dispatched
cpu.DIS:op_count_2                            1482578                       # number of operations dispatched
cpu.DIS:op_count_3                            1007395                       # number of operations dispatched
cpu.DIS:op_rate                              6.728401                       # dispatched operations per cycle
cpu.DIS:op_rate_0                            2.099966                       # dispatched operations per cycle
cpu.DIS:op_rate_1                            0.862175                       # dispatched operations per cycle
cpu.DIS:op_rate_2                            2.242504                       # dispatched operations per cycle
cpu.DIS:op_rate_3                            1.523756                       # dispatched operations per cycle
cpu.DIS:rate                                 4.896348                       # dispatched_insts per cycle
cpu.DIS:rate_0                               1.501824                       # dispatched_insts per cycle
cpu.DIS:rate_1                               0.630515                       # dispatched_insts per cycle
cpu.DIS:rate_2                               1.633127                       # dispatched_insts per cycle
cpu.DIS:rate_3                               1.130881                       # dispatched_insts per cycle
cpu.DIS:second_choice_clust                         0                       # Number of instructions dispatched to second-choice cluster
cpu.DIS:second_choice_stall                         0                       # Number of instructions stalled when first choice not available
cpu.DIS:serialize_stall_cycles                      0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_0                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_1                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_2                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_3                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serializing_insts                           0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_0                         0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_1                         0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_2                         0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_3                         0                       # count of serializing insts dispatched
cpu.DIS:two_input_insts                             0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_0                           0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_1                           0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_2                           0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_3                           0                       # Number of two input instructions queued
cpu.DIS:two_input_ratio                             0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_0                           0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_1                           0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_2                           0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_3                           0                       # fraction of all insts having 2 inputs
cpu.FETCH:branch_count                         633279                       # Number of branches fetched
cpu.FETCH:branch_count_0                       208316                       # Number of branches fetched
cpu.FETCH:branch_count_1                        96365                       # Number of branches fetched
cpu.FETCH:branch_count_2                       160233                       # Number of branches fetched
cpu.FETCH:branch_count_3                       168365                       # Number of branches fetched
cpu.FETCH:branch_rate                        0.957879                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_0                      0.315093                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_1                      0.145759                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_2                      0.242364                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_3                      0.254664                       # Number of branch fetches per cycle
cpu.FETCH:chance_pct_0                       0.304918                       # Percentage of all fetch chances
cpu.FETCH:chance_pct_1                       0.157510                       # Percentage of all fetch chances
cpu.FETCH:chance_pct_2                       0.282923                       # Percentage of all fetch chances
cpu.FETCH:chance_pct_3                       0.254649                       # Percentage of all fetch chances
cpu.FETCH:chances                              629192                       # Number of fetch opportunities
cpu.FETCH:chances_0                            191852                       # Number of fetch opportunities
cpu.FETCH:chances_1                             99104                       # Number of fetch opportunities
cpu.FETCH:chances_2                            178013                       # Number of fetch opportunities
cpu.FETCH:chances_3                            160223                       # Number of fetch opportunities
cpu.FETCH:choice                               629192                       # Number of times we fetched from our first choice
cpu.FETCH:choice.start_dist
                               0       629192    100.00%            # Number of times we fetched from our first choice
                               1            0      0.00%            # Number of times we fetched from our first choice
                               2            0      0.00%            # Number of times we fetched from our first choice
                               3            0      0.00%            # Number of times we fetched from our first choice
cpu.FETCH:choice.end_dist
cpu.FETCH:count                               4820408                       # Number of instructions fetched
cpu.FETCH:count_0                             1417424                       # Number of instructions fetched
cpu.FETCH:count_1                              771938                       # Number of instructions fetched
cpu.FETCH:count_2                             1380469                       # Number of instructions fetched
cpu.FETCH:count_3                             1250577                       # Number of instructions fetched
cpu.FETCH:decisions                            629192                       # number of times the fetch stage chose between threads
cpu.FETCH:idle_cycles                           31934                       # number of cycles where fetch stage was idle
cpu.FETCH:idle_icache_blocked_cycles                0                       # number of cycles where fetch was idle due to icache blocked
cpu.FETCH:idle_rate                              4.83                       # percent of cycles fetch stage was idle
cpu.FETCH:prio_changes                              0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_0                            0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_1                            0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_2                            0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_3                            0                       # Number of times priorities were changed
cpu.FETCH:rate                               7.291209                       # Number of inst fetches per cycle
cpu.FETCH:rate_0                             2.143954                       # Number of inst fetches per cycle
cpu.FETCH:rate_1                             1.167611                       # Number of inst fetches per cycle
cpu.FETCH:rate_2                             2.088057                       # Number of inst fetches per cycle
cpu.FETCH:rate_3                             1.891586                       # Number of inst fetches per cycle
cpu.FETCH:rate_dist.start_dist                                 # Number of instructions fetched each cycle (Total)
cpu.FETCH:rate_dist.samples                    629192                      
cpu.FETCH:rate_dist.min_value                       0                      
                               0         1311     20.84%           
                               1         2368     37.64%           
                               2         2605     41.40%           
                               3         3372     53.59%           
                               4         6353    100.97%           
                               5         8926    141.86%           
                               6        45149    717.57%           
                               7        11086    176.19%           
                               8       548022   8709.93%           
cpu.FETCH:rate_dist.max_value                       8                      
cpu.FETCH:rate_dist.end_dist

cpu.FETCH:rate_dist_0.start_dist                               # Number of instructions fetched each cycle (Thread 0)
cpu.FETCH:rate_dist_0.samples                  191852                      
cpu.FETCH:rate_dist_0.min_value                     0                      
                               0          801     41.75%           
                               1         1111     57.91%           
                               2         1167     60.83%           
                               3         1339     69.79%           
                               4         2069    107.84%           
                               5         3792    197.65%           
                               6        33022   1721.22%           
                               7         3814    198.80%           
                               8       144737   7544.20%           
cpu.FETCH:rate_dist_0.max_value                     8                      
cpu.FETCH:rate_dist_0.end_dist

cpu.FETCH:rate_dist_1.start_dist                               # Number of instructions fetched each cycle (Thread 1)
cpu.FETCH:rate_dist_1.samples                   99104                      
cpu.FETCH:rate_dist_1.min_value                     0                      
                               0          343     34.61%           
                               1          270     27.24%           
                               2          273     27.55%           
                               3          456     46.01%           
                               4         1138    114.83%           
                               5          801     80.82%           
                               6         1595    160.94%           
                               7         2197    221.69%           
                               8        92031   9286.31%           
cpu.FETCH:rate_dist_1.max_value                     8                      
cpu.FETCH:rate_dist_1.end_dist

cpu.FETCH:rate_dist_2.start_dist                               # Number of instructions fetched each cycle (Thread 2)
cpu.FETCH:rate_dist_2.samples                  178013                      
cpu.FETCH:rate_dist_2.min_value                     1                      
                               0            0      0.00%           
                               1          570     32.02%           
                               2          696     39.10%           
                               3         1014     56.96%           
                               4         1897    106.57%           
                               5         2701    151.73%           
                               6         6570    369.07%           
                               7         1568     88.08%           
                               8       162997   9156.47%           
cpu.FETCH:rate_dist_2.max_value                     8                      
cpu.FETCH:rate_dist_2.end_dist

cpu.FETCH:rate_dist_3.start_dist                               # Number of instructions fetched each cycle (Thread 3)
cpu.FETCH:rate_dist_3.samples                  160223                      
cpu.FETCH:rate_dist_3.min_value                     0                      
                               0          167     10.42%           
                               1          417     26.03%           
                               2          469     29.27%           
                               3          563     35.14%           
                               4         1249     77.95%           
                               5         1632    101.86%           
                               6         3962    247.28%           
                               7         3507    218.88%           
                               8       148257   9253.17%           
cpu.FETCH:rate_dist_3.max_value                     8                      
cpu.FETCH:rate_dist_3.end_dist

cpu.IFQ:count                                32466291                       # cumulative IFQ occupancy
cpu.IFQ:full_count                             343467                       # cumulative IFQ full count
cpu.IFQ:full_count_0                           111011                       # cumulative IFQ full count
cpu.IFQ:full_count_1                            65841                       # cumulative IFQ full count
cpu.IFQ:full_count_2                           113166                       # cumulative IFQ full count
cpu.IFQ:full_count_3                            53449                       # cumulative IFQ full count
cpu.IFQ:full_rate                           51.951822                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_0                         16.791202                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_1                          9.958919                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_2                         17.117161                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_3                          8.084541                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:latency                             10.029428                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_0                           32.698615                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_1                           77.884829                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_2                           30.069650                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_3                           43.424161                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:occupancy                           49.107570                       # avg IFQ occupancy (inst's)
cpu.IFQ:qfull_iq_occ                         12675148                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_0                        3742527                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_1                        3143369                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_2                        3581752                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_3                        2207500                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_0.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_0.samples            277040                      
cpu.IFQ:qfull_iq_occ_dist_0.min_value               0                      
                               0        99353   3586.23%           
                              10       119207   4302.88%           
                              20        44105   1592.01%           
                              30         9520    343.63%           
                              40         1914     69.09%           
                              50         1514     54.65%           
                              60         1427     51.51%           
cpu.IFQ:qfull_iq_occ_dist_0.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_0.end_dist

cpu.IFQ:qfull_iq_occ_dist_1.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_1.samples            277040                      
cpu.IFQ:qfull_iq_occ_dist_1.min_value               0                      
                               0       135614   4895.11%           
                              10        90834   3278.73%           
                              20        34199   1234.44%           
                              30         8943    322.81%           
                              40         3834    138.39%           
                              50         2333     84.21%           
                              60         1283     46.31%           
cpu.IFQ:qfull_iq_occ_dist_1.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_1.end_dist

cpu.IFQ:qfull_iq_occ_dist_2.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_2.samples            277040                      
cpu.IFQ:qfull_iq_occ_dist_2.min_value               0                      
                               0        97553   3521.26%           
                              10       129831   4686.36%           
                              20        42143   1521.19%           
                              30         7070    255.20%           
                              40          206      7.44%           
                              50          192      6.93%           
                              60           45      1.62%           
cpu.IFQ:qfull_iq_occ_dist_2.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_2.end_dist

cpu.IFQ:qfull_iq_occ_dist_3.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_3.samples            277040                      
cpu.IFQ:qfull_iq_occ_dist_3.min_value               0                      
                               0       160458   5791.87%           
                              10        95394   3443.33%           
                              20        20119    726.21%           
                              30          843     30.43%           
                              40           93      3.36%           
                              50          125      4.51%           
                              60            8      0.29%           
cpu.IFQ:qfull_iq_occ_dist_3.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_3.end_dist

cpu.IFQ:qfull_rob_occ                        29121032                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_0                       7875642                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_1                       5535166                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_2                      10329357                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_3                       5380867                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_0.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_0.samples           277040                      
cpu.IFQ:qfull_rob_occ_dist_0.min_value              0                      
                               0        38557   1391.75%           
                              10        42715   1541.84%           
                              20        87063   3142.61%           
                              30        52673   1901.28%           
                              40        29549   1066.60%           
                              50        12923    466.47%           
                              60         5341    192.79%           
                              70         2173     78.44%           
                              80         1346     48.59%           
                              90         1044     37.68%           
                             100          778     28.08%           
                             110         1015     36.64%           
                             120          163      5.88%           
                             130          113      4.08%           
                             140          149      5.38%           
                             150          161      5.81%           
                             160          112      4.04%           
                             170           77      2.78%           
                             180          720     25.99%           
                             190          368     13.28%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_0.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_0.end_dist

cpu.IFQ:qfull_rob_occ_dist_1.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_1.samples           277040                      
cpu.IFQ:qfull_rob_occ_dist_1.min_value              0                      
                               0        93113   3360.99%           
                              10        43020   1552.84%           
                              20        80305   2898.68%           
                              30        33709   1216.76%           
                              40        10762    388.46%           
                              50         6681    241.16%           
                              60         3809    137.49%           
                              70         2454     88.58%           
                              80          574     20.72%           
                              90          482     17.40%           
                             100          270      9.75%           
                             110          295     10.65%           
                             120          249      8.99%           
                             130          167      6.03%           
                             140          363     13.10%           
                             150          194      7.00%           
                             160          352     12.71%           
                             170          128      4.62%           
                             180            6      0.22%           
                             190          107      3.86%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_1.max_value            195                      
cpu.IFQ:qfull_rob_occ_dist_1.end_dist

cpu.IFQ:qfull_rob_occ_dist_2.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_2.samples           277040                      
cpu.IFQ:qfull_rob_occ_dist_2.min_value              0                      
                               0        30711   1108.54%           
                              10        37565   1355.94%           
                              20        85928   3101.65%           
                              30        51919   1874.06%           
                              40        21957    792.56%           
                              50        11355    409.87%           
                              60         6536    235.92%           
                              70         3149    113.67%           
                              80         3195    115.33%           
                              90         2554     92.19%           
                             100         3330    120.20%           
                             110         2845    102.69%           
                             120         2522     91.03%           
                             130         3015    108.83%           
                             140         3341    120.60%           
                             150         2299     82.98%           
                             160         1885     68.04%           
                             170         1444     52.12%           
                             180          645     23.28%           
                             190          845     30.50%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_2.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_2.end_dist

cpu.IFQ:qfull_rob_occ_dist_3.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_3.samples           277040                      
cpu.IFQ:qfull_rob_occ_dist_3.min_value              0                      
                               0        90405   3263.25%           
                              10        46061   1662.61%           
                              20        80997   2923.66%           
                              30        34911   1260.14%           
                              40        11833    427.12%           
                              50         5738    207.12%           
                              60         3367    121.53%           
                              70         1409     50.86%           
                              80          814     29.38%           
                              90          217      7.83%           
                             100          312     11.26%           
                             110           80      2.89%           
                             120          153      5.52%           
                             130          116      4.19%           
                             140           73      2.63%           
                             150           57      2.06%           
                             160           81      2.92%           
                             170           27      0.97%           
                             180          282     10.18%           
                             190          107      3.86%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_3.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_3.end_dist

cpu.IQ:cap_events                                   0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_0                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_1                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_2                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_3                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_inst                                     0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_0                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_1                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_2                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_3                                   0                       # number of instructions held up by IQ cap
cpu.IQ:residence:(null).start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:(null).samples                     0                      
cpu.IQ:residence:(null).min_value                   0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:(null).max_value                   0                      
cpu.IQ:residence:(null).end_dist

cpu.IQ:residence:IntAlu.start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:IntAlu.samples               1861890                      
cpu.IQ:residence:IntAlu.min_value                   1                      
                               0       165034    886.38%    886.38%
                               2       226418   1216.07%   2102.44%
                               4       208004   1117.17%   3219.61%
                               6       267841   1438.54%   4658.15%
                               8       252040   1353.68%   6011.83%
                              10       226517   1216.60%   7228.43%
                              12       160439    861.70%   8090.13%
                              14       122656    658.77%   8748.90%
                              16        84199    452.22%   9201.12%
                              18        54040    290.24%   9491.37%
                              20        30495    163.79%   9655.15%
                              22        15842     85.09%   9740.24%
                              24         7607     40.86%   9781.09%
                              26         3580     19.23%   9800.32%
                              28         2093     11.24%   9811.56%
                              30         1400      7.52%   9819.08%
                              32          941      5.05%   9824.14%
                              34          731      3.93%   9828.06%
                              36          617      3.31%   9831.38%
                              38          486      2.61%   9833.99%
                              40          456      2.45%   9836.44%
                              42          889      4.77%   9841.21%
                              44          576      3.09%   9844.30%
                              46          369      1.98%   9846.29%
                              48          269      1.44%   9847.73%
                              50          221      1.19%   9848.92%
                              52          230      1.24%   9850.15%
                              54          308      1.65%   9851.81%
                              56          238      1.28%   9853.08%
                              58          231      1.24%   9854.33%
                              60          267      1.43%   9855.76%
                              62          204      1.10%   9856.86%
                              64          263      1.41%   9858.27%
                              66          231      1.24%   9859.51%
                              68          249      1.34%   9860.85%
                              70          231      1.24%   9862.09%
                              72          186      1.00%   9863.09%
                              74          203      1.09%   9864.18%
                              76          198      1.06%   9865.24%
                              78          205      1.10%   9866.34%
                              80          209      1.12%   9867.46%
                              82          222      1.19%   9868.65%
                              84          223      1.20%   9869.85%
                              86          206      1.11%   9870.96%
                              88          253      1.36%   9872.32%
                              90          200      1.07%   9873.39%
                              92          254      1.36%   9874.76%
                              94          249      1.34%   9876.09%
                              96          286      1.54%   9877.63%
                              98          321      1.72%   9879.35%
cpu.IQ:residence:IntAlu.overflows               22463                      
cpu.IQ:residence:IntAlu.max_value                1150                      
cpu.IQ:residence:IntAlu.end_dist

cpu.IQ:residence:IntMult.start_dist                            # cycles from dispatch to issue
cpu.IQ:residence:IntMult.samples                  705                      
cpu.IQ:residence:IntMult.min_value                  1                      
                               0           58    822.70%    822.70%
                               2           98   1390.07%   2212.77%
                               4           73   1035.46%   3248.23%
                               6          165   2340.43%   5588.65%
                               8          106   1503.55%   7092.20%
                              10           75   1063.83%   8156.03%
                              12           58    822.70%   8978.72%
                              14           36    510.64%   9489.36%
                              16           10    141.84%   9631.21%
                              18            1     14.18%   9645.39%
                              20            2     28.37%   9673.76%
                              22            2     28.37%   9702.13%
                              24            3     42.55%   9744.68%
                              26            2     28.37%   9773.05%
                              28            0      0.00%   9773.05%
                              30            1     14.18%   9787.23%
                              32            0      0.00%   9787.23%
                              34            0      0.00%   9787.23%
                              36            0      0.00%   9787.23%
                              38            0      0.00%   9787.23%
                              40            0      0.00%   9787.23%
                              42            0      0.00%   9787.23%
                              44            0      0.00%   9787.23%
                              46            0      0.00%   9787.23%
                              48            0      0.00%   9787.23%
                              50            0      0.00%   9787.23%
                              52            0      0.00%   9787.23%
                              54            0      0.00%   9787.23%
                              56            0      0.00%   9787.23%
                              58            0      0.00%   9787.23%
                              60            0      0.00%   9787.23%
                              62            0      0.00%   9787.23%
                              64            0      0.00%   9787.23%
                              66            0      0.00%   9787.23%
                              68            0      0.00%   9787.23%
                              70            0      0.00%   9787.23%
                              72            0      0.00%   9787.23%
                              74            0      0.00%   9787.23%
                              76            0      0.00%   9787.23%
                              78            0      0.00%   9787.23%
                              80            0      0.00%   9787.23%
                              82            0      0.00%   9787.23%
                              84            0      0.00%   9787.23%
                              86            1     14.18%   9801.42%
                              88            0      0.00%   9801.42%
                              90            1     14.18%   9815.60%
                              92            0      0.00%   9815.60%
                              94            0      0.00%   9815.60%
                              96            1     14.18%   9829.79%
                              98            1     14.18%   9843.97%
cpu.IQ:residence:IntMult.overflows                 11                      
cpu.IQ:residence:IntMult.max_value                138                      
cpu.IQ:residence:IntMult.end_dist

cpu.IQ:residence:IntDiv.start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:IntDiv.samples                     0                      
cpu.IQ:residence:IntDiv.min_value                   0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:IntDiv.max_value                   0                      
cpu.IQ:residence:IntDiv.end_dist

cpu.IQ:residence:FloatAdd.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatAdd.samples                 110                      
cpu.IQ:residence:FloatAdd.min_value                 1                      
                               0            7    636.36%    636.36%
                               2           17   1545.45%   2181.82%
                               4            9    818.18%   3000.00%
                               6            7    636.36%   3636.36%
                               8           13   1181.82%   4818.18%
                              10           16   1454.55%   6272.73%
                              12           10    909.09%   7181.82%
                              14            9    818.18%   8000.00%
                              16            8    727.27%   8727.27%
                              18            5    454.55%   9181.82%
                              20            4    363.64%   9545.45%
                              22            1     90.91%   9636.36%
                              24            0      0.00%   9636.36%
                              26            0      0.00%   9636.36%
                              28            1     90.91%   9727.27%
                              30            0      0.00%   9727.27%
                              32            0      0.00%   9727.27%
                              34            1     90.91%   9818.18%
                              36            0      0.00%   9818.18%
                              38            0      0.00%   9818.18%
                              40            0      0.00%   9818.18%
                              42            0      0.00%   9818.18%
                              44            0      0.00%   9818.18%
                              46            0      0.00%   9818.18%
                              48            0      0.00%   9818.18%
                              50            0      0.00%   9818.18%
                              52            0      0.00%   9818.18%
                              54            0      0.00%   9818.18%
                              56            0      0.00%   9818.18%
                              58            0      0.00%   9818.18%
                              60            0      0.00%   9818.18%
                              62            0      0.00%   9818.18%
                              64            0      0.00%   9818.18%
                              66            0      0.00%   9818.18%
                              68            0      0.00%   9818.18%
                              70            0      0.00%   9818.18%
                              72            0      0.00%   9818.18%
                              74            0      0.00%   9818.18%
                              76            0      0.00%   9818.18%
                              78            0      0.00%   9818.18%
                              80            0      0.00%   9818.18%
                              82            0      0.00%   9818.18%
                              84            0      0.00%   9818.18%
                              86            0      0.00%   9818.18%
                              88            0      0.00%   9818.18%
                              90            0      0.00%   9818.18%
                              92            0      0.00%   9818.18%
                              94            0      0.00%   9818.18%
                              96            0      0.00%   9818.18%
                              98            0      0.00%   9818.18%
cpu.IQ:residence:FloatAdd.overflows                 2                      
cpu.IQ:residence:FloatAdd.max_value               149                      
cpu.IQ:residence:FloatAdd.end_dist

cpu.IQ:residence:FloatCmp.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatCmp.samples                   7                      
cpu.IQ:residence:FloatCmp.min_value                 7                      
                               0            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               6            1   1428.57%   1428.57%
                               8            2   2857.14%   4285.71%
                              10            2   2857.14%   7142.86%
                              12            0      0.00%   7142.86%
                              14            0      0.00%   7142.86%
                              16            0      0.00%   7142.86%
                              18            0      0.00%   7142.86%
                              20            1   1428.57%   8571.43%
                              22            0      0.00%   8571.43%
                              24            0      0.00%   8571.43%
                              26            0      0.00%   8571.43%
                              28            0      0.00%   8571.43%
                              30            0      0.00%   8571.43%
                              32            0      0.00%   8571.43%
                              34            0      0.00%   8571.43%
                              36            0      0.00%   8571.43%
                              38            0      0.00%   8571.43%
                              40            0      0.00%   8571.43%
                              42            0      0.00%   8571.43%
                              44            0      0.00%   8571.43%
                              46            0      0.00%   8571.43%
                              48            0      0.00%   8571.43%
                              50            0      0.00%   8571.43%
                              52            0      0.00%   8571.43%
                              54            0      0.00%   8571.43%
                              56            0      0.00%   8571.43%
                              58            0      0.00%   8571.43%
                              60            0      0.00%   8571.43%
                              62            0      0.00%   8571.43%
                              64            0      0.00%   8571.43%
                              66            0      0.00%   8571.43%
                              68            0      0.00%   8571.43%
                              70            0      0.00%   8571.43%
                              72            0      0.00%   8571.43%
                              74            0      0.00%   8571.43%
                              76            0      0.00%   8571.43%
                              78            0      0.00%   8571.43%
                              80            0      0.00%   8571.43%
                              82            0      0.00%   8571.43%
                              84            0      0.00%   8571.43%
                              86            0      0.00%   8571.43%
                              88            0      0.00%   8571.43%
                              90            0      0.00%   8571.43%
                              92            0      0.00%   8571.43%
                              94            0      0.00%   8571.43%
                              96            0      0.00%   8571.43%
                              98            0      0.00%   8571.43%
cpu.IQ:residence:FloatCmp.overflows                 1                      
cpu.IQ:residence:FloatCmp.max_value               147                      
cpu.IQ:residence:FloatCmp.end_dist

cpu.IQ:residence:FloatCvt.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatCvt.samples                  93                      
cpu.IQ:residence:FloatCvt.min_value                 1                      
                               0           15   1612.90%   1612.90%
                               2            7    752.69%   2365.59%
                               4           17   1827.96%   4193.55%
                               6           11   1182.80%   5376.34%
                               8           12   1290.32%   6666.67%
                              10            8    860.22%   7526.88%
                              12            9    967.74%   8494.62%
                              14            4    430.11%   8924.73%
                              16            2    215.05%   9139.78%
                              18            2    215.05%   9354.84%
                              20            2    215.05%   9569.89%
                              22            1    107.53%   9677.42%
                              24            1    107.53%   9784.95%
                              26            0      0.00%   9784.95%
                              28            0      0.00%   9784.95%
                              30            1    107.53%   9892.47%
                              32            0      0.00%   9892.47%
                              34            0      0.00%   9892.47%
                              36            1    107.53%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.IQ:residence:FloatCvt.max_value                37                      
cpu.IQ:residence:FloatCvt.end_dist

cpu.IQ:residence:FloatMult.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:FloatMult.samples                  6                      
cpu.IQ:residence:FloatMult.min_value                6                      
                               0            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               6            2   3333.33%   3333.33%
                               8            2   3333.33%   6666.67%
                              10            0      0.00%   6666.67%
                              12            0      0.00%   6666.67%
                              14            0      0.00%   6666.67%
                              16            1   1666.67%   8333.33%
                              18            0      0.00%   8333.33%
                              20            0      0.00%   8333.33%
                              22            0      0.00%   8333.33%
                              24            0      0.00%   8333.33%
                              26            0      0.00%   8333.33%
                              28            0      0.00%   8333.33%
                              30            0      0.00%   8333.33%
                              32            0      0.00%   8333.33%
                              34            0      0.00%   8333.33%
                              36            0      0.00%   8333.33%
                              38            0      0.00%   8333.33%
                              40            0      0.00%   8333.33%
                              42            0      0.00%   8333.33%
                              44            0      0.00%   8333.33%
                              46            0      0.00%   8333.33%
                              48            0      0.00%   8333.33%
                              50            0      0.00%   8333.33%
                              52            0      0.00%   8333.33%
                              54            0      0.00%   8333.33%
                              56            0      0.00%   8333.33%
                              58            0      0.00%   8333.33%
                              60            0      0.00%   8333.33%
                              62            0      0.00%   8333.33%
                              64            0      0.00%   8333.33%
                              66            0      0.00%   8333.33%
                              68            0      0.00%   8333.33%
                              70            0      0.00%   8333.33%
                              72            0      0.00%   8333.33%
                              74            0      0.00%   8333.33%
                              76            0      0.00%   8333.33%
                              78            0      0.00%   8333.33%
                              80            0      0.00%   8333.33%
                              82            0      0.00%   8333.33%
                              84            0      0.00%   8333.33%
                              86            0      0.00%   8333.33%
                              88            0      0.00%   8333.33%
                              90            0      0.00%   8333.33%
                              92            0      0.00%   8333.33%
                              94            0      0.00%   8333.33%
                              96            0      0.00%   8333.33%
                              98            0      0.00%   8333.33%
cpu.IQ:residence:FloatMult.overflows                1                      
cpu.IQ:residence:FloatMult.max_value              144                      
cpu.IQ:residence:FloatMult.end_dist

cpu.IQ:residence:FloatDiv.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatDiv.samples                  11                      
cpu.IQ:residence:FloatDiv.min_value                 2                      
                               0            0      0.00%      0.00%
                               2            2   1818.18%   1818.18%
                               4            2   1818.18%   3636.36%
                               6            2   1818.18%   5454.55%
                               8            1    909.09%   6363.64%
                              10            2   1818.18%   8181.82%
                              12            0      0.00%   8181.82%
                              14            0      0.00%   8181.82%
                              16            1    909.09%   9090.91%
                              18            0      0.00%   9090.91%
                              20            0      0.00%   9090.91%
                              22            1    909.09%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.IQ:residence:FloatDiv.max_value                23                      
cpu.IQ:residence:FloatDiv.end_dist

cpu.IQ:residence:FloatSqrt.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:FloatSqrt.samples                  0                      
cpu.IQ:residence:FloatSqrt.min_value                0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:FloatSqrt.max_value                0                      
cpu.IQ:residence:FloatSqrt.end_dist

cpu.IQ:residence:MemRead.start_dist                            # cycles from dispatch to issue
cpu.IQ:residence:MemRead.samples              1546417                      
cpu.IQ:residence:MemRead.min_value                  1                      
                               0        98694    638.21%    638.21%
                               2       276593   1788.61%   2426.82%
                               4       228259   1476.05%   3902.87%
                               6       276502   1788.02%   5690.88%
                               8       250384   1619.12%   7310.01%
                              10       190184   1229.84%   8539.84%
                              12        96022    620.93%   9160.78%
                              14        52884    341.98%   9502.75%
                              16        28672    185.41%   9688.16%
                              18        14590     94.35%   9782.51%
                              20         7924     51.24%   9833.75%
                              22         3931     25.42%   9859.17%
                              24         1607     10.39%   9869.56%
                              26          812      5.25%   9874.81%
                              28          563      3.64%   9878.45%
                              30          411      2.66%   9881.11%
                              32          307      1.99%   9883.10%
                              34          322      2.08%   9885.18%
                              36          303      1.96%   9887.14%
                              38          285      1.84%   9888.98%
                              40          318      2.06%   9891.04%
                              42          563      3.64%   9894.68%
                              44          371      2.40%   9897.08%
                              46          164      1.06%   9898.14%
                              48          158      1.02%   9899.16%
                              50          148      0.96%   9900.12%
                              52          125      0.81%   9900.93%
                              54          166      1.07%   9902.00%
                              56          159      1.03%   9903.03%
                              58          138      0.89%   9903.92%
                              60          189      1.22%   9905.14%
                              62          191      1.24%   9906.38%
                              64          197      1.27%   9907.65%
                              66          169      1.09%   9908.74%
                              68           98      0.63%   9909.38%
                              70          123      0.80%   9910.17%
                              72          114      0.74%   9910.91%
                              74          124      0.80%   9911.71%
                              76          116      0.75%   9912.46%
                              78          116      0.75%   9913.21%
                              80          116      0.75%   9913.96%
                              82          116      0.75%   9914.71%
                              84          117      0.76%   9915.47%
                              86          106      0.69%   9916.15%
                              88          175      1.13%   9917.29%
                              90          161      1.04%   9918.33%
                              92          181      1.17%   9919.50%
                              94          208      1.35%   9920.84%
                              96          229      1.48%   9922.32%
                              98          243      1.57%   9923.90%
cpu.IQ:residence:MemRead.overflows              11769                      
cpu.IQ:residence:MemRead.max_value               1021                      
cpu.IQ:residence:MemRead.end_dist

cpu.IQ:residence:MemWrite.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:MemWrite.samples              700874                      
cpu.IQ:residence:MemWrite.min_value                 1                      
                               0        41284    589.04%    589.04%
                               2       134561   1919.90%   2508.94%
                               4       108363   1546.11%   4055.05%
                               6       118569   1691.73%   5746.78%
                               8       115157   1643.05%   7389.83%
                              10        96827   1381.52%   8771.35%
                              12        42332    603.99%   9375.34%
                              14        17788    253.80%   9629.13%
                              16         9804    139.88%   9769.02%
                              18         4779     68.19%   9837.20%
                              20         1946     27.77%   9864.97%
                              22         1139     16.25%   9881.22%
                              24          691      9.86%   9891.08%
                              26          343      4.89%   9895.97%
                              28          266      3.80%   9899.77%
                              30          188      2.68%   9902.45%
                              32          127      1.81%   9904.26%
                              34           96      1.37%   9905.63%
                              36           81      1.16%   9906.79%
                              38           84      1.20%   9907.99%
                              40           65      0.93%   9908.91%
                              42           55      0.78%   9909.70%
                              44           40      0.57%   9910.27%
                              46           56      0.80%   9911.07%
                              48           66      0.94%   9912.01%
                              50           83      1.18%   9913.19%
                              52           44      0.63%   9913.82%
                              54           65      0.93%   9914.75%
                              56           77      1.10%   9915.85%
                              58           44      0.63%   9916.48%
                              60           67      0.96%   9917.43%
                              62           73      1.04%   9918.47%
                              64           53      0.76%   9919.23%
                              66           64      0.91%   9920.14%
                              68           46      0.66%   9920.80%
                              70           50      0.71%   9921.51%
                              72           45      0.64%   9922.15%
                              74           56      0.80%   9922.95%
                              76           43      0.61%   9923.57%
                              78           45      0.64%   9924.21%
                              80           48      0.68%   9924.89%
                              82           55      0.78%   9925.68%
                              84           88      1.26%   9926.93%
                              86           91      1.30%   9928.23%
                              88          117      1.67%   9929.90%
                              90          109      1.56%   9931.46%
                              92          107      1.53%   9932.98%
                              94          103      1.47%   9934.45%
                              96          139      1.98%   9936.44%
                              98          157      2.24%   9938.68%
cpu.IQ:residence:MemWrite.overflows              4298                      
cpu.IQ:residence:MemWrite.max_value               408                      
cpu.IQ:residence:MemWrite.end_dist

cpu.IQ:residence:IprAccess.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:IprAccess.samples                  0                      
cpu.IQ:residence:IprAccess.min_value                0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:IprAccess.max_value                0                      
cpu.IQ:residence:IprAccess.end_dist

cpu.IQ:residence:InstPrefetch.start_dist                       # cycles from dispatch to issue
cpu.IQ:residence:InstPrefetch.samples               0                      
cpu.IQ:residence:InstPrefetch.min_value             0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:InstPrefetch.max_value             0                      
cpu.IQ:residence:InstPrefetch.end_dist

cpu.ISSUE:(null)_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:(null)_delay.samples                      0                      
cpu.ISSUE:(null)_delay.min_value                    0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:(null)_delay.max_value                    0                      
cpu.ISSUE:(null)_delay.end_dist

cpu.ISSUE:IntAlu_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:IntAlu_delay.samples                1861890                      
cpu.ISSUE:IntAlu_delay.min_value                    0                      
                               0      1354816   7276.56%   7276.56%
                               2       191199   1026.91%   8303.47%
                               4       123499    663.30%   8966.77%
                               6        93167    500.39%   9467.16%
                               8        67420    362.11%   9829.26%
                              10        30662    164.68%   9993.95%
                              12         1127      6.05%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:IntAlu_delay.max_value                   13                      
cpu.ISSUE:IntAlu_delay.end_dist

cpu.ISSUE:IntMult_delay.start_dist                             # cycles from operands ready to issue
cpu.ISSUE:IntMult_delay.samples                   705                      
cpu.ISSUE:IntMult_delay.min_value                   0                      
                               0          600   8510.64%   8510.64%
                               2           68    964.54%   9475.18%
                               4           29    411.35%   9886.52%
                               6            7     99.29%   9985.82%
                               8            1     14.18%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:IntMult_delay.max_value                   8                      
cpu.ISSUE:IntMult_delay.end_dist

cpu.ISSUE:IntDiv_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:IntDiv_delay.samples                      0                      
cpu.ISSUE:IntDiv_delay.min_value                    0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:IntDiv_delay.max_value                    0                      
cpu.ISSUE:IntDiv_delay.end_dist

cpu.ISSUE:FloatAdd_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatAdd_delay.samples                  110                      
cpu.ISSUE:FloatAdd_delay.min_value                  0                      
                               0          102   9272.73%   9272.73%
                               2            7    636.36%   9909.09%
                               4            1     90.91%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatAdd_delay.max_value                  4                      
cpu.ISSUE:FloatAdd_delay.end_dist

cpu.ISSUE:FloatCmp_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatCmp_delay.samples                    7                      
cpu.ISSUE:FloatCmp_delay.min_value                  0                      
                               0            7  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatCmp_delay.max_value                  0                      
cpu.ISSUE:FloatCmp_delay.end_dist

cpu.ISSUE:FloatCvt_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatCvt_delay.samples                   93                      
cpu.ISSUE:FloatCvt_delay.min_value                  0                      
                               0           81   8709.68%   8709.68%
                               2            4    430.11%   9139.78%
                               4            3    322.58%   9462.37%
                               6            3    322.58%   9784.95%
                               8            2    215.05%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatCvt_delay.max_value                  8                      
cpu.ISSUE:FloatCvt_delay.end_dist

cpu.ISSUE:FloatMult_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:FloatMult_delay.samples                   6                      
cpu.ISSUE:FloatMult_delay.min_value                 0                      
                               0            6  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatMult_delay.max_value                 0                      
cpu.ISSUE:FloatMult_delay.end_dist

cpu.ISSUE:FloatDiv_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatDiv_delay.samples                   11                      
cpu.ISSUE:FloatDiv_delay.min_value                  0                      
                               0           11  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatDiv_delay.max_value                  0                      
cpu.ISSUE:FloatDiv_delay.end_dist

cpu.ISSUE:FloatSqrt_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:FloatSqrt_delay.samples                   0                      
cpu.ISSUE:FloatSqrt_delay.min_value                 0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:FloatSqrt_delay.max_value                 0                      
cpu.ISSUE:FloatSqrt_delay.end_dist

cpu.ISSUE:MemRead_delay.start_dist                             # cycles from operands ready to issue
cpu.ISSUE:MemRead_delay.samples               1546417                      
cpu.ISSUE:MemRead_delay.min_value                   0                      
                               0      1187264   7677.52%   7677.52%
                               2       144883    936.89%   8614.41%
                               4        82697    534.77%   9149.18%
                               6        61913    400.36%   9549.54%
                               8        45565    294.65%   9844.19%
                              10        19751    127.72%   9971.91%
                              12          698      4.51%   9976.42%
                              14           39      0.25%   9976.68%
                              16           39      0.25%   9976.93%
                              18           31      0.20%   9977.13%
                              20           26      0.17%   9977.30%
                              22           47      0.30%   9977.60%
                              24           43      0.28%   9977.88%
                              26           31      0.20%   9978.08%
                              28           14      0.09%   9978.17%
                              30           14      0.09%   9978.26%
                              32           34      0.22%   9978.48%
                              34           13      0.08%   9978.56%
                              36           15      0.10%   9978.66%
                              38           22      0.14%   9978.80%
                              40           43      0.28%   9979.08%
                              42           21      0.14%   9979.22%
                              44           33      0.21%   9979.43%
                              46           40      0.26%   9979.69%
                              48           48      0.31%   9980.00%
                              50           61      0.39%   9980.39%
                              52           96      0.62%   9981.01%
                              54           69      0.45%   9981.46%
                              56           65      0.42%   9981.88%
                              58           43      0.28%   9982.16%
                              60           31      0.20%   9982.36%
                              62            9      0.06%   9982.42%
                              64           14      0.09%   9982.51%
                              66           13      0.08%   9982.59%
                              68           21      0.14%   9982.73%
                              70           28      0.18%   9982.91%
                              72           29      0.19%   9983.10%
                              74           24      0.16%   9983.25%
                              76           16      0.10%   9983.36%
                              78           21      0.14%   9983.49%
                              80           49      0.32%   9983.81%
                              82           27      0.17%   9983.98%
                              84           40      0.26%   9984.24%
                              86           70      0.45%   9984.69%
                              88           96      0.62%   9985.31%
                              90           97      0.63%   9985.94%
                              92           73      0.47%   9986.41%
                              94          118      0.76%   9987.18%
                              96          141      0.91%   9988.09%
                              98          162      1.05%   9989.14%
cpu.ISSUE:MemRead_delay.overflows                1680                      
cpu.ISSUE:MemRead_delay.max_value                 259                      
cpu.ISSUE:MemRead_delay.end_dist

cpu.ISSUE:MemWrite_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:MemWrite_delay.samples               700874                      
cpu.ISSUE:MemWrite_delay.min_value                  0                      
                               0       539596   7698.90%   7698.90%
                               2        74258   1059.51%   8758.41%
                               4        40481    577.58%   9335.99%
                               6        23243    331.63%   9667.62%
                               8        14504    206.94%   9874.56%
                              10         5968     85.15%   9959.71%
                              12          217      3.10%   9962.80%
                              14            4      0.06%   9962.86%
                              16           12      0.17%   9963.03%
                              18            4      0.06%   9963.09%
                              20           10      0.14%   9963.23%
                              22            8      0.11%   9963.35%
                              24           12      0.17%   9963.52%
                              26            8      0.11%   9963.63%
                              28            8      0.11%   9963.75%
                              30            7      0.10%   9963.85%
                              32            3      0.04%   9963.89%
                              34           10      0.14%   9964.03%
                              36            9      0.13%   9964.16%
                              38            7      0.10%   9964.26%
                              40           10      0.14%   9964.40%
                              42           19      0.27%   9964.67%
                              44           17      0.24%   9964.92%
                              46           24      0.34%   9965.26%
                              48           40      0.57%   9965.83%
                              50           56      0.80%   9966.63%
                              52           27      0.39%   9967.01%
                              54           27      0.39%   9967.40%
                              56           18      0.26%   9967.65%
                              58           10      0.14%   9967.80%
                              60            6      0.09%   9967.88%
                              62            8      0.11%   9968.00%
                              64           14      0.20%   9968.20%
                              66           11      0.16%   9968.35%
                              68           15      0.21%   9968.57%
                              70            8      0.11%   9968.68%
                              72           16      0.23%   9968.91%
                              74            9      0.13%   9969.04%
                              76           23      0.33%   9969.37%
                              78           32      0.46%   9969.82%
                              80           41      0.58%   9970.41%
                              82           31      0.44%   9970.85%
                              84           50      0.71%   9971.56%
                              86           55      0.78%   9972.35%
                              88           69      0.98%   9973.33%
                              90          118      1.68%   9975.02%
                              92           92      1.31%   9976.33%
                              94          153      2.18%   9978.51%
                              96          140      2.00%   9980.51%
                              98          168      2.40%   9982.91%
cpu.ISSUE:MemWrite_delay.overflows               1198                      
cpu.ISSUE:MemWrite_delay.max_value                126                      
cpu.ISSUE:MemWrite_delay.end_dist

cpu.ISSUE:IprAccess_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:IprAccess_delay.samples                   0                      
cpu.ISSUE:IprAccess_delay.min_value                 0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:IprAccess_delay.max_value                 0                      
cpu.ISSUE:IprAccess_delay.end_dist

cpu.ISSUE:InstPrefetch_delay.start_dist                        # cycles from operands ready to issue
cpu.ISSUE:InstPrefetch_delay.samples                0                      
cpu.ISSUE:InstPrefetch_delay.min_value              0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:InstPrefetch_delay.max_value              0                      
cpu.ISSUE:InstPrefetch_delay.end_dist

cpu.ISSUE:FU_type_0                           1276285                       # Type of FU issued
cpu.ISSUE:FU_type_0.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu       920733     72.14%            # Type of FU issued
                         IntMult            0      0.00%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd            0      0.00%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       274604     21.52%            # Type of FU issued
                        MemWrite        80948      6.34%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_0.end_dist
cpu.ISSUE:FU_type_1                            486981                       # Type of FU issued
cpu.ISSUE:FU_type_1.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu       361674     74.27%            # Type of FU issued
                         IntMult          479      0.10%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd           41      0.01%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt           50      0.01%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv           11      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead        90642     18.61%            # Type of FU issued
                        MemWrite        34084      7.00%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_1.end_dist
cpu.ISSUE:FU_type_2                           1423116                       # Type of FU issued
cpu.ISSUE:FU_type_2.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu      1039426     73.04%            # Type of FU issued
                         IntMult            2      0.00%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd           20      0.00%            # Type of FU issued
                        FloatCmp            4      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            3      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       268407     18.86%            # Type of FU issued
                        MemWrite       115254      8.10%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_2.end_dist
cpu.ISSUE:FU_type_3                            900680                       # Type of FU issued
cpu.ISSUE:FU_type_3.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu       673650     74.79%            # Type of FU issued
                         IntMult          224      0.02%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd           49      0.01%            # Type of FU issued
                        FloatCmp            3      0.00%            # Type of FU issued
                        FloatCvt           43      0.00%            # Type of FU issued
                       FloatMult            3      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       134409     14.92%            # Type of FU issued
                        MemWrite        92299     10.25%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_3.end_dist
cpu.ISSUE:FU_type                             4087062                       # Type of FU issued
cpu.ISSUE:FU_type.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu      2995483     73.29%            # Type of FU issued
                         IntMult          705      0.02%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd          110      0.00%            # Type of FU issued
                        FloatCmp            7      0.00%            # Type of FU issued
                        FloatCvt           93      0.00%            # Type of FU issued
                       FloatMult            6      0.00%            # Type of FU issued
                        FloatDiv           11      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       768062     18.79%            # Type of FU issued
                        MemWrite       322585      7.89%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type.end_dist
cpu.ISSUE:IQ_0:fu_full.start_dist
                          (null)            0      0.00%           
                          IntAlu      1645793     93.15%           
                         IntMult           12      0.00%           
                          IntDiv            0      0.00%           
                        FloatAdd            0      0.00%           
                        FloatCmp            0      0.00%           
                        FloatCvt            0      0.00%           
                       FloatMult            0      0.00%           
                        FloatDiv            0      0.00%           
                       FloatSqrt            0      0.00%           
                         MemRead       110821      6.27%           
                        MemWrite        10286      0.58%           
                       IprAccess            0      0.00%           
                    InstPrefetch            0      0.00%           
cpu.ISSUE:IQ_0:fu_full.end_dist
cpu.ISSUE:MSIPC                              0.398910                       # Misspec issue rate
cpu.ISSUE:MSIPC_0                            0.124312                       # Misspec issue rate
cpu.ISSUE:MSIPC_1                            0.100359                       # Misspec issue rate
cpu.ISSUE:MSIPC_2                            0.059653                       # Misspec issue rate
cpu.ISSUE:MSIPC_3                            0.114586                       # Misspec issue rate
cpu.ISSUE:addr_loads                             1225                       # number of invalid-address loads
cpu.ISSUE:addr_loads_0                             53                       # number of invalid-address loads
cpu.ISSUE:addr_loads_1                            619                       # number of invalid-address loads
cpu.ISSUE:addr_loads_2                             15                       # number of invalid-address loads
cpu.ISSUE:addr_loads_3                            538                       # number of invalid-address loads
cpu.ISSUE:addr_swpfs                                0                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_0                              0                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_1                              0                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_2                              0                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_3                              0                       # number of invalid-address SW prefetches
cpu.ISSUE:branches                             449636                       # Number of branches issued
cpu.ISSUE:branches_0                           149903                       # Number of branches issued
cpu.ISSUE:branches_1                            56698                       # Number of branches issued
cpu.ISSUE:branches_2                           132014                       # Number of branches issued
cpu.ISSUE:branches_3                           111021                       # Number of branches issued
cpu.ISSUE:count                               2990188                       # number of insts issued
cpu.ISSUE:count_0                              920168                       # number of insts issued
cpu.ISSUE:count_1                              361465                       # number of insts issued
cpu.ISSUE:count_2                             1039439                       # number of insts issued
cpu.ISSUE:count_3                              669116                       # number of insts issued
cpu.ISSUE:fu_busy_cnt                         1766912                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_0                        494516                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_1                        295597                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_2                        506265                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_3                        470534                       # FU busy when requested
cpu.ISSUE:fu_busy_rate                       0.590903                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_0                     0.537419                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_1                     0.817775                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_2                     0.487056                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_3                     0.703217                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_full.start_dist
                          (null)            0      0.00%            # attempts to use FU when none available
                          IntAlu      1645793     93.15%            # attempts to use FU when none available
                         IntMult           12      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead       110821      6.27%            # attempts to use FU when none available
                        MemWrite        10286      0.58%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
cpu.ISSUE:fu_full.end_dist
cpu.ISSUE:issued_per_cycle                     639333                       # Number of insts issued each cycle
cpu.ISSUE:issued_per_cycle.start_dist
                               0        24454      3.82%            # Number of insts issued each cycle
                               1        16750      2.62%            # Number of insts issued each cycle
                               2        18869      2.95%            # Number of insts issued each cycle
                               3        20612      3.22%            # Number of insts issued each cycle
                               4        22530      3.52%            # Number of insts issued each cycle
                               5        24149      3.78%            # Number of insts issued each cycle
                               6        94816     14.83%            # Number of insts issued each cycle
                               7       123196     19.27%            # Number of insts issued each cycle
                               8       293957     45.98%            # Number of insts issued each cycle
cpu.ISSUE:issued_per_cycle.end_dist
cpu.ISSUE:loads                                778355                       # number of load insts issued
cpu.ISSUE:loads_0                              277640                       # number of load insts issued
cpu.ISSUE:loads_1                               92966                       # number of load insts issued
cpu.ISSUE:loads_2                              270115                       # number of load insts issued
cpu.ISSUE:loads_3                              137634                       # number of load insts issued
cpu.ISSUE:lsq_inv_rate                              0                       # Early LSQ issues per cycle
cpu.ISSUE:lsq_invert                                0                       # Number of times LSQ instruction issued early
cpu.ISSUE:misspec_cnt                          263730                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_0                         82186                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_1                         66350                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_2                         39438                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_3                         75756                       # Number of misspeculated insts issued
cpu.ISSUE:nop                                  273236                       # number of nop insts issued
cpu.ISSUE:nop_0                                 28331                       # number of nop insts issued
cpu.ISSUE:nop_1                                 68936                       # number of nop insts issued
cpu.ISSUE:nop_2                                 73776                       # number of nop insts issued
cpu.ISSUE:nop_3                                102193                       # number of nop insts issued
cpu.ISSUE:op_count                            4110113                       # number of insts issued
cpu.ISSUE:op_count_0                          1285046                       # number of insts issued
cpu.ISSUE:op_count_1                           492779                       # number of insts issued
cpu.ISSUE:op_count_2                          1426119                       # number of insts issued
cpu.ISSUE:op_count_3                           906169                       # number of insts issued
cpu.ISSUE:op_rate                            6.216838                       # Operation issue rate
cpu.ISSUE:op_rate_0                          1.943723                       # Operation issue rate
cpu.ISSUE:op_rate_1                          0.745363                       # Operation issue rate
cpu.ISSUE:op_rate_2                          2.157106                       # Operation issue rate
cpu.ISSUE:op_rate_3                          1.370645                       # Operation issue rate
cpu.ISSUE:rate                               4.522872                       # Inst issue rate
cpu.ISSUE:rate_0                             1.391819                       # Inst issue rate
cpu.ISSUE:rate_1                             0.546741                       # Inst issue rate
cpu.ISSUE:rate_2                             1.572225                       # Inst issue rate
cpu.ISSUE:rate_3                             1.012085                       # Inst issue rate
cpu.ISSUE:refs                                1133593                       # number of memory reference insts issued
cpu.ISSUE:refs_0                               370867                       # number of memory reference insts issued
cpu.ISSUE:refs_1                               134978                       # number of memory reference insts issued
cpu.ISSUE:refs_2                               389860                       # number of memory reference insts issued
cpu.ISSUE:refs_3                               237888                       # number of memory reference insts issued
cpu.ISSUE:stores                               355238                       # Number of stores issued
cpu.ISSUE:stores_0                              93227                       # Number of stores issued
cpu.ISSUE:stores_1                              42012                       # Number of stores issued
cpu.ISSUE:stores_2                             119745                       # Number of stores issued
cpu.ISSUE:stores_3                             100254                       # Number of stores issued
cpu.ISSUE:swp                                    6227                       # number of swp insts issued
cpu.ISSUE:swp_0                                   565                       # number of swp insts issued
cpu.ISSUE:swp_1                                   790                       # number of swp insts issued
cpu.ISSUE:swp_2                                    16                       # number of swp insts issued
cpu.ISSUE:swp_3                                  4856                       # number of swp insts issued
cpu.ISSUE:unissued_cause.start_dist
                          (null)            0      0.00%            # Reason ready instruction not issued
                          IntAlu      1645793     92.34%            # Reason ready instruction not issued
                         IntMult           12      0.00%            # Reason ready instruction not issued
                          IntDiv            0      0.00%            # Reason ready instruction not issued
                        FloatAdd            0      0.00%            # Reason ready instruction not issued
                        FloatCmp            0      0.00%            # Reason ready instruction not issued
                        FloatCvt            0      0.00%            # Reason ready instruction not issued
                       FloatMult            0      0.00%            # Reason ready instruction not issued
                        FloatDiv            0      0.00%            # Reason ready instruction not issued
                       FloatSqrt            0      0.00%            # Reason ready instruction not issued
                         MemRead       110821      6.22%            # Reason ready instruction not issued
                        MemWrite            0      0.00%            # Reason ready instruction not issued
                       IprAccess            0      0.00%            # Reason ready instruction not issued
                    InstPrefetch            0      0.00%            # Reason ready instruction not issued
                  DCache_Blocked        25767      1.45%            # Reason ready instruction not issued
                       Too_Young            0      0.00%            # Reason ready instruction not issued
cpu.ISSUE:unissued_cause.end_dist
cpu.LSQ:RQ:rdy_inst                           1792321                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_0                          547571                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_1                          235174                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_2                          565601                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_3                          443975                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_dist_0_mean              0.828240                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_0_stdev             1.577086                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_0_TOT       661126                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_1_mean              0.355717                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_1_stdev             1.285160                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_1_TOT       661126                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_2_mean              0.855512                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_2_stdev             1.461385                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_2_TOT       661126                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_3_mean              0.671544                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_3_stdev             1.892960                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_3_TOT       661126                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_rate                          2.711013                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_0                        0.828240                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_1                        0.355717                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_2                        0.855512                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_3                        0.671544                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_x_count                        1114883                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_0                       364634                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_1                       130863                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_2                       386816                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_3                       232570                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_max                               23                       # largest number of insts that become ready
cpu.LSQ:RQ:rdy_x_rate                        1.686340                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_0                      0.551535                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_1                      0.197940                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_2                      0.585087                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_3                      0.351779                       # number of insts that become ready per cycle
cpu.LSQ:avg_residency                        3.878401                       # Average IQ residency
cpu.LSQ:avg_residency_0                      4.095661                       # Average IQ residency
cpu.LSQ:avg_residency_1                      5.804180                       # Average IQ residency
cpu.LSQ:avg_residency_2                      3.330010                       # Average IQ residency
cpu.LSQ:avg_residency_3                      3.391195                       # Average IQ residency
cpu.LSQ:blocked_loads                          330802                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_0                        117019                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_1                         43155                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_2                         99371                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_3                         71257                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:cum_num_insts                        11597149                       # Total occupancy
cpu.LSQ:cum_num_insts_0                       3768696                       # Total occupancy
cpu.LSQ:cum_num_insts_1                       2098008                       # Total occupancy
cpu.LSQ:cum_num_insts_2                       3461342                       # Total occupancy
cpu.LSQ:cum_num_insts_3                       2269103                       # Total occupancy
cpu.LSQ:current_count                              28                       # Occupancy this cycle
cpu.LSQ:empty_count                              8783                       # Number of empty cycles
cpu.LSQ:empty_rate                           1.328491                       # Fraction of cycles empty
cpu.LSQ:forw_loads                                 47                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_0                               17                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_1                               20                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_2                                0                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_3                               10                       # number of loads forwarded via LSQ
cpu.LSQ:full_count                                  0                       # Number of full cycles
cpu.LSQ:full_rate                                   0                       # Fraction of cycles full
cpu.LSQ:occ_dist_0.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_0.samples                     661126                      
cpu.LSQ:occ_dist_0.min_value                        0                      
                               0       152527              2307.08%
                               2        74124              3428.26%
                               4       111842              5119.95%
                               6       106627              6732.76%
                               8        88346              8069.05%
                              10        60734              8987.70%
                              12        31355              9461.96%
                              14        17603              9728.22%
                              16         9970              9879.02%
                              18         3597              9933.43%
                              20         1869              9961.70%
                              22          976              9976.46%
                              24          658              9986.42%
                              26          327              9991.36%
                              28          320              9996.20%
                              30           51              9996.97%
                              32          200             10000.00%
cpu.LSQ:occ_dist_0.max_value                       32                      
cpu.LSQ:occ_dist_0.end_dist

cpu.LSQ:occ_dist_1.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_1.samples                     661126                      
cpu.LSQ:occ_dist_1.min_value                        0                      
                               0       330128              4993.42%
                               2        69143              6039.26%
                               4       101104              7568.53%
                               6        71816              8654.80%
                               8        38003              9229.62%
                              10        25869              9620.90%
                              12        10155              9774.51%
                              14         7392              9886.32%
                              16         3682              9942.01%
                              18         1607              9966.32%
                              20         1332              9986.46%
                              22          442              9993.15%
                              24          321              9998.00%
                              26           21              9998.32%
                              28          111             10000.00%
                              30            0             10000.00%
                              32            0             10000.00%
cpu.LSQ:occ_dist_1.max_value                       29                      
cpu.LSQ:occ_dist_1.end_dist

cpu.LSQ:occ_dist_2.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_2.samples                     661126                      
cpu.LSQ:occ_dist_2.min_value                        0                      
                               0       123516              1868.27%
                               2        92154              3262.16%
                               4       145593              5464.36%
                               6       134126              7493.11%
                               8        88892              8837.66%
                              10        41642              9467.53%
                              12        22482              9807.59%
                              14         8442              9935.28%
                              16         2457              9972.44%
                              18          677              9982.68%
                              20          462              9989.67%
                              22          240              9993.30%
                              24          271              9997.40%
                              26          139              9999.50%
                              28           25              9999.88%
                              30            2              9999.91%
                              32            6             10000.00%
cpu.LSQ:occ_dist_2.max_value                       32                      
cpu.LSQ:occ_dist_2.end_dist

cpu.LSQ:occ_dist_3.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_3.samples                     661126                      
cpu.LSQ:occ_dist_3.min_value                        0                      
                               0       327493              4953.56%
                               2        91736              6341.14%
                               4        70017              7400.19%
                               6        50174              8159.11%
                               8        46685              8865.25%
                              10        37154              9427.23%
                              12        17400              9690.42%
                              14         9831              9839.12%
                              16         4933              9913.74%
                              18         2486              9951.34%
                              20         1274              9970.61%
                              22          903              9984.27%
                              24          494              9991.74%
                              26          205              9994.84%
                              28          158              9997.23%
                              30           75              9998.37%
                              32          108             10000.00%
cpu.LSQ:occ_dist_3.max_value                       32                      
cpu.LSQ:occ_dist_3.end_dist

cpu.LSQ:occ_rate                            17.541511                       # Average occupancy
cpu.LSQ:occ_rate_0                           5.700420                       # Average occupancy
cpu.LSQ:occ_rate_1                           3.173386                       # Average occupancy
cpu.LSQ:occ_rate_2                           5.235525                       # Average occupancy
cpu.LSQ:occ_rate_3                           3.432179                       # Average occupancy
cpu.LSQ:peak_occupancy                            125                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_0                           32                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_1                           29                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_2                           32                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_3                           32                       # Peak IQ occupancy
cpu.REG:fp:full                                     0                       # number of cycles where there were no FP registers
cpu.REG:fp:occ                                  13755                       # Cumulative count of FP register usage
cpu.REG:fp:occ_0                                    0                       # Cumulative count of FP register usage
cpu.REG:fp:occ_1                                 8117                       # Cumulative count of FP register usage
cpu.REG:fp:occ_2                                 1399                       # Cumulative count of FP register usage
cpu.REG:fp:occ_3                                 4239                       # Cumulative count of FP register usage
cpu.REG:fp:occ_rate                                 0                       # Average FP register usage
cpu.REG:fp:occ_rate_0                               0                       # Average FP register usage
cpu.REG:fp:occ_rate_1                               0                       # Average FP register usage
cpu.REG:fp:occ_rate_2                               0                       # Average FP register usage
cpu.REG:fp:occ_rate_3                               0                       # Average FP register usage
cpu.REG:int:full                                    0                       # number of cycles where there were no INT registers
cpu.REG:int:occ                              47649387                       # Cumulative count of INT register usage
cpu.REG:int:occ_0                            13400712                       # Cumulative count of INT register usage
cpu.REG:int:occ_1                             8397783                       # Cumulative count of INT register usage
cpu.REG:int:occ_2                            17286686                       # Cumulative count of INT register usage
cpu.REG:int:occ_3                             8564206                       # Cumulative count of INT register usage
cpu.REG:int:occ_rate                               72                       # Average INT register usage
cpu.REG:int:occ_rate_0                             20                       # Average INT register usage
cpu.REG:int:occ_rate_1                             13                       # Average INT register usage
cpu.REG:int:occ_rate_2                             26                       # Average INT register usage
cpu.REG:int:occ_rate_3                             13                       # Average INT register usage
cpu.ROB:cap_events                                  0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_0                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_1                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_2                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_3                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_inst                                    0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_0                                  0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_1                                  0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_2                                  0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_3                                  0                       # number of instructions held up by ROB cap
cpu.ROB:current_count                             109                       # Current ROB occupancy
cpu.ROB:full_count                              25914                       # number of cycles where ROB was full
cpu.ROB:full_rate                            0.039197                       # ROB full per cycle
cpu.ROB:occ_dist_0.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_0.samples                     661126                      
cpu.ROB:occ_dist_0.min_value                        0                      
                               0        86828              1313.34%
                               2         2652              1353.45%
                               4         5495              1436.56%
                               6         8877              1570.84%
                               8        18320              1847.94%
                              10        11333              2019.36%
                              12        13551              2224.33%
                              14        18101              2498.12%
                              16        28009              2921.77%
                              18        26539              3323.19%
                              20        35065              3853.58%
                              22        40512              4466.35%
                              24        45167              5149.53%
                              26        36024              5694.42%
                              28        35658              6233.77%
                              30        32508              6725.48%
                              32        30364              7184.76%
                              34        22722              7528.44%
                              36        19995              7830.88%
                              38        17477              8095.23%
                              40        15559              8330.58%
                              42        12278              8516.29%
                              44        11075              8683.81%
                              46        10255              8838.92%
                              48         9869              8988.20%
                              50         8679              9119.47%
                              52         7182              9228.10%
                              54         6253              9322.69%
                              56         6418              9419.76%
                              58         4685              9490.63%
                              60         4696              9561.66%
                              62         3067              9608.05%
                              64         2546              9646.56%
                              66         2095              9678.25%
                              68         1564              9701.90%
                              70         1828              9729.55%
                              72         1273              9748.81%
                              74         1196              9766.90%
                              76          860              9779.91%
                              78          707              9790.60%
                              80          802              9802.73%
                              82          831              9815.30%
                              84          792              9827.28%
                              86          924              9841.26%
                              88         1239              9860.00%
                              90         1011              9875.29%
                              92          341              9880.45%
                              94          525              9888.39%
                              96          860              9901.40%
                              98          369              9906.98%
                             100          336              9912.06%
                             102          446              9918.81%
                             104          288              9923.16%
                             106          204              9926.25%
                             108          173              9928.86%
                             110          297              9933.36%
                             112          397              9939.36%
                             114           78              9940.54%
                             116          271              9944.64%
                             118           94              9946.06%
                             120           77              9947.23%
                             122           87              9948.54%
                             124           80              9949.75%
                             126           71              9950.83%
                             128           38              9951.40%
                             130          105              9952.99%
                             132           65              9953.97%
                             134           92              9955.36%
                             136           25              9955.74%
                             138           69              9956.79%
                             140           43              9957.44%
                             142           85              9958.72%
                             144          125              9960.61%
                             146           22              9960.95%
                             148           42              9961.58%
                             150           69              9962.62%
                             152          115              9964.36%
                             154           11              9964.53%
                             156           35              9965.06%
                             158           49              9965.80%
                             160           21              9966.12%
                             162           40              9966.72%
                             164           62              9967.66%
                             166           45              9968.34%
                             168           92              9969.73%
                             170           29              9970.17%
                             172           93              9971.58%
                             174           37              9972.14%
                             176           17              9972.40%
                             178           42              9973.03%
                             180          249              9976.80%
                             182          171              9979.38%
                             184          244              9983.07%
                             186          324              9987.98%
                             188           66              9988.97%
                             190          193              9991.89%
                             192          176              9994.55%
                             194           19              9994.84%
                             196          341             10000.00%
cpu.ROB:occ_dist_0.max_value                      196                      
cpu.ROB:occ_dist_0.end_dist

cpu.ROB:occ_dist_1.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_1.samples                     661126                      
cpu.ROB:occ_dist_1.min_value                        0                      
                               0       230673              3489.09%
                               2        17457              3753.14%
                               4        16515              4002.94%
                               6        18778              4286.97%
                               8        19379              4580.10%
                              10        14398              4797.88%
                              12        16256              5043.76%
                              14        20245              5349.98%
                              16        22650              5692.58%
                              18        21098              6011.70%
                              20        27591              6429.03%
                              22        29306              6872.31%
                              24        31602              7350.31%
                              26        24340              7718.47%
                              28        24585              8090.33%
                              30        19014              8377.93%
                              32        12736              8570.58%
                              34        13768              8778.83%
                              36         6647              8879.37%
                              38         7105              8986.83%
                              40         6504              9085.21%
                              42         5052              9161.63%
                              44         5976              9252.02%
                              46         3625              9306.85%
                              48         3551              9360.56%
                              50         3856              9418.89%
                              52         2552              9457.49%
                              54         4028              9518.41%
                              56         1995              9548.59%
                              58         2377              9584.54%
                              60         2124              9616.67%
                              62         1691              9642.25%
                              64         2381              9678.26%
                              66         1522              9701.28%
                              68         1321              9721.26%
                              70          918              9735.15%
                              72          985              9750.05%
                              74         1412              9771.41%
                              76          814              9783.72%
                              78          683              9794.05%
                              80          746              9805.33%
                              82          632              9814.89%
                              84          558              9823.33%
                              86          706              9834.01%
                              88          621              9843.40%
                              90          628              9852.90%
                              92          450              9859.71%
                              94          576              9868.42%
                              96          449              9875.21%
                              98          472              9882.35%
                             100          543              9890.57%
                             102          460              9897.52%
                             104          440              9904.18%
                             106          300              9908.72%
                             108          237              9912.30%
                             110          349              9917.58%
                             112          178              9920.27%
                             114          286              9924.60%
                             116          248              9928.35%
                             118          179              9931.06%
                             120          200              9934.08%
                             122          270              9938.17%
                             124          184              9940.95%
                             126          269              9945.02%
                             128          370              9950.61%
                             130          276              9954.79%
                             132          300              9959.33%
                             134          201              9962.37%
                             136          348              9967.63%
                             138          115              9969.37%
                             140          157              9971.75%
                             142          208              9974.89%
                             144          260              9978.82%
                             146          131              9980.81%
                             148          151              9983.09%
                             150           99              9984.59%
                             152           59              9985.48%
                             154          105              9987.07%
                             156           57              9987.93%
                             158           57              9988.79%
                             160           95              9990.23%
                             162           94              9991.65%
                             164           22              9991.98%
                             166           82              9993.22%
                             168          111              9994.90%
                             170           49              9995.64%
                             172           62              9996.58%
                             174           35              9997.11%
                             176           14              9997.32%
                             178            7              9997.43%
                             180            2              9997.46%
                             182            7              9997.56%
                             184            8              9997.69%
                             186           11              9997.85%
                             188            2              9997.88%
                             190           55              9998.71%
                             192           22              9999.05%
                             194           41              9999.67%
                             196           22             10000.00%
cpu.ROB:occ_dist_1.max_value                      196                      
cpu.ROB:occ_dist_1.end_dist

cpu.ROB:occ_dist_2.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_2.samples                     661126                      
cpu.ROB:occ_dist_2.min_value                        0                      
                               0        60898               921.13%
                               2         3560               974.97%
                               4         5662              1060.61%
                               6         8958              1196.11%
                               8        16090              1439.48%
                              10         9589              1584.52%
                              12        13281              1785.41%
                              14        18022              2058.00%
                              16        24070              2422.08%
                              18        24003              2785.14%
                              20        34947              3313.74%
                              22        40179              3921.48%
                              24        41914              4555.46%
                              26        37253              5118.93%
                              28        37667              5688.67%
                              30        36863              6246.25%
                              32        26593              6648.49%
                              34        23620              7005.76%
                              36        23432              7360.19%
                              38        17562              7625.82%
                              40        13583              7831.28%
                              42        12282              8017.05%
                              44        13196              8216.65%
                              46        10284              8372.20%
                              48         8220              8496.53%
                              50         8097              8619.01%
                              52         7546              8733.15%
                              54         6050              8824.66%
                              56         5156              8902.64%
                              58         4462              8970.14%
                              60         3917              9029.38%
                              62         3484              9082.08%
                              64         3162              9129.91%
                              66         3087              9176.60%
                              68         2402              9212.93%
                              70         1827              9240.57%
                              72         1582              9264.50%
                              74         1703              9290.26%
                              76         1234              9308.92%
                              78         1284              9328.34%
                              80         1237              9347.05%
                              82         1203              9365.25%
                              84         1113              9382.08%
                              86         1031              9397.68%
                              88         1003              9412.85%
                              90          961              9427.39%
                              92          666              9437.46%
                              94          938              9451.65%
                              96         1591              9475.71%
                              98          776              9487.45%
                             100          841              9500.17%
                             102         1114              9517.02%
                             104          865              9530.10%
                             106          949              9544.46%
                             108          932              9558.56%
                             110          842              9571.29%
                             112          974              9586.02%
                             114          865              9599.11%
                             116         1392              9620.16%
                             118          662              9630.18%
                             120          613              9639.45%
                             122          722              9650.37%
                             124          879              9663.66%
                             126          985              9678.56%
                             128          779              9690.35%
                             130          735              9701.46%
                             132          681              9711.76%
                             134         1083              9728.15%
                             136          862              9741.18%
                             138         1106              9757.91%
                             140          889              9771.36%
                             142          914              9785.18%
                             144          808              9797.41%
                             146          828              9809.93%
                             148          927              9823.95%
                             150         1366              9844.61%
                             152          843              9857.36%
                             154          685              9867.73%
                             156          774              9879.43%
                             158          670              9889.57%
                             160          661              9899.57%
                             162          493              9907.02%
                             164          562              9915.52%
                             166          727              9926.52%
                             168          718              9937.38%
                             170          724              9948.33%
                             172          526              9956.29%
                             174          416              9962.58%
                             176          462              9969.57%
                             178          242              9973.23%
                             180          177              9975.90%
                             182          245              9979.61%
                             184           86              9980.91%
                             186          189              9983.77%
                             188           79              9984.97%
                             190          231              9988.46%
                             192           94              9989.88%
                             194           59              9990.77%
                             196          610             10000.00%
cpu.ROB:occ_dist_2.max_value                      196                      
cpu.ROB:occ_dist_2.end_dist

cpu.ROB:occ_dist_3.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_3.samples                     661126                      
cpu.ROB:occ_dist_3.min_value                        0                      
                               0       193980              2934.09%
                               2        11138              3102.56%
                               4        12538              3292.20%
                               6        15839              3531.78%
                               8        20519              3842.14%
                              10        15444              4075.74%
                              12        18717              4358.85%
                              14        24094              4723.29%
                              16        27196              5134.65%
                              18        27680              5553.33%
                              20        33233              6056.00%
                              22        37365              6621.17%
                              24        34302              7140.02%
                              26        30626              7603.26%
                              28        27246              8015.37%
                              30        23396              8369.25%
                              32        18216              8644.78%
                              34        14413              8862.79%
                              36        10416              9020.34%
                              38         8474              9148.51%
                              40         6995              9254.32%
                              42         5895              9343.48%
                              44         4012              9404.17%
                              46         3928              9463.58%
                              48         3570              9517.58%
                              50         2566              9556.39%
                              52         2721              9597.55%
                              54         2560              9636.27%
                              56         1715              9662.21%
                              58         1582              9686.14%
                              60         1602              9710.37%
                              62         1515              9733.29%
                              64         1306              9753.04%
                              66         1085              9769.45%
                              68          939              9783.66%
                              70          979              9798.47%
                              72          845              9811.25%
                              74          817              9823.60%
                              76          573              9832.27%
                              78          814              9844.58%
                              80          338              9849.70%
                              82          630              9859.23%
                              84          669              9869.34%
                              86          313              9874.08%
                              88          525              9882.02%
                              90          375              9887.69%
                              92          267              9891.73%
                              94          294              9896.18%
                              96          214              9899.41%
                              98          306              9904.04%
                             100          247              9907.78%
                             102          258              9911.68%
                             104          308              9916.34%
                             106          307              9920.98%
                             108          252              9924.79%
                             110          314              9929.54%
                             112          290              9933.93%
                             114          151              9936.21%
                             116          198              9939.21%
                             118          150              9941.48%
                             120          162              9943.93%
                             122          149              9946.18%
                             124          254              9950.02%
                             126          157              9952.40%
                             128          223              9955.77%
                             130          133              9957.78%
                             132          139              9959.89%
                             134          135              9961.93%
                             136          230              9965.41%
                             138          103              9966.97%
                             140          104              9968.54%
                             142           75              9969.67%
                             144          182              9972.43%
                             146          100              9973.94%
                             148          143              9976.10%
                             150          148              9978.34%
                             152           83              9979.60%
                             154           74              9980.71%
                             156           76              9981.86%
                             158          142              9984.01%
                             160           86              9985.31%
                             162          146              9987.52%
                             164           72              9988.61%
                             166           86              9989.91%
                             168           63              9990.86%
                             170           45              9991.54%
                             172           72              9992.63%
                             174           41              9993.25%
                             176           73              9994.36%
                             178           27              9994.77%
                             180           19              9995.05%
                             182           34              9995.57%
                             184          122              9997.41%
                             186           87              9998.73%
                             188            2              9998.76%
                             190            1              9998.77%
                             192            1              9998.79%
                             194            0              9998.79%
                             196           80             10000.00%
cpu.ROB:occ_dist_3.max_value                      196                      
cpu.ROB:occ_dist_3.end_dist

cpu.ROB:occ_rate                            96.076730                       # ROB occupancy rate
cpu.ROB:occ_rate_0                          27.048656                       # ROB occupancy rate
cpu.ROB:occ_rate_1                          17.355094                       # ROB occupancy rate
cpu.ROB:occ_rate_2                          33.390547                       # ROB occupancy rate
cpu.ROB:occ_rate_3                          18.282432                       # ROB occupancy rate
cpu.ROB:occupancy                            63518824                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_0                          17882570                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_1                          11473904                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_2                          22075359                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_3                          12086991                       # cpu.ROB occupancy (cumulative)
cpu.SB:RQ:rdy_inst                             443226                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_0                           103902                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_1                            53209                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_2                           145631                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_3                           140484                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_dist_0_mean               0.157159                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_0_stdev              0.594558                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_0_TOT        661126                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_1_mean               0.080482                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_1_stdev              0.541595                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_1_TOT        661126                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_2_mean               0.220277                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_2_stdev              0.638882                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_2_TOT        661126                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_3_mean               0.212492                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_3_stdev              0.878084                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_3_TOT        661126                       # standard deviation of ready rate
cpu.SB:RQ:rdy_rate                           0.670411                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_0                         0.157159                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_1                         0.080482                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_2                         0.220277                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_3                         0.212492                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_x_count                          322585                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_0                         80948                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_1                         34084                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_2                        115254                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_3                         92299                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_max                                 8                       # largest number of insts that become ready
cpu.SB:RQ:rdy_x_rate                         0.487933                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_0                       0.122440                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_1                       0.051554                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_2                       0.174330                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_3                       0.139609                       # number of insts that become ready per cycle
cpu.SB:full_count                                2487                       # store buffer full events (cumulative)
cpu.SB:full_rate                             0.003762                       # store buffer full rate
cpu.SB:occ_rate                              3.804478                       # store buffer occupancy rate
cpu.SB:occ_rate_0                            0.539906                       # store buffer occupancy rate
cpu.SB:occ_rate_1                            0.553825                       # store buffer occupancy rate
cpu.SB:occ_rate_2                            0.771438                       # store buffer occupancy rate
cpu.SB:occ_rate_3                            1.939308                       # store buffer occupancy rate
cpu.SB:occupancy                              2515239                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_0                             356946                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_1                             366148                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_2                             510018                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_3                            1282127                       # store buffer occupancy (cumulative)
cpu.SB:write_barrier_pending_cycles_0               0                       # number of cycles write barriers were pending
cpu.SB:write_barrier_pending_cycles_1               0                       # number of cycles write barriers were pending
cpu.SB:write_barrier_pending_cycles_2               0                       # number of cycles write barriers were pending
cpu.SB:write_barrier_pending_cycles_3               0                       # number of cycles write barriers were pending
cpu.SB:write_barriers                               0                       # number of write barrier operations
cpu.SB:write_barriers_0                             0                       # number of write barrier operations
cpu.SB:write_barriers_1                             0                       # number of write barrier operations
cpu.SB:write_barriers_2                             0                       # number of write barrier operations
cpu.SB:write_barriers_3                             0                       # number of write barrier operations
cpu.WB:consumers                              3609627                       # num instructions consuming a value
cpu.WB:consumers_0                            1172302                       # num instructions consuming a value
cpu.WB:consumers_1                             399384                       # num instructions consuming a value
cpu.WB:consumers_2                            1270009                       # num instructions consuming a value
cpu.WB:consumers_3                             767932                       # num instructions consuming a value
cpu.WB:count                                  4047438                       # cumulative count of insts written-back
cpu.WB:count_0                                1266266                       # cumulative count of insts written-back
cpu.WB:count_1                                 478502                       # cumulative count of insts written-back
cpu.WB:count_2                                1415669                       # cumulative count of insts written-back
cpu.WB:count_3                                 887001                       # cumulative count of insts written-back
cpu.WB:fanout                                0.915330                       # average fanout of values written-back
cpu.WB:fanout_0                              0.884576                       # average fanout of values written-back
cpu.WB:fanout_1                              0.972032                       # average fanout of values written-back
cpu.WB:fanout_2                              0.933957                       # average fanout of values written-back
cpu.WB:fanout_3                              0.901984                       # average fanout of values written-back
cpu.WB:penalized                                    0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_0                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_1                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_2                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_3                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_rate                               0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_0                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_1                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_2                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_3                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:pred_error.start_dist                                   # error in predicted writeback times
cpu.WB:pred_error.samples                     4047438                      
cpu.WB:pred_error.min_value                       147                      
                             -10            0      0.00%      0.00%
                              -9            0      0.00%      0.00%
                              -8            0      0.00%      0.00%
                              -7            0      0.00%      0.00%
                              -6            0      0.00%      0.00%
                              -5            0      0.00%      0.00%
                              -4            0      0.00%      0.00%
                              -3            0      0.00%      0.00%
                              -2            0      0.00%      0.00%
                              -1            0      0.00%      0.00%
                               0            0      0.00%      0.00%
                               1            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               3            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               5            0      0.00%      0.00%
                               6            0      0.00%      0.00%
                               7            0      0.00%      0.00%
                               8            0      0.00%      0.00%
                               9            0      0.00%      0.00%
                              10            0      0.00%      0.00%
                              11            0      0.00%      0.00%
                              12            0      0.00%      0.00%
                              13            0      0.00%      0.00%
                              14            0      0.00%      0.00%
                              15            0      0.00%      0.00%
                              16            0      0.00%      0.00%
                              17            0      0.00%      0.00%
                              18            0      0.00%      0.00%
                              19            0      0.00%      0.00%
                              20            0      0.00%      0.00%
                              21            0      0.00%      0.00%
                              22            0      0.00%      0.00%
                              23            0      0.00%      0.00%
                              24            0      0.00%      0.00%
                              25            0      0.00%      0.00%
                              26            0      0.00%      0.00%
                              27            0      0.00%      0.00%
                              28            0      0.00%      0.00%
                              29            0      0.00%      0.00%
                              30            0      0.00%      0.00%
                              31            0      0.00%      0.00%
                              32            0      0.00%      0.00%
                              33            0      0.00%      0.00%
                              34            0      0.00%      0.00%
                              35            0      0.00%      0.00%
                              36            0      0.00%      0.00%
                              37            0      0.00%      0.00%
                              38            0      0.00%      0.00%
                              39            0      0.00%      0.00%
                              40            0      0.00%      0.00%
                              41            0      0.00%      0.00%
                              42            0      0.00%      0.00%
                              43            0      0.00%      0.00%
                              44            0      0.00%      0.00%
                              45            0      0.00%      0.00%
                              46            0      0.00%      0.00%
                              47            0      0.00%      0.00%
                              48            0      0.00%      0.00%
                              49            0      0.00%      0.00%
                              50            0      0.00%      0.00%
                              51            0      0.00%      0.00%
                              52            0      0.00%      0.00%
                              53            0      0.00%      0.00%
                              54            0      0.00%      0.00%
                              55            0      0.00%      0.00%
                              56            0      0.00%      0.00%
                              57            0      0.00%      0.00%
                              58            0      0.00%      0.00%
                              59            0      0.00%      0.00%
                              60            0      0.00%      0.00%
                              61            0      0.00%      0.00%
                              62            0      0.00%      0.00%
                              63            0      0.00%      0.00%
                              64            0      0.00%      0.00%
                              65            0      0.00%      0.00%
                              66            0      0.00%      0.00%
                              67            0      0.00%      0.00%
                              68            0      0.00%      0.00%
                              69            0      0.00%      0.00%
                              70            0      0.00%      0.00%
                              71            0      0.00%      0.00%
                              72            0      0.00%      0.00%
                              73            0      0.00%      0.00%
                              74            0      0.00%      0.00%
                              75            0      0.00%      0.00%
                              76            0      0.00%      0.00%
                              77            0      0.00%      0.00%
                              78            0      0.00%      0.00%
                              79            0      0.00%      0.00%
                              80            0      0.00%      0.00%
                              81            0      0.00%      0.00%
                              82            0      0.00%      0.00%
                              83            0      0.00%      0.00%
                              84            0      0.00%      0.00%
                              85            0      0.00%      0.00%
                              86            0      0.00%      0.00%
                              87            0      0.00%      0.00%
                              88            0      0.00%      0.00%
                              89            0      0.00%      0.00%
                              90            0      0.00%      0.00%
                              91            0      0.00%      0.00%
                              92            0      0.00%      0.00%
                              93            0      0.00%      0.00%
                              94            0      0.00%      0.00%
                              95            0      0.00%      0.00%
                              96            0      0.00%      0.00%
                              97            0      0.00%      0.00%
                              98            0      0.00%      0.00%
                              99            0      0.00%      0.00%
                             100            0      0.00%      0.00%
cpu.WB:pred_error.overflows                   4047438                      
cpu.WB:pred_error.max_value                    661126                      
cpu.WB:pred_error.end_dist

cpu.WB:producers                              3304000                       # num instructions producing a value
cpu.WB:producers_0                            1036990                       # num instructions producing a value
cpu.WB:producers_1                             388214                       # num instructions producing a value
cpu.WB:producers_2                            1186134                       # num instructions producing a value
cpu.WB:producers_3                             692662                       # num instructions producing a value
cpu.WB:rate                                  6.122037                       # insts written-back per cycle
cpu.WB:rate_0                                1.915317                       # insts written-back per cycle
cpu.WB:rate_1                                0.723768                       # insts written-back per cycle
cpu.WB:rate_2                                2.141300                       # insts written-back per cycle
cpu.WB:rate_3                                1.341652                       # insts written-back per cycle
cpu.branch_pred.btb_accuracy                 0.995625                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_0                      1                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_1               0.976711                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_2                      1                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_3               0.990823                       # fraction of BTB targets correct
cpu.branch_pred.btb_correct                    249652                       # num correct BTB predictions
cpu.branch_pred.btb_correct_0                   83432                       # num correct BTB predictions
cpu.branch_pred.btb_correct_1                   25037                       # num correct BTB predictions
cpu.branch_pred.btb_correct_2                   87197                       # num correct BTB predictions
cpu.branch_pred.btb_correct_3                   53986                       # num correct BTB predictions
cpu.branch_pred.btb_hit_rate                 0.927818                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_0               0.978926                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_1               0.795997                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_2               0.990452                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_3               0.886305                       # BTB hit ratio
cpu.branch_pred.btb_hits                       424538                       # Number of BTB hits
cpu.branch_pred.btb_hits_0                     140889                       # Number of BTB hits
cpu.branch_pred.btb_hits_1                      58228                       # Number of BTB hits
cpu.branch_pred.btb_hits_2                     116698                       # Number of BTB hits
cpu.branch_pred.btb_hits_3                     108723                       # Number of BTB hits
cpu.branch_pred.btb_lookups                    457566                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_0                  143922                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_1                   73151                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_2                  117823                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_3                  122670                       # Number of BTB lookups
cpu.branch_pred.cond_correct                   261685                       # num correct dir predictions
cpu.branch_pred.cond_correct_0                  92106                       # num correct dir predictions
cpu.branch_pred.cond_correct_1                  32588                       # num correct dir predictions
cpu.branch_pred.cond_correct_2                  71316                       # num correct dir predictions
cpu.branch_pred.cond_correct_3                  65675                       # num correct dir predictions
cpu.branch_pred.cond_predicted                 278739                       # num committed conditional branches
cpu.branch_pred.cond_predicted_0                96591                       # num committed conditional branches
cpu.branch_pred.cond_predicted_1                37332                       # num committed conditional branches
cpu.branch_pred.cond_predicted_2                73950                       # num committed conditional branches
cpu.branch_pred.cond_predicted_3                70866                       # num committed conditional branches
cpu.branch_pred.dir_accuracy                 0.938817                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_0               0.953567                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_1               0.872924                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_2               0.964381                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_3               0.926749                       # fraction of predictions correct
cpu.branch_pred.lookup_rate                  1.059440                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_0                0.346489                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_1                0.168532                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_2                0.252492                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_3                0.291926                       # Rate of bpred lookups
cpu.branch_pred.lookups                        700423                       # num BP lookups
cpu.branch_pred.lookups_0                      229073                       # num BP lookups
cpu.branch_pred.lookups_1                      111421                       # num BP lookups
cpu.branch_pred.lookups_2                      166929                       # num BP lookups
cpu.branch_pred.lookups_3                      193000                       # num BP lookups
cpu.branch_pred.ras_accuracy                 0.964323                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_0               0.985503                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_1               0.883096                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_2               0.997725                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_3               0.913285                       # fraction of RAS targets correct
cpu.branch_pred.ras_correct                     37625                       # num correct RAS predictions
cpu.branch_pred.ras_correct_0                    7206                       # num correct RAS predictions
cpu.branch_pred.ras_correct_1                    2795                       # num correct RAS predictions
cpu.branch_pred.ras_correct_2                   18419                       # num correct RAS predictions
cpu.branch_pred.ras_correct_3                    9205                       # num correct RAS predictions
cpu.branch_pred.used_btb                       250749                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_0                      83432                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_1                      25634                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_2                      87197                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_3                      54486                       # num committed branches using target from BTB
cpu.branch_pred.used_ras                        39017                       # num returns predicted using RAS
cpu.branch_pred.used_ras_0                       7312                       # num returns predicted using RAS
cpu.branch_pred.used_ras_1                       3165                       # num returns predicted using RAS
cpu.branch_pred.used_ras_2                      18461                       # num returns predicted using RAS
cpu.branch_pred.used_ras_3                      10079                       # num returns predicted using RAS
cpu.dcache.advance_pool_dist.start_dist                        # Dist. of Repl. across pools
cpu.dcache.advance_pool_dist.samples            68927                      
cpu.dcache.advance_pool_dist.min_value              0                      
                               0        11955   1734.44%           
                               1         4996    724.82%           
                               2         3013    437.13%           
                               3         2209    320.48%           
                               4         1961    284.50%           
                               5         1719    249.39%           
                               6         1775    257.52%           
                               7         1895    274.93%           
                               8         2285    331.51%           
                               9         1719    249.39%           
                              10         1559    226.18%           
                              11         1474    213.85%           
                              12         1595    231.40%           
                              13         1841    267.09%           
                              14         3116    452.07%           
                              15        20968   3042.06%           
                              16         4847    703.21%           
cpu.dcache.advance_pool_dist.max_value             16                      
cpu.dcache.advance_pool_dist.end_dist

cpu.dcache.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
cpu.dcache.avg_blocked_cycles_no_targets    89.212329                       # average number of cycles each access was blocked
cpu.dcache.avg_refs                        121.102995                       # Average number of references to valid blocks.
cpu.dcache.blocked_no_mshrs                         0                       # number of cycles access was blocked
cpu.dcache.blocked_no_targets                     292                       # number of cycles access was blocked
cpu.dcache.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
cpu.dcache.blocked_cycles_no_targets            26050                       # number of cycles access was blocked
cpu.dcache.cache_copies                             0                       # number of cache copies performed
cpu.dcache.demand_accesses                    1087804                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_0                   354935                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_1                   123959                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_2                   383630                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_3                   225280                       # number of demand (read+write) accesses
cpu.dcache.demand_avg_miss_latency          96.533071                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_0        99.989418                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_1        82.705130                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_2        91.545690                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_3       106.856622                       # average overall miss latency
cpu.dcache.demand_avg_mshr_miss_latency     86.649555                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_0   100.131613                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_1    73.673817                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_2    91.621849                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_3   104.858784                       # average overall mshr miss latency
cpu.dcache.demand_hits                        1067212                       # number of demand (read+write) hits
cpu.dcache.demand_hits_0                       353234                       # number of demand (read+write) hits
cpu.dcache.demand_hits_1                       116376                       # number of demand (read+write) hits
cpu.dcache.demand_hits_2                       382470                       # number of demand (read+write) hits
cpu.dcache.demand_hits_3                       215132                       # number of demand (read+write) hits
cpu.dcache.demand_miss_latency                1987809                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_0               170082                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_1               627153                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_2               106193                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_3              1084381                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_rate                  0.018930                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_0                0.004792                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_1                0.061173                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_2                0.003024                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_3                0.045046                       # miss rate for demand accesses
cpu.dcache.demand_misses                        20592                       # number of demand (read+write) misses
cpu.dcache.demand_misses_0                       1701                       # number of demand (read+write) misses
cpu.dcache.demand_misses_1                       7583                       # number of demand (read+write) misses
cpu.dcache.demand_misses_2                       1160                       # number of demand (read+write) misses
cpu.dcache.demand_misses_3                      10148                       # number of demand (read+write) misses
cpu.dcache.demand_mshr_hits                     12839                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_0                     926                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_1                    3527                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_2                     327                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_3                    8059                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_miss_latency            671794                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_0           77602                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_1          298821                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_2           76321                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_3          219050                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_rate             0.007127                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_0           0.002183                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_1           0.032720                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_2           0.002171                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_3           0.009273                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_misses                    7753                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_0                   775                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_1                  4056                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_2                   833                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_3                  2089                       # number of demand (read+write) MSHR misses
cpu.dcache.demote_pool_dist.start_dist                         # Dist. of Repl. across pools
cpu.dcache.demote_pool_dist.samples            574575                      
cpu.dcache.demote_pool_dist.min_value               0                      
                               0       463209   8061.77%           
                               1        20461    356.11%           
                               2        13539    235.64%           
                               3        11603    201.94%           
                               4        10817    188.26%           
                               5        10589    184.29%           
                               6        10364    180.38%           
                               7        10434    181.60%           
                               8         6630    115.39%           
                               9         2193     38.17%           
                              10         1629     28.35%           
                              11         1471     25.60%           
                              12         1388     24.16%           
                              13         1512     26.32%           
                              14         1760     30.63%           
                              15         3037     52.86%           
                              16         3939     68.56%           
cpu.dcache.demote_pool_dist.max_value              16                      
cpu.dcache.demote_pool_dist.end_dist

cpu.dcache.fast_writes                            717                       # number of fast writes performed
cpu.dcache.hash_hit                           1067644                       # Total of hites in hash table
cpu.dcache.hash_miss                            21731                       # Total of misses in hash table
cpu.dcache.hit_depth_total                    1067644                       # Total of hit depths
cpu.dcache.hit_hash_depth_dist.start_dist                      # Dist. of Hash lookup depths
cpu.dcache.hit_hash_depth_dist.samples        1067644                      
cpu.dcache.hit_hash_depth_dist.min_value            1                      
                               0            0      0.00%           
                               1      1067644  10000.00%           
                               2            0      0.00%           
                               3            0      0.00%           
                               4            0      0.00%           
                               5            0      0.00%           
                               6            0      0.00%           
                               7            0      0.00%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
                              17            0      0.00%           
                              18            0      0.00%           
                              19            0      0.00%           
                              20            0      0.00%           
cpu.dcache.hit_hash_depth_dist.max_value            1                      
cpu.dcache.hit_hash_depth_dist.end_dist

cpu.dcache.miss_depth_total                     30104                       # Total of miss depths
cpu.dcache.miss_hash_depth_dist.start_dist                     # Dist. of Hash lookup depths
cpu.dcache.miss_hash_depth_dist.samples         21731                      
cpu.dcache.miss_hash_depth_dist.min_value            1                      
                               0            0      0.00%           
                               1        16360   7528.42%           
                               2         3145   1447.24%           
                               3         1657    762.51%           
                               4          402    184.99%           
                               5          131     60.28%           
                               6           32     14.73%           
                               7            4      1.84%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
                              17            0      0.00%           
                              18            0      0.00%           
                              19            0      0.00%           
                              20            0      0.00%           
cpu.dcache.miss_hash_depth_dist.max_value            7                      
cpu.dcache.miss_hash_depth_dist.end_dist

cpu.dcache.mshr_cap_events                          0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_0                        0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_1                        0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_2                        0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_3                        0                       # number of times MSHR cap was activated
cpu.dcache.no_allocate_misses                       0                       # Number of misses that were no-allocate
cpu.dcache.overall_accesses                   1089375                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_0                  355482                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_1                  124087                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_2                  383646                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_3                  226160                       # number of overall (read+write) accesses
cpu.dcache.overall_avg_miss_latency         97.048825                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_0       99.833920                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_1       82.786576                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_2       91.866438                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_3      107.520544                       # average overall miss latency
cpu.dcache.overall_avg_mshr_miss_latency    88.197185                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_0   100.024485                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_1    73.831131                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_2    92.038050                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_3   107.517529                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_2 <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_3 <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_hits                       1068361                       # number of overall hits
cpu.dcache.overall_hits_0                      353778                       # number of overall hits
cpu.dcache.overall_hits_1                      116459                       # number of overall hits
cpu.dcache.overall_hits_2                      382478                       # number of overall hits
cpu.dcache.overall_hits_3                      215646                       # number of overall hits
cpu.dcache.overall_miss_latency               2039384                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_0              170117                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_1              631496                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_2              107300                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_3             1130471                       # number of overall miss cycles
cpu.dcache.overall_miss_rate                 0.019290                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_0               0.004793                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_1               0.061473                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_2               0.003044                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_3               0.046489                       # miss rate for overall accesses
cpu.dcache.overall_misses                       21014                       # number of overall misses
cpu.dcache.overall_misses_0                      1704                       # number of overall misses
cpu.dcache.overall_misses_1                      7628                       # number of overall misses
cpu.dcache.overall_misses_2                      1168                       # number of overall misses
cpu.dcache.overall_misses_3                     10514                       # number of overall misses
cpu.dcache.overall_mshr_hits                    12915                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_0                    928                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_1                   3542                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_2                    327                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_3                   8118                       # number of overall MSHR hits
cpu.dcache.overall_mshr_miss_latency           714309                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_0          77619                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_1         301674                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_2          77404                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_3         257612                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_rate            0.007435                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_0          0.002183                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_1          0.032929                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_2          0.002192                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_3          0.010594                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_misses                   8099                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_0                  776                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_1                 4086                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_2                  841                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_3                 2396                       # number of overall MSHR misses
cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_2            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_3            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_2            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_3            0                       # number of overall MSHR uncacheable misses
cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.dcache.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
cpu.dcache.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.dcache.read_accesses                       765219                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_0                     273987                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_1                      89875                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_2                     268376                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_3                     132981                       # number of read accesses(hits+misses)
cpu.dcache.read_avg_miss_latency            82.090883                       # average read miss latency
cpu.dcache.read_avg_miss_latency_0         101.044994                       # average read miss latency
cpu.dcache.read_avg_miss_latency_1          74.164214                       # average read miss latency
cpu.dcache.read_avg_miss_latency_2          89.791107                       # average read miss latency
cpu.dcache.read_avg_miss_latency_3          84.925090                       # average read miss latency
cpu.dcache.read_avg_mshr_miss_latency       77.935897                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_0    100.765499                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_1     70.891508                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_2     89.322622                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_3     78.484048                       # average read mshr miss latency
cpu.dcache.read_hits                           754953                       # number of read hits
cpu.dcache.read_hits_0                         272409                       # number of read hits
cpu.dcache.read_hits_1                          84370                       # number of read hits
cpu.dcache.read_hits_2                         267409                       # number of read hits
cpu.dcache.read_hits_3                         130765                       # number of read hits
cpu.dcache.read_miss_latency                   842745                       # number of read miss cycles
cpu.dcache.read_miss_latency_0                 159449                       # number of read miss cycles
cpu.dcache.read_miss_latency_1                 408274                       # number of read miss cycles
cpu.dcache.read_miss_latency_2                  86828                       # number of read miss cycles
cpu.dcache.read_miss_latency_3                 188194                       # number of read miss cycles
cpu.dcache.read_miss_rate                    0.013416                       # miss rate for read accesses
cpu.dcache.read_miss_rate_0                  0.005759                       # miss rate for read accesses
cpu.dcache.read_miss_rate_1                  0.061252                       # miss rate for read accesses
cpu.dcache.read_miss_rate_2                  0.003603                       # miss rate for read accesses
cpu.dcache.read_miss_rate_3                  0.016664                       # miss rate for read accesses
cpu.dcache.read_misses                          10266                       # number of read misses
cpu.dcache.read_misses_0                         1578                       # number of read misses
cpu.dcache.read_misses_1                         5505                       # number of read misses
cpu.dcache.read_misses_2                          967                       # number of read misses
cpu.dcache.read_misses_3                         2216                       # number of read misses
cpu.dcache.read_mshr_hits                        4104                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_0                       836                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_1                      1772                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_2                       189                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_3                      1307                       # number of read MSHR hits
cpu.dcache.read_mshr_miss_latency              480241                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_0             74768                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_1            264638                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_2             69493                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_3             71342                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_rate               0.008053                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_0             0.002708                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_1             0.041535                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_2             0.002899                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_3             0.006836                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_misses                      6162                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_0                     742                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_1                    3733                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_2                     778                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_3                     909                       # number of read MSHR misses
cpu.dcache.repl_pool_dist.start_dist                           # Dist. of Repl. across pools
cpu.dcache.repl_pool_dist.samples                7792                      
cpu.dcache.repl_pool_dist.min_value                 0                      
                               0         7792  10000.00%           
                               1            0      0.00%           
                               2            0      0.00%           
                               3            0      0.00%           
                               4            0      0.00%           
                               5            0      0.00%           
                               6            0      0.00%           
                               7            0      0.00%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
cpu.dcache.repl_pool_dist.max_value                 0                      
cpu.dcache.repl_pool_dist.end_dist

cpu.dcache.replacements                          7792                       # number of replacements
cpu.dcache.replacements_0                         578                       # number of replacements
cpu.dcache.replacements_1                        3579                       # number of replacements
cpu.dcache.replacements_2                         711                       # number of replacements
cpu.dcache.replacements_3                        2924                       # number of replacements
cpu.dcache.sampled_refs                          8816                       # Sample count of references to valid blocks.
cpu.dcache.set_access_dist.start_dist                          # Dist. of Accesses across sets
cpu.dcache.set_access_dist.samples            1089375                      
cpu.dcache.set_access_dist.min_value                0                      
                               0          299      2.74%           
                               1          209      1.92%           
                               2          235      2.16%           
                               3          221      2.03%           
                               4          232      2.13%           
                               5          258      2.37%           
                               6          643      5.90%           
                               7         9166     84.14%           
                               8         6837     62.76%           
                               9        76612    703.27%           
                              10          337      3.09%           
                              11          322      2.96%           
                              12          211      1.94%           
                              13          302      2.77%           
                              14          184      1.69%           
                              15          238      2.18%           
                              16          208      1.91%           
                              17          205      1.88%           
                              18          247      2.27%           
                              19          300      2.75%           
                              20          383      3.52%           
                              21          278      2.55%           
                              22          255      2.34%           
                              23          311      2.85%           
                              24          268      2.46%           
                              25          333      3.06%           
                              26          403      3.70%           
                              27         2167     19.89%           
                              28          332      3.05%           
                              29          555      5.09%           
                              30          231      2.12%           
                              31        20097    184.48%           
                              32          250      2.29%           
                              33          329      3.02%           
                              34         1140     10.46%           
                              35          280      2.57%           
                              36          762      6.99%           
                              37         1388     12.74%           
                              38          286      2.63%           
                              39          255      2.34%           
                              40          539      4.95%           
                              41        26920    247.11%           
                              42          765      7.02%           
                              43         2187     20.08%           
                              44          461      4.23%           
                              45          462      4.24%           
                              46         2495     22.90%           
                              47          243      2.23%           
                              48          177      1.62%           
                              49          242      2.22%           
                              50        10308     94.62%           
                              51         1299     11.92%           
                              52          159      1.46%           
                              53          144      1.32%           
                              54          168      1.54%           
                              55          329      3.02%           
                              56         1132     10.39%           
                              57          871      8.00%           
                              58          577      5.30%           
                              59         1812     16.63%           
                              60          358      3.29%           
                              61          336      3.08%           
                              62         1013      9.30%           
                              63          323      2.97%           
                              64          750      6.88%           
                              65          317      2.91%           
                              66          197      1.81%           
                              67          493      4.53%           
                              68         7121     65.37%           
                              69        10639     97.66%           
                              70          579      5.31%           
                              71         1162     10.67%           
                              72        27581    253.18%           
                              73       156208   1433.92%           
                              74        38737    355.59%           
                              75        55355    508.14%           
                              76        10377     95.26%           
                              77          266      2.44%           
                              78        39593    363.45%           
                              79        24125    221.46%           
                              80          120      1.10%           
                              81         1365     12.53%           
                              82          732      6.72%           
                              83          165      1.51%           
                              84         2197     20.17%           
                              85         2014     18.49%           
                              86         1201     11.02%           
                              87          831      7.63%           
                              88          368      3.38%           
                              89          311      2.85%           
                              90        27044    248.25%           
                              91         2865     26.30%           
                              92        21396    196.41%           
                              93          599      5.50%           
                              94          384      3.52%           
                              95         1037      9.52%           
                              96         7852     72.08%           
                              97         1915     17.58%           
                              98         2163     19.86%           
                              99         5055     46.40%           
                             100         7881     72.34%           
                             101        15798    145.02%           
                             102         5811     53.34%           
                             103         4414     40.52%           
                             104          311      2.85%           
                             105         8694     79.81%           
                             106         3294     30.24%           
                             107         2188     20.08%           
                             108          410      3.76%           
                             109          344      3.16%           
                             110         4905     45.03%           
                             111         1127     10.35%           
                             112          286      2.63%           
                             113          279      2.56%           
                             114          373      3.42%           
                             115          471      4.32%           
                             116          447      4.10%           
                             117          740      6.79%           
                             118          296      2.72%           
                             119          276      2.53%           
                             120         2554     23.44%           
                             121          354      3.25%           
                             122          941      8.64%           
                             123         2679     24.59%           
                             124          934      8.57%           
                             125         1212     11.13%           
                             126         1746     16.03%           
                             127         1112     10.21%           
                             128         2261     20.76%           
                             129          829      7.61%           
                             130          997      9.15%           
                             131         1005      9.23%           
                             132          756      6.94%           
                             133          716      6.57%           
                             134          728      6.68%           
                             135          710      6.52%           
                             136          740      6.79%           
                             137          660      6.06%           
                             138          987      9.06%           
                             139          970      8.90%           
                             140          608      5.58%           
                             141          611      5.61%           
                             142          955      8.77%           
                             143          571      5.24%           
                             144          685      6.29%           
                             145          919      8.44%           
                             146          647      5.94%           
                             147          692      6.35%           
                             148          503      4.62%           
                             149          648      5.95%           
                             150          743      6.82%           
                             151          832      7.64%           
                             152          693      6.36%           
                             153          657      6.03%           
                             154          600      5.51%           
                             155          548      5.03%           
                             156          838      7.69%           
                             157         1122     10.30%           
                             158         1693     15.54%           
                             159         1519     13.94%           
                             160         1354     12.43%           
                             161         1826     16.76%           
                             162         2249     20.64%           
                             163         1835     16.84%           
                             164         2601     23.88%           
                             165         2602     23.89%           
                             166         3508     32.20%           
                             167         2790     25.61%           
                             168         4269     39.19%           
                             169         4008     36.79%           
                             170         5560     51.04%           
                             171         5101     46.83%           
                             172          733      6.73%           
                             173          596      5.47%           
                             174          650      5.97%           
                             175          684      6.28%           
                             176          607      5.57%           
                             177         1948     17.88%           
                             178          623      5.72%           
                             179          694      6.37%           
                             180          591      5.43%           
                             181          693      6.36%           
                             182          906      8.32%           
                             183          772      7.09%           
                             184          583      5.35%           
                             185          492      4.52%           
                             186          531      4.87%           
                             187          616      5.65%           
                             188          537      4.93%           
                             189          599      5.50%           
                             190          619      5.68%           
                             191          901      8.27%           
                             192          313      2.87%           
                             193          311      2.85%           
                             194          310      2.85%           
                             195          351      3.22%           
                             196          377      3.46%           
                             197          366      3.36%           
                             198          331      3.04%           
                             199          316      2.90%           
                             200          339      3.11%           
                             201          327      3.00%           
                             202          450      4.13%           
                             203          354      3.25%           
                             204          361      3.31%           
                             205          325      2.98%           
                             206          340      3.12%           
                             207          354      3.25%           
                             208          474      4.35%           
                             209          723      6.64%           
                             210          455      4.18%           
                             211          531      4.87%           
                             212          618      5.67%           
                             213          395      3.63%           
                             214         2290     21.02%           
                             215         2407     22.10%           
                             216          352      3.23%           
                             217          355      3.26%           
                             218          609      5.59%           
                             219          465      4.27%           
                             220          387      3.55%           
                             221         1011      9.28%           
                             222          337      3.09%           
                             223          437      4.01%           
                             224          564      5.18%           
                             225          310      2.85%           
                             226          379      3.48%           
                             227          287      2.63%           
                             228         1788     16.41%           
                             229         1813     16.64%           
                             230          681      6.25%           
                             231          411      3.77%           
                             232          384      3.52%           
                             233          427      3.92%           
                             234          368      3.38%           
                             235          518      4.76%           
                             236          493      4.53%           
                             237          811      7.44%           
                             238          427      3.92%           
                             239          474      4.35%           
                             240          263      2.41%           
                             241          324      2.97%           
                             242          316      2.90%           
                             243          304      2.79%           
                             244          328      3.01%           
                             245         1401     12.86%           
                             246        17901    164.32%           
                             247          300      2.75%           
                             248          623      5.72%           
                             249          429      3.94%           
                             250          882      8.10%           
                             251          285      2.62%           
                             252          267      2.45%           
                             253          353      3.24%           
                             254          325      2.98%           
                             255          318      2.92%           
                             256         3394     31.16%           
                             257          693      6.36%           
                             258          273      2.51%           
                             259          303      2.78%           
                             260          264      2.42%           
                             261          271      2.49%           
                             262          432      3.97%           
                             263         3912     35.91%           
                             264          331      3.04%           
                             265         2636     24.20%           
                             266          652      5.99%           
                             267          550      5.05%           
                             268         1209     11.10%           
                             269         2095     19.23%           
                             270         2182     20.03%           
                             271         2040     18.73%           
                             272        31582    289.91%           
                             273         1520     13.95%           
                             274         2688     24.67%           
                             275         1284     11.79%           
                             276          498      4.57%           
                             277          391      3.59%           
                             278         3022     27.74%           
                             279         1337     12.27%           
                             280          342      3.14%           
                             281         1155     10.60%           
                             282         1025      9.41%           
                             283          330      3.03%           
                             284         1096     10.06%           
                             285          520      4.77%           
                             286          407      3.74%           
                             287          307      2.82%           
                             288         1206     11.07%           
                             289          453      4.16%           
                             290          774      7.10%           
                             291          858      7.88%           
                             292          977      8.97%           
                             293          506      4.64%           
                             294          812      7.45%           
                             295          454      4.17%           
                             296         1506     13.82%           
                             297          959      8.80%           
                             298          832      7.64%           
                             299         1343     12.33%           
                             300         1371     12.59%           
                             301         2327     21.36%           
                             302          832      7.64%           
                             303          791      7.26%           
                             304          867      7.96%           
                             305          473      4.34%           
                             306         1115     10.24%           
                             307         1031      9.46%           
                             308         1696     15.57%           
                             309         1405     12.90%           
                             310          444      4.08%           
                             311          789      7.24%           
                             312          918      8.43%           
                             313          437      4.01%           
                             314          909      8.34%           
                             315          680      6.24%           
                             316          789      7.24%           
                             317          852      7.82%           
                             318         1035      9.50%           
                             319          545      5.00%           
                             320          490      4.50%           
                             321          694      6.37%           
                             322          416      3.82%           
                             323          725      6.66%           
                             324          401      3.68%           
                             325          449      4.12%           
                             326          616      5.65%           
                             327          438      4.02%           
                             328         1012      9.29%           
                             329         1179     10.82%           
                             330         1401     12.86%           
                             331          821      7.54%           
                             332         1178     10.81%           
                             333          665      6.10%           
                             334          749      6.88%           
                             335          979      8.99%           
                             336          512      4.70%           
                             337          329      3.02%           
                             338          623      5.72%           
                             339          850      7.80%           
                             340         1157     10.62%           
                             341         1824     16.74%           
                             342          384      3.52%           
                             343         2437     22.37%           
                             344         1146     10.52%           
                             345          329      3.02%           
                             346          883      8.11%           
                             347          986      9.05%           
                             348          449      4.12%           
                             349          797      7.32%           
                             350          689      6.32%           
                             351          521      4.78%           
                             352          804      7.38%           
                             353        27437    251.86%           
                             354        26340    241.79%           
                             355         2524     23.17%           
                             356         1714     15.73%           
                             357         1290     11.84%           
                             358          557      5.11%           
                             359         1805     16.57%           
                             360          476      4.37%           
                             361          616      5.65%           
                             362         1502     13.79%           
                             363         1440     13.22%           
                             364          433      3.97%           
                             365          369      3.39%           
                             366          987      9.06%           
                             367          737      6.77%           
                             368          664      6.10%           
                             369         2259     20.74%           
                             370          292      2.68%           
                             371          870      7.99%           
                             372          501      4.60%           
                             373          621      5.70%           
                             374         4424     40.61%           
                             375         2910     26.71%           
                             376          429      3.94%           
                             377          830      7.62%           
                             378          839      7.70%           
                             379          580      5.32%           
                             380          966      8.87%           
                             381          753      6.91%           
                             382          889      8.16%           
                             383          635      5.83%           
                             384          238      2.18%           
                             385          218      2.00%           
                             386          262      2.41%           
                             387          248      2.28%           
                             388          260      2.39%           
                             389          232      2.13%           
                             390         4619     42.40%           
                             391         4366     40.08%           
                             392          431      3.96%           
                             393          356      3.27%           
                             394          360      3.30%           
                             395          499      4.58%           
                             396          266      2.44%           
                             397          239      2.19%           
                             398          296      2.72%           
                             399          298      2.74%           
                             400          226      2.07%           
                             401          268      2.46%           
                             402          576      5.29%           
                             403          529      4.86%           
                             404          282      2.59%           
                             405          286      2.63%           
                             406          242      2.22%           
                             407          280      2.57%           
                             408          229      2.10%           
                             409          230      2.11%           
                             410          230      2.11%           
                             411          233      2.14%           
                             412          234      2.15%           
                             413          257      2.36%           
                             414          263      2.41%           
                             415          210      1.93%           
                             416          224      2.06%           
                             417          220      2.02%           
                             418          204      1.87%           
                             419          241      2.21%           
                             420          818      7.51%           
                             421          237      2.18%           
                             422          237      2.18%           
                             423          313      2.87%           
                             424         3000     27.54%           
                             425          276      2.53%           
                             426          330      3.03%           
                             427          255      2.34%           
                             428          245      2.25%           
                             429          219      2.01%           
                             430          265      2.43%           
                             431          274      2.52%           
                             432          299      2.74%           
                             433          324      2.97%           
                             434          341      3.13%           
                             435          294      2.70%           
                             436          311      2.85%           
                             437          308      2.83%           
                             438          257      2.36%           
                             439          341      3.13%           
                             440          119      1.09%           
                             441          301      2.76%           
                             442          302      2.77%           
                             443          238      2.18%           
                             444          115      1.06%           
                             445          116      1.06%           
                             446          200      1.84%           
                             447          154      1.41%           
                             448          128      1.17%           
                             449          154      1.41%           
                             450          107      0.98%           
                             451          140      1.29%           
                             452          124      1.14%           
                             453          129      1.18%           
                             454          150      1.38%           
                             455          127      1.17%           
                             456          208      1.91%           
                             457          262      2.41%           
                             458          144      1.32%           
                             459          151      1.39%           
                             460          153      1.40%           
                             461          197      1.81%           
                             462          140      1.29%           
                             463          173      1.59%           
                             464          140      1.29%           
                             465          194      1.78%           
                             466          109      1.00%           
                             467          119      1.09%           
                             468           96      0.88%           
                             469          113      1.04%           
                             470          108      0.99%           
                             471          112      1.03%           
                             472          109      1.00%           
                             473          207      1.90%           
                             474          109      1.00%           
                             475          100      0.92%           
                             476          110      1.01%           
                             477          144      1.32%           
                             478          106      0.97%           
                             479          119      1.09%           
                             480           67      0.62%           
                             481          497      4.56%           
                             482           82      0.75%           
                             483           75      0.69%           
                             484          104      0.95%           
                             485          150      1.38%           
                             486          138      1.27%           
                             487          140      1.29%           
                             488          122      1.12%           
                             489          239      2.19%           
                             490          162      1.49%           
                             491          142      1.30%           
                             492          145      1.33%           
                             493          144      1.32%           
                             494          166      1.52%           
                             495          182      1.67%           
                             496           96      0.88%           
                             497          182      1.67%           
                             498          204      1.87%           
                             499          115      1.06%           
                             500          437      4.01%           
                             501          244      2.24%           
                             502          171      1.57%           
                             503           72      0.66%           
                             504          413      3.79%           
                             505          189      1.73%           
                             506          162      1.49%           
                             507          533      4.89%           
                             508         1986     18.23%           
                             509          246      2.26%           
                             510          149      1.37%           
                             511          123      1.13%           
                             512            0      0.00%           
cpu.dcache.set_access_dist.max_value              511                      
cpu.dcache.set_access_dist.end_dist

cpu.dcache.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_0                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_1                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_2                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_3                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.swpf_accesses                         1571                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_0                        547                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_1                        128                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_2                         16                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_3                        880                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_avg_miss_latency           122.215640                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_0          11.666667                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_1          96.511111                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_2         138.375000                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_3         125.928962                       # average swpf miss latency
cpu.dcache.swpf_avg_mshr_miss_latency      122.875723                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_0            17                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_1     95.100000                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_2    135.375000                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_3    125.609121                       # average swpf mshr miss latency
cpu.dcache.swpf_hits                             1149                       # number of swpf hits
cpu.dcache.swpf_hits_0                            544                       # number of swpf hits
cpu.dcache.swpf_hits_1                             83                       # number of swpf hits
cpu.dcache.swpf_hits_2                              8                       # number of swpf hits
cpu.dcache.swpf_hits_3                            514                       # number of swpf hits
cpu.dcache.swpf_miss_latency                    51575                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_0                     35                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_1                   4343                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_2                   1107                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_3                  46090                       # number of swpf miss cycles
cpu.dcache.swpf_miss_rate                    0.268619                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_0                  0.005484                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_1                  0.351562                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_2                  0.500000                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_3                  0.415909                       # miss rate for swpf accesses
cpu.dcache.swpf_misses                            422                       # number of swpf misses
cpu.dcache.swpf_misses_0                            3                       # number of swpf misses
cpu.dcache.swpf_misses_1                           45                       # number of swpf misses
cpu.dcache.swpf_misses_2                            8                       # number of swpf misses
cpu.dcache.swpf_misses_3                          366                       # number of swpf misses
cpu.dcache.swpf_mshr_hits                          76                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_0                         2                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_1                        15                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_3                        59                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_miss_latency               42515                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_0                17                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_1              2853                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_2              1083                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_3             38562                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_rate               0.220242                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_0             0.001828                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_1             0.234375                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_2             0.500000                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_3             0.348864                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_misses                       346                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_0                       1                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_1                      30                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_2                       8                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_3                     307                       # number of swpf MSHR misses
cpu.dcache.tagsinuse                       971.505991                       # Cycle average of tags in use
cpu.dcache.total_refs                         1067644                       # Total number of references to valid blocks.
cpu.dcache.warmup_cycle                         81079                       # Cycle when the warmup percentage was hit.
cpu.dcache.write_accesses                      322585                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_0                     80948                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_1                     34084                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_2                    115254                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_3                     92299                       # number of write accesses(hits+misses)
cpu.dcache.write_avg_miss_latency          110.891342                       # average write miss latency
cpu.dcache.write_avg_miss_latency_0         86.447154                       # average write miss latency
cpu.dcache.write_avg_miss_latency_1        105.331569                       # average write miss latency
cpu.dcache.write_avg_miss_latency_2        100.336788                       # average write miss latency
cpu.dcache.write_avg_miss_latency_3        112.983737                       # average write miss latency
cpu.dcache.write_avg_mshr_miss_latency     120.397863                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_0    85.878788                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_1   105.829721                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_2   124.145455                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_3   125.176271                       # average write mshr miss latency
cpu.dcache.write_hits                          312259                       # number of write hits
cpu.dcache.write_hits_0                         80825                       # number of write hits
cpu.dcache.write_hits_1                         32006                       # number of write hits
cpu.dcache.write_hits_2                        115061                       # number of write hits
cpu.dcache.write_hits_3                         84367                       # number of write hits
cpu.dcache.write_miss_latency                 1145064                       # number of write miss cycles
cpu.dcache.write_miss_latency_0                 10633                       # number of write miss cycles
cpu.dcache.write_miss_latency_1                218879                       # number of write miss cycles
cpu.dcache.write_miss_latency_2                 19365                       # number of write miss cycles
cpu.dcache.write_miss_latency_3                896187                       # number of write miss cycles
cpu.dcache.write_miss_rate                   0.032010                       # miss rate for write accesses
cpu.dcache.write_miss_rate_0                 0.001519                       # miss rate for write accesses
cpu.dcache.write_miss_rate_1                 0.060967                       # miss rate for write accesses
cpu.dcache.write_miss_rate_2                 0.001675                       # miss rate for write accesses
cpu.dcache.write_miss_rate_3                 0.085938                       # miss rate for write accesses
cpu.dcache.write_misses                         10326                       # number of write misses
cpu.dcache.write_misses_0                         123                       # number of write misses
cpu.dcache.write_misses_1                        2078                       # number of write misses
cpu.dcache.write_misses_2                         193                       # number of write misses
cpu.dcache.write_misses_3                        7932                       # number of write misses
cpu.dcache.write_mshr_hits                       8735                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_0                       90                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_1                     1755                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_2                      138                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_3                     6752                       # number of write MSHR hits
cpu.dcache.write_mshr_miss_latency             191553                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_0             2834                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_1            34183                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_2             6828                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_3           147708                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_rate              0.004932                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_0            0.000408                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_1            0.009477                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_2            0.000477                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_3            0.012785                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_misses                     1591                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_0                     33                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_1                    323                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_2                     55                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_3                   1180                       # number of write MSHR misses
cpu.dcache.writebacks                            3077                       # number of writebacks
cpu.dcache.writebacks_0                            56                       # number of writebacks
cpu.dcache.writebacks_1                           394                       # number of writebacks
cpu.dcache.writebacks_2                           381                       # number of writebacks
cpu.dcache.writebacks_3                          2246                       # number of writebacks
cpu.floss.fetch_0.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_0.end_dist
cpu.floss.fetch_1.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_1.end_dist
cpu.floss.fetch_2.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_2.end_dist
cpu.floss.fetch_3.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_3.end_dist
cpu.floss.icache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_0.end_dist
cpu.floss.icache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_1.end_dist
cpu.floss.icache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_2.end_dist
cpu.floss.icache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_3.end_dist
cpu.floss.iq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_0.end_dist
cpu.floss.iq_full_1.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_1.end_dist
cpu.floss.iq_full_2.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_2.end_dist
cpu.floss.iq_full_3.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_3.end_dist
cpu.floss.iq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_0.end_dist
cpu.floss.iq_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_1.end_dist
cpu.floss.iq_full_dcache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_2.end_dist
cpu.floss.iq_full_dcache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_3.end_dist
cpu.floss.iq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_0.end_dist
cpu.floss.iq_full_deps_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_1.end_dist
cpu.floss.iq_full_deps_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_2.end_dist
cpu.floss.iq_full_deps_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_3.end_dist
cpu.floss.iq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_0.end_dist
cpu.floss.iq_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_1.end_dist
cpu.floss.iq_full_fu_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_2.end_dist
cpu.floss.iq_full_fu_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_3.end_dist
cpu.floss.lsq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_0.end_dist
cpu.floss.lsq_full_1.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_1.end_dist
cpu.floss.lsq_full_2.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_2.end_dist
cpu.floss.lsq_full_3.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_3.end_dist
cpu.floss.lsq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_0.end_dist
cpu.floss.lsq_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_1.end_dist
cpu.floss.lsq_full_dcache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_2.end_dist
cpu.floss.lsq_full_dcache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_3.end_dist
cpu.floss.lsq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_0.end_dist
cpu.floss.lsq_full_deps_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_1.end_dist
cpu.floss.lsq_full_deps_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_2.end_dist
cpu.floss.lsq_full_deps_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_3.end_dist
cpu.floss.lsq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_0.end_dist
cpu.floss.lsq_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_1.end_dist
cpu.floss.lsq_full_fu_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_2.end_dist
cpu.floss.lsq_full_fu_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_3.end_dist
cpu.floss.qfull_0.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_0.end_dist
cpu.floss.qfull_1.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_1.end_dist
cpu.floss.qfull_2.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_2.end_dist
cpu.floss.qfull_3.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_3.end_dist
cpu.floss.rob_full_0.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_0.end_dist
cpu.floss.rob_full_1.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_1.end_dist
cpu.floss.rob_full_2.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_2.end_dist
cpu.floss.rob_full_3.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_3.end_dist
cpu.floss.rob_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_0.end_dist
cpu.floss.rob_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_1.end_dist
cpu.floss.rob_full_dcache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_2.end_dist
cpu.floss.rob_full_dcache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_3.end_dist
cpu.floss.rob_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_0.end_dist
cpu.floss.rob_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_1.end_dist
cpu.floss.rob_full_fu_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_2.end_dist
cpu.floss.rob_full_fu_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_3.end_dist
cpu.icache.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
cpu.icache.avg_refs                         66.521842                       # Average number of references to valid blocks.
cpu.icache.blocked_no_mshrs                         0                       # number of cycles access was blocked
cpu.icache.blocked_no_targets                       0                       # number of cycles access was blocked
cpu.icache.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
cpu.icache.blocked_cycles_no_targets                0                       # number of cycles access was blocked
cpu.icache.cache_copies                             0                       # number of cache copies performed
cpu.icache.demand_accesses                    1234327                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_0                   347351                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_1                   185130                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_2                   382324                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_3                   319522                       # number of demand (read+write) accesses
cpu.icache.demand_avg_miss_latency                 25                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_0        24.230134                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_1        24.074617                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_2        41.031532                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_3        25.158499                       # average overall miss latency
cpu.icache.demand_avg_mshr_miss_latency     36.851628                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_0    33.846402                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_1    33.724041                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_2    59.877517                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_3    40.631782                       # average overall mshr miss latency
cpu.icache.demand_hits                        1213691                       # number of demand (read+write) hits
cpu.icache.demand_hits_0                       346382                       # number of demand (read+write) hits
cpu.icache.demand_hits_1                       173189                       # number of demand (read+write) hits
cpu.icache.demand_hits_2                       381658                       # number of demand (read+write) hits
cpu.icache.demand_hits_3                       312462                       # number of demand (read+write) hits
cpu.icache.demand_miss_latency                 515900                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_0                23479                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_1               287475                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_2                27327                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_3               177619                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_rate                  0.016718                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_0                0.002790                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_1                0.064501                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_2                0.001742                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_3                0.022096                       # miss rate for demand accesses
cpu.icache.demand_misses                        20636                       # number of demand (read+write) misses
cpu.icache.demand_misses_0                        969                       # number of demand (read+write) misses
cpu.icache.demand_misses_1                      11941                       # number of demand (read+write) misses
cpu.icache.demand_misses_2                        666                       # number of demand (read+write) misses
cpu.icache.demand_misses_3                       7060                       # number of demand (read+write) misses
cpu.icache.demand_mshr_hits                      1286                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_0                      38                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_1                     606                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_2                      70                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_3                     572                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_miss_latency            713079                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_0           31511                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_1          382262                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_2           35687                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_3          263619                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_rate             0.015677                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_0           0.002680                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_1           0.061227                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_2           0.001559                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_3           0.020305                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_misses                   19350                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_0                   931                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_1                 11335                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_2                   596                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_3                  6488                       # number of demand (read+write) MSHR misses
cpu.icache.fast_writes                              0                       # number of fast writes performed
cpu.icache.mshr_cap_events                          0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_0                        0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_1                        0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_2                        0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_3                        0                       # number of times MSHR cap was activated
cpu.icache.no_allocate_misses                       0                       # Number of misses that were no-allocate
cpu.icache.overall_accesses                   1234327                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_0                  347351                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_1                  185130                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_2                  382324                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_3                  319522                       # number of overall (read+write) accesses
cpu.icache.overall_avg_miss_latency                25                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_0       24.230134                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_1       24.074617                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_2       41.031532                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_3       25.158499                       # average overall miss latency
cpu.icache.overall_avg_mshr_miss_latency    36.851628                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_0    33.846402                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_1    33.724041                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_2    59.877517                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_3    40.631782                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_2 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_3 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_hits                       1213691                       # number of overall hits
cpu.icache.overall_hits_0                      346382                       # number of overall hits
cpu.icache.overall_hits_1                      173189                       # number of overall hits
cpu.icache.overall_hits_2                      381658                       # number of overall hits
cpu.icache.overall_hits_3                      312462                       # number of overall hits
cpu.icache.overall_miss_latency                515900                       # number of overall miss cycles
cpu.icache.overall_miss_latency_0               23479                       # number of overall miss cycles
cpu.icache.overall_miss_latency_1              287475                       # number of overall miss cycles
cpu.icache.overall_miss_latency_2               27327                       # number of overall miss cycles
cpu.icache.overall_miss_latency_3              177619                       # number of overall miss cycles
cpu.icache.overall_miss_rate                 0.016718                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_0               0.002790                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_1               0.064501                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_2               0.001742                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_3               0.022096                       # miss rate for overall accesses
cpu.icache.overall_misses                       20636                       # number of overall misses
cpu.icache.overall_misses_0                       969                       # number of overall misses
cpu.icache.overall_misses_1                     11941                       # number of overall misses
cpu.icache.overall_misses_2                       666                       # number of overall misses
cpu.icache.overall_misses_3                      7060                       # number of overall misses
cpu.icache.overall_mshr_hits                     1286                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_0                     38                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_1                    606                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_2                     70                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_3                    572                       # number of overall MSHR hits
cpu.icache.overall_mshr_miss_latency           713079                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_0          31511                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_1         382262                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_2          35687                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_3         263619                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_rate            0.015677                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_0          0.002680                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_1          0.061227                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_2          0.001559                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_3          0.020305                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_misses                  19350                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_0                  931                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_1                11335                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_2                  596                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_3                 6488                       # number of overall MSHR misses
cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_2            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_3            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_2            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_3            0                       # number of overall MSHR uncacheable misses
cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.icache.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
cpu.icache.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.icache.read_accesses                      1234327                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_0                     347351                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_1                     185130                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_2                     382324                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_3                     319522                       # number of read accesses(hits+misses)
cpu.icache.read_avg_miss_latency                   25                       # average read miss latency
cpu.icache.read_avg_miss_latency_0          24.230134                       # average read miss latency
cpu.icache.read_avg_miss_latency_1          24.074617                       # average read miss latency
cpu.icache.read_avg_miss_latency_2          41.031532                       # average read miss latency
cpu.icache.read_avg_miss_latency_3          25.158499                       # average read miss latency
cpu.icache.read_avg_mshr_miss_latency       36.851628                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_0     33.846402                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_1     33.724041                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_2     59.877517                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_3     40.631782                       # average read mshr miss latency
cpu.icache.read_hits                          1213691                       # number of read hits
cpu.icache.read_hits_0                         346382                       # number of read hits
cpu.icache.read_hits_1                         173189                       # number of read hits
cpu.icache.read_hits_2                         381658                       # number of read hits
cpu.icache.read_hits_3                         312462                       # number of read hits
cpu.icache.read_miss_latency                   515900                       # number of read miss cycles
cpu.icache.read_miss_latency_0                  23479                       # number of read miss cycles
cpu.icache.read_miss_latency_1                 287475                       # number of read miss cycles
cpu.icache.read_miss_latency_2                  27327                       # number of read miss cycles
cpu.icache.read_miss_latency_3                 177619                       # number of read miss cycles
cpu.icache.read_miss_rate                    0.016718                       # miss rate for read accesses
cpu.icache.read_miss_rate_0                  0.002790                       # miss rate for read accesses
cpu.icache.read_miss_rate_1                  0.064501                       # miss rate for read accesses
cpu.icache.read_miss_rate_2                  0.001742                       # miss rate for read accesses
cpu.icache.read_miss_rate_3                  0.022096                       # miss rate for read accesses
cpu.icache.read_misses                          20636                       # number of read misses
cpu.icache.read_misses_0                          969                       # number of read misses
cpu.icache.read_misses_1                        11941                       # number of read misses
cpu.icache.read_misses_2                          666                       # number of read misses
cpu.icache.read_misses_3                         7060                       # number of read misses
cpu.icache.read_mshr_hits                        1286                       # number of read MSHR hits
cpu.icache.read_mshr_hits_0                        38                       # number of read MSHR hits
cpu.icache.read_mshr_hits_1                       606                       # number of read MSHR hits
cpu.icache.read_mshr_hits_2                        70                       # number of read MSHR hits
cpu.icache.read_mshr_hits_3                       572                       # number of read MSHR hits
cpu.icache.read_mshr_miss_latency              713079                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_0             31511                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_1            382262                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_2             35687                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_3            263619                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_rate               0.015677                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_0             0.002680                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_1             0.061227                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_2             0.001559                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_3             0.020305                       # mshr miss rate for read accesses
cpu.icache.read_mshr_misses                     19350                       # number of read MSHR misses
cpu.icache.read_mshr_misses_0                     931                       # number of read MSHR misses
cpu.icache.read_mshr_misses_1                   11335                       # number of read MSHR misses
cpu.icache.read_mshr_misses_2                     596                       # number of read MSHR misses
cpu.icache.read_mshr_misses_3                    6488                       # number of read MSHR misses
cpu.icache.replacements                         17228                       # number of replacements
cpu.icache.replacements_0                         843                       # number of replacements
cpu.icache.replacements_1                        9896                       # number of replacements
cpu.icache.replacements_2                         526                       # number of replacements
cpu.icache.replacements_3                        5963                       # number of replacements
cpu.icache.sampled_refs                         18245                       # Sample count of references to valid blocks.
cpu.icache.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_0                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_1                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_2                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_3                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.tagsinuse                       914.895666                       # Cycle average of tags in use
cpu.icache.total_refs                         1213691                       # Total number of references to valid blocks.
cpu.icache.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
cpu.icache.writebacks                               0                       # number of writebacks
cpu.icache.writebacks_0                             0                       # number of writebacks
cpu.icache.writebacks_1                             0                       # number of writebacks
cpu.icache.writebacks_2                             0                       # number of writebacks
cpu.icache.writebacks_3                             0                       # number of writebacks
cpu.iq:RQ:rdy_inst                            7419332                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_0                          2191786                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_1                          1095524                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_2                          2308106                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_3                          1823916                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_dist_0_mean               3.315232                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_0_stdev              3.300678                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_0_TOT        661126                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_1_mean               1.657058                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_1_stdev              2.938775                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_1_TOT        661126                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_2_mean               3.491174                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_2_stdev              2.922923                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_2_TOT        661126                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_3_mean               2.758802                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_3_stdev              3.481755                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_3_TOT        661126                       # standard deviation of ready rate
cpu.iq:RQ:rdy_rate                          11.222266                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_0                         3.315232                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_1                         1.657058                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_2                         3.491174                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_3                         2.758802                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_x_count                         3059397                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_0                        936719                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_1                        379837                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_2                       1048277                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_3                        694564                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_max                                31                       # largest number of insts that become ready
cpu.iq:RQ:rdy_x_rate                         4.627555                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_0                       1.416854                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_1                       0.574530                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_2                       1.585593                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_3                       1.050577                       # number of insts that become ready per cycle
cpu.iq:avg_residency                        10.006264                       # Average IQ residency
cpu.iq:avg_residency_0                      10.090124                       # Average IQ residency
cpu.iq:avg_residency_1                      16.503908                       # Average IQ residency
cpu.iq:avg_residency_2                       8.539241                       # Average IQ residency
cpu.iq:avg_residency_3                       8.659779                       # Average IQ residency
cpu.iq:cum_num_insts                         29920611                       # Total occupancy
cpu.iq:cum_num_insts_0                        9284609                       # Total occupancy
cpu.iq:cum_num_insts_1                        5965585                       # Total occupancy
cpu.iq:cum_num_insts_2                        8876020                       # Total occupancy
cpu.iq:cum_num_insts_3                        5794397                       # Total occupancy
cpu.iq:current_count                               64                       # Occupancy this cycle
cpu.iq:empty_count                               3280                       # Number of empty cycles
cpu.iq:empty_rate                            0.496123                       # Fraction of cycles empty
cpu.iq:full_count                              202758                       # Number of full cycles
cpu.iq:full_rate                            30.668587                       # Fraction of cycles full
cpu.iq:occ_dist_0.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_0.samples                      661126                      
cpu.iq:occ_dist_0.min_value                         0                      
                               0       102334              1547.87%
                               2        22413              1886.89%
                               4        24383              2255.70%
                               6        27692              2674.56%
                               8        42415              3316.12%
                              10        37567              3884.34%
                              12        46173              4582.74%
                              14        67009              5596.30%
                              16        67801              6621.84%
                              18        57674              7494.20%
                              20        45194              8177.79%
                              22        36831              8734.89%
                              24        17884              9005.39%
                              26         9828              9154.05%
                              28        10291              9309.71%
                              30        12265              9495.22%
                              32        11376              9667.29%
                              34         5547              9751.20%
                              36         2024              9781.81%
                              38         1544              9805.17%
                              40         1447              9827.05%
                              42         1520              9850.04%
                              44         2368              9885.86%
                              46         1376              9906.67%
                              48          839              9919.36%
                              50         1138              9936.58%
                              52         1497              9959.22%
                              54          631              9968.77%
                              56          405              9974.89%
                              58          355              9980.26%
                              60          427              9986.72%
                              62          263              9990.70%
                              64          615             10000.00%
cpu.iq:occ_dist_0.max_value                        64                      
cpu.iq:occ_dist_0.end_dist

cpu.iq:occ_dist_1.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_1.samples                      661126                      
cpu.iq:occ_dist_1.min_value                         0                      
                               0       271107              4100.69%
                               2        35562              4638.59%
                               4        24646              5011.37%
                               6        25394              5395.48%
                               8        27991              5818.86%
                              10        23210              6169.93%
                              12        29179              6611.28%
                              14        48282              7341.58%
                              16        50754              8109.27%
                              18        36345              8659.02%
                              20        18327              8936.22%
                              22        18656              9218.41%
                              24        14983              9445.04%
                              26         3906              9504.12%
                              28         4019              9564.91%
                              30         3335              9615.35%
                              32         6438              9712.73%
                              34         2789              9754.92%
                              36         1905              9783.73%
                              38         1659              9808.83%
                              40         1172              9826.55%
                              42         2166              9859.32%
                              44         1610              9883.67%
                              46         1874              9912.01%
                              48          807              9924.22%
                              50          856              9937.17%
                              52          869              9950.31%
                              54         1232              9968.95%
                              56          736              9980.08%
                              58          362              9985.55%
                              60           60              9986.46%
                              62           78              9987.64%
                              64          817             10000.00%
cpu.iq:occ_dist_1.max_value                        64                      
cpu.iq:occ_dist_1.end_dist

cpu.iq:occ_dist_2.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_2.samples                      661126                      
cpu.iq:occ_dist_2.min_value                         0                      
                               0        77039              1165.27%
                               2        27869              1586.81%
                               4        28860              2023.34%
                               6        36793              2579.86%
                               8        46731              3286.70%
                              10        42783              3933.82%
                              12        54386              4756.45%
                              14        72030              5845.95%
                              16        69994              6904.66%
                              18        62544              7850.68%
                              20        45328              8536.30%
                              22        32515              9028.11%
                              24        16366              9275.66%
                              26         9027              9412.20%
                              28         9477              9555.55%
                              30        11577              9730.66%
                              32         9481              9874.06%
                              34         4677              9944.81%
                              36          825              9957.28%
                              38          580              9966.06%
                              40          423              9972.46%
                              42          374              9978.11%
                              44          327              9983.06%
                              46          189              9985.92%
                              48          181              9988.66%
                              50          114              9990.38%
                              52           98              9991.86%
                              54           73              9992.97%
                              56           76              9994.12%
                              58          148              9996.35%
                              60           54              9997.17%
                              62           52              9997.96%
                              64          135             10000.00%
cpu.iq:occ_dist_2.max_value                        64                      
cpu.iq:occ_dist_2.end_dist

cpu.iq:occ_dist_3.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_3.samples                      661126                      
cpu.iq:occ_dist_3.min_value                         0                      
                               0       238953              3614.33%
                               2        30889              4081.55%
                               4        27211              4493.14%
                               6        27704              4912.18%
                               8        37053              5472.63%
                              10        30149              5928.66%
                              12        39520              6526.43%
                              14        59284              7423.14%
                              16        56021              8270.50%
                              18        43830              8933.46%
                              20        29163              9374.57%
                              22        19860              9674.96%
                              24         8368              9801.54%
                              26         2716              9842.62%
                              28         2362              9878.34%
                              30         2232              9912.10%
                              32         1972              9941.93%
                              34          989              9956.89%
                              36          380              9962.64%
                              38          318              9967.45%
                              40          509              9975.15%
                              42          237              9978.73%
                              44          195              9981.68%
                              46           82              9982.92%
                              48          244              9986.61%
                              50          117              9988.38%
                              52          158              9990.77%
                              54          139              9992.88%
                              56           23              9993.22%
                              58          119              9995.02%
                              60           23              9995.37%
                              62           24              9995.73%
                              64          282             10000.00%
cpu.iq:occ_dist_3.max_value                        64                      
cpu.iq:occ_dist_3.end_dist

cpu.iq:occ_rate                             45.257048                       # Average occupancy
cpu.iq:occ_rate_0                           14.043630                       # Average occupancy
cpu.iq:occ_rate_1                            9.023371                       # Average occupancy
cpu.iq:occ_rate_2                           13.425610                       # Average occupancy
cpu.iq:occ_rate_3                            8.764437                       # Average occupancy
cpu.iq:peak_occupancy                             256                       # Peak IQ occupancy
cpu.iq:peak_occupancy_0                            64                       # Peak IQ occupancy
cpu.iq:peak_occupancy_1                            64                       # Peak IQ occupancy
cpu.iq:peak_occupancy_2                            64                       # Peak IQ occupancy
cpu.iq:peak_occupancy_3                            64                       # Peak IQ occupancy
cpu.l2.avg_blocked_cycles_no_mshrs       <err: div-0>                       # average number of cycles each access was blocked
cpu.l2.avg_blocked_cycles_no_targets     <err: div-0>                       # average number of cycles each access was blocked
cpu.l2.avg_refs                          <err: div-0>                       # Average number of references to valid blocks.
cpu.l2.blocked_no_mshrs                             0                       # number of cycles access was blocked
cpu.l2.blocked_no_targets                           0                       # number of cycles access was blocked
cpu.l2.blocked_cycles_no_mshrs                      0                       # number of cycles access was blocked
cpu.l2.blocked_cycles_no_targets                    0                       # number of cycles access was blocked
cpu.l2.cache_copies                                 0                       # number of cache copies performed
cpu.l2.demand_accesses                          26345                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_0                         1653                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_1                        14819                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_2                         1390                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_3                         8483                       # number of demand (read+write) accesses
cpu.l2.demand_avg_miss_latency             128.053363                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_0           129.300554                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_1           127.931675                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_2           128.195980                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_3           127.898568                       # average overall miss latency
cpu.l2.demand_avg_mshr_miss_latency        114.030157                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_0      114.677285                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_1      113.984426                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_2      113.914573                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_3      113.973692                       # average overall mshr miss latency
cpu.l2.demand_hits                              17425                       # number of demand (read+write) hits
cpu.l2.demand_hits_0                              931                       # number of demand (read+write) hits
cpu.l2.demand_hits_1                            10838                       # number of demand (read+write) hits
cpu.l2.demand_hits_2                              594                       # number of demand (read+write) hits
cpu.l2.demand_hits_3                             5062                       # number of demand (read+write) hits
cpu.l2.demand_miss_latency                    1142236                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_0                    93355                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_1                   509296                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_2                   102044                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_3                   437541                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_rate                      0.338584                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_0                    0.436782                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_1                    0.268642                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_2                    0.572662                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_3                    0.403277                       # miss rate for demand accesses
cpu.l2.demand_misses                             8920                       # number of demand (read+write) misses
cpu.l2.demand_misses_0                            722                       # number of demand (read+write) misses
cpu.l2.demand_misses_1                           3981                       # number of demand (read+write) misses
cpu.l2.demand_misses_2                            796                       # number of demand (read+write) misses
cpu.l2.demand_misses_3                           3421                       # number of demand (read+write) misses
cpu.l2.demand_mshr_hits                             0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_0                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_1                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_2                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_3                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_miss_latency               1017149                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_0               82797                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_1              453772                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_2               90676                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_3              389904                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_rate                 0.338584                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_0               0.436782                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_1               0.268642                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_2               0.572662                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_3               0.403277                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_misses                        8920                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_0                       722                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_1                      3981                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_2                       796                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_3                      3421                       # number of demand (read+write) MSHR misses
cpu.l2.falru_accesses                           29422                       # The number of accesses to the FA LRU cache.
cpu.l2.falru_hits_128K                          14349                       # Hits in a 128K cache
cpu.l2.falru_hits_256K                          17539                       # Hits in a 256K cache
cpu.l2.falru_hits_512K                          19780                       # Hits in a 512K cache
cpu.l2.falru_hits_1M                            19799                       # Hits in a 1M cache
cpu.l2.falru_hits_2M                            19799                       # Hits in a 2M cache
cpu.l2.falru_misses_128K                        15073                       # Misses in a 128K cache
cpu.l2.falru_misses_256K                        11883                       # Misses in a 256K cache
cpu.l2.falru_misses_512K                         9642                       # Misses in a 512K cache
cpu.l2.falru_misses_1M                           9623                       # Misses in a 1M cache
cpu.l2.falru_misses_2M                           9623                       # Misses in a 2M cache
cpu.l2.fast_writes                                  0                       # number of fast writes performed
cpu.l2.mshr_cap_events                              0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_0                            0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_1                            0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_2                            0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_3                            0                       # number of times MSHR cap was activated
cpu.l2.no_allocate_misses                           0                       # Number of misses that were no-allocate
cpu.l2.overall_accesses                         29422                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_0                        1709                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_1                       15213                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_2                        1771                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_3                       10729                       # number of overall (read+write) accesses
cpu.l2.overall_avg_miss_latency            118.698535                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_0          129.300554                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_1          127.292177                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_2          128.195980                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_3          106.613304                       # average overall miss latency
cpu.l2.overall_avg_mshr_miss_latency       114.030157                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_0     114.677285                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_1     113.984426                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_2     113.914573                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_3     113.973692                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_2 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_3 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_hits                             19799                       # number of overall hits
cpu.l2.overall_hits_0                             987                       # number of overall hits
cpu.l2.overall_hits_1                           11212                       # number of overall hits
cpu.l2.overall_hits_2                             975                       # number of overall hits
cpu.l2.overall_hits_3                            6625                       # number of overall hits
cpu.l2.overall_miss_latency                   1142236                       # number of overall miss cycles
cpu.l2.overall_miss_latency_0                   93355                       # number of overall miss cycles
cpu.l2.overall_miss_latency_1                  509296                       # number of overall miss cycles
cpu.l2.overall_miss_latency_2                  102044                       # number of overall miss cycles
cpu.l2.overall_miss_latency_3                  437541                       # number of overall miss cycles
cpu.l2.overall_miss_rate                     0.327068                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_0                   0.422469                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_1                   0.262999                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_2                   0.449464                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_3                   0.382515                       # miss rate for overall accesses
cpu.l2.overall_misses                            9623                       # number of overall misses
cpu.l2.overall_misses_0                           722                       # number of overall misses
cpu.l2.overall_misses_1                          4001                       # number of overall misses
cpu.l2.overall_misses_2                           796                       # number of overall misses
cpu.l2.overall_misses_3                          4104                       # number of overall misses
cpu.l2.overall_mshr_hits                            0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_0                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_1                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_2                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_3                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_miss_latency              1017149                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_0              82797                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_1             453772                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_2              90676                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_3             389904                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_rate                0.303174                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_0              0.422469                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_1              0.261684                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_2              0.449464                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_3              0.318855                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_misses                       8920                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_0                      722                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_1                     3981                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_2                      796                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_3                     3421                       # number of overall MSHR misses
cpu.l2.overall_mshr_uncacheable_latency             0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_2            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_3            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_misses              0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_2            0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_3            0                       # number of overall MSHR uncacheable misses
cpu.l2.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.l2.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.l2.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.l2.prefetcher.num_hwpf_evicted                  0                       # number of hwpf removed due to no buffer left
cpu.l2.prefetcher.num_hwpf_identified               0                       # number of hwpf identified
cpu.l2.prefetcher.num_hwpf_issued                   0                       # number of hwpf issued
cpu.l2.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.l2.prefetcher.num_hwpf_span_page                0                       # number of hwpf spanning a virtual page
cpu.l2.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.l2.read_accesses                            26345                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_0                           1653                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_1                          14819                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_2                           1390                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_3                           8483                       # number of read accesses(hits+misses)
cpu.l2.read_avg_miss_latency               128.053363                       # average read miss latency
cpu.l2.read_avg_miss_latency_0             129.300554                       # average read miss latency
cpu.l2.read_avg_miss_latency_1             127.931675                       # average read miss latency
cpu.l2.read_avg_miss_latency_2             128.195980                       # average read miss latency
cpu.l2.read_avg_miss_latency_3             127.898568                       # average read miss latency
cpu.l2.read_avg_mshr_miss_latency          114.030157                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_0        114.677285                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_1        113.984426                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_2        113.914573                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_3        113.973692                       # average read mshr miss latency
cpu.l2.read_hits                                17425                       # number of read hits
cpu.l2.read_hits_0                                931                       # number of read hits
cpu.l2.read_hits_1                              10838                       # number of read hits
cpu.l2.read_hits_2                                594                       # number of read hits
cpu.l2.read_hits_3                               5062                       # number of read hits
cpu.l2.read_miss_latency                      1142236                       # number of read miss cycles
cpu.l2.read_miss_latency_0                      93355                       # number of read miss cycles
cpu.l2.read_miss_latency_1                     509296                       # number of read miss cycles
cpu.l2.read_miss_latency_2                     102044                       # number of read miss cycles
cpu.l2.read_miss_latency_3                     437541                       # number of read miss cycles
cpu.l2.read_miss_rate                        0.338584                       # miss rate for read accesses
cpu.l2.read_miss_rate_0                      0.436782                       # miss rate for read accesses
cpu.l2.read_miss_rate_1                      0.268642                       # miss rate for read accesses
cpu.l2.read_miss_rate_2                      0.572662                       # miss rate for read accesses
cpu.l2.read_miss_rate_3                      0.403277                       # miss rate for read accesses
cpu.l2.read_misses                               8920                       # number of read misses
cpu.l2.read_misses_0                              722                       # number of read misses
cpu.l2.read_misses_1                             3981                       # number of read misses
cpu.l2.read_misses_2                              796                       # number of read misses
cpu.l2.read_misses_3                             3421                       # number of read misses
cpu.l2.read_mshr_miss_latency                 1017149                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_0                 82797                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_1                453772                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_2                 90676                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_3                389904                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_rate                   0.338584                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_0                 0.436782                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_1                 0.268642                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_2                 0.572662                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_3                 0.403277                       # mshr miss rate for read accesses
cpu.l2.read_mshr_misses                          8920                       # number of read MSHR misses
cpu.l2.read_mshr_misses_0                         722                       # number of read MSHR misses
cpu.l2.read_mshr_misses_1                        3981                       # number of read MSHR misses
cpu.l2.read_mshr_misses_2                         796                       # number of read MSHR misses
cpu.l2.read_mshr_misses_3                        3421                       # number of read MSHR misses
cpu.l2.replacements                                 0                       # number of replacements
cpu.l2.replacements_0                               0                       # number of replacements
cpu.l2.replacements_1                               0                       # number of replacements
cpu.l2.replacements_2                               0                       # number of replacements
cpu.l2.replacements_3                               0                       # number of replacements
cpu.l2.sampled_refs                                 0                       # Sample count of references to valid blocks.
cpu.l2.soft_prefetch_mshr_full                      0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_0                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_1                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_2                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_3                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.tagsinuse                          5610.008469                       # Cycle average of tags in use
cpu.l2.total_refs                                   0                       # Total number of references to valid blocks.
cpu.l2.warmup_cycle                                 0                       # Cycle when the warmup percentage was hit.
cpu.l2.writeback_accesses                        3077                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_0                        56                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_1                       394                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_2                       381                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_3                      2246                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_hits                            2374                       # number of writeback hits
cpu.l2.writeback_hits_0                            56                       # number of writeback hits
cpu.l2.writeback_hits_1                           374                       # number of writeback hits
cpu.l2.writeback_hits_2                           381                       # number of writeback hits
cpu.l2.writeback_hits_3                          1563                       # number of writeback hits
cpu.l2.writeback_miss_rate                   0.228469                       # miss rate for writeback accesses
cpu.l2.writeback_miss_rate_1                 0.050761                       # miss rate for writeback accesses
cpu.l2.writeback_miss_rate_3                 0.304096                       # miss rate for writeback accesses
cpu.l2.writeback_misses                           703                       # number of writeback misses
cpu.l2.writeback_misses_1                          20                       # number of writeback misses
cpu.l2.writeback_misses_3                         683                       # number of writeback misses
cpu.l2.writeback_mshr_miss_rate              0.228469                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_miss_rate_1            0.050761                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_miss_rate_3            0.304096                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_misses                      703                       # number of writeback MSHR misses
cpu.l2.writeback_mshr_misses_1                     20                       # number of writeback MSHR misses
cpu.l2.writeback_mshr_misses_3                    683                       # number of writeback MSHR misses
cpu.l2.writebacks                                   0                       # number of writebacks
cpu.l2.writebacks_0                                 0                       # number of writebacks
cpu.l2.writebacks_1                                 0                       # number of writebacks
cpu.l2.writebacks_2                                 0                       # number of writebacks
cpu.l2.writebacks_3                                 0                       # number of writebacks
cpu.numCycles                                  661126                       # number of cpu cycles simulated
cpu.toL2Bus.addr_idle_cycles                   631694                       # number of cycles bus was idle
cpu.toL2Bus.addr_idle_fraction               0.955483                       # fraction of time addr bus was idle
cpu.toL2Bus.addr_queued                      3.401332                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_0                    3.850205                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_1                    3.475383                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_2                    3.683230                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_3                    3.178302                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_cycles                 100074                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_0                 6580                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_1                52871                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_2                 6523                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_3                34100                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_requests                       29422                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_0                      1709                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_1                     15213                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_2                      1771                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_3                     10729                       # number of transmissions on bus
cpu.toL2Bus.bus_blocked                             0                       # number of times bus was blocked
cpu.toL2Bus.bus_blocked_cycles                      0                       # number of cycles bus was blocked
cpu.toL2Bus.bus_blocked_fraction                    0                       # fraction of time bus was blocked
cpu.toL2Bus.data_idle_cycles                   631618                       # number of cycles bus was idle
cpu.toL2Bus.data_idle_fraction               0.955369                       # fraction of time data bus was idle
cpu.toL2Bus.data_queued                      1.023573                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_0                    1.015729                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_1                    1.021661                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_2                    1.022302                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_3                    1.028649                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_cycles                  26965                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_0                 1679                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_1                15140                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_2                 1421                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_3                 8725                       # total number of queued cycles for all requests
cpu.toL2Bus.data_requests                       26344                       # number of transmissions on bus
cpu.toL2Bus.data_requests_0                      1653                       # number of transmissions on bus
cpu.toL2Bus.data_requests_1                     14819                       # number of transmissions on bus
cpu.toL2Bus.data_requests_2                      1390                       # number of transmissions on bus
cpu.toL2Bus.data_requests_3                      8482                       # number of transmissions on bus
cpu.toL2Bus.null_grants                           693                       # number of null grants (wasted cycles)
cpu.workload0.MainMem.page_count                    0                       # total number of pages allocated
cpu.workload0.MainMem.page_mem                      0                       # total size of memory pages allocated
cpu.workload0.MainMem.ptab_accesses           1988946                       # total page table accessess
cpu.workload0.MainMem.ptab_miss_rate           0.0081                       # first level page table miss rate
cpu.workload0.MainMem.ptab_misses               16102                       # total first level page table misses
cpu.workload0.PROG:num_syscalls                   639                       # Number of system calls
cpu.workload1.MainMem.page_count                    1                       # total number of pages allocated
cpu.workload1.MainMem.page_mem                      8                       # total size of memory pages allocated
cpu.workload1.MainMem.ptab_accesses           1010381                       # total page table accessess
cpu.workload1.MainMem.ptab_miss_rate           0.0085                       # first level page table miss rate
cpu.workload1.MainMem.ptab_misses                8587                       # total first level page table misses
cpu.workload1.PROG:num_syscalls                    68                       # Number of system calls
cpu.workload2.MainMem.page_count                    8                       # total number of pages allocated
cpu.workload2.MainMem.page_mem                     64                       # total size of memory pages allocated
cpu.workload2.MainMem.ptab_accesses           1948322                       # total page table accessess
cpu.workload2.MainMem.ptab_miss_rate           0.0951                       # first level page table miss rate
cpu.workload2.MainMem.ptab_misses              185298                       # total first level page table misses
cpu.workload2.PROG:num_syscalls                    13                       # Number of system calls
cpu.workload3.MainMem.page_count                   30                       # total number of pages allocated
cpu.workload3.MainMem.page_mem                    240                       # total size of memory pages allocated
cpu.workload3.MainMem.ptab_accesses           1650702                       # total page table accessess
cpu.workload3.MainMem.ptab_miss_rate           0.0041                       # first level page table miss rate
cpu.workload3.MainMem.ptab_misses                6697                       # total first level page table misses
cpu.workload3.PROG:num_syscalls                    13                       # Number of system calls
cpuinst_class_dist.start_dist
                   All ops ready            0      0.00%            # Operand status at dispatch
                One op not ready            0      0.00%            # Operand status at dispatch
           None rdy, mult chains            0      0.00%            # Operand status at dispatch
           None rdy, one chained            0      0.00%            # Operand status at dispatch
        None rdy, all self-timed            0      0.00%            # Operand status at dispatch
cpuinst_class_dist.end_dist
host_inst_rate                                  69042                       # Simulator instruction rate (inst/s)
host_mem_usage                                  22804                       # Number of bytes of host memory used
host_seconds                                    39.49                       # Real time elapsed on the host
host_tick_rate                                  16741                       # Simulator tick rate (ticks/s)
ram.accesses                                     9623                       # total number of accesses
ram.accesses_0                                    722                       # total number of accesses
ram.accesses_1                                   4001                       # total number of accesses
ram.accesses_2                                    796                       # total number of accesses
ram.accesses_3                                   4104                       # total number of accesses
ram.bytes_requested                                 0                       # total number of bytes requested
ram.bytes_requested_0                               0                       # total number of bytes requested
ram.bytes_requested_1                               0                       # total number of bytes requested
ram.bytes_requested_2                               0                       # total number of bytes requested
ram.bytes_requested_3                               0                       # total number of bytes requested
ram.bytes_sent                                      0                       # total number of bytes sent
ram.bytes_sent_0                                    0                       # total number of bytes sent
ram.bytes_sent_1                                    0                       # total number of bytes sent
ram.bytes_sent_2                                    0                       # total number of bytes sent
ram.bytes_sent_3                                    0                       # total number of bytes sent
ram.compressed_responses                            0                       # total number of accesses that are compressed
ram.compressed_responses_0                          0                       # total number of accesses that are compressed
ram.compressed_responses_1                          0                       # total number of accesses that are compressed
ram.compressed_responses_2                          0                       # total number of accesses that are compressed
ram.compressed_responses_3                          0                       # total number of accesses that are compressed
sim_freq                                    200000000                       # Frequency of simulated ticks
sim_insts                                     2726458                       # Number of instructions simulated
sim_seconds                                  0.003306                       # Number of seconds simulated
sim_ticks                                      661125                       # Number of ticks simulated
toMemBus.addr_idle_cycles                      650221                       # number of cycles bus was idle
toMemBus.addr_idle_fraction                  0.983507                       # fraction of time addr bus was idle
toMemBus.addr_queued                        11.004261                       # average queueing delay seen by bus request
toMemBus.addr_queued_0                      10.785319                       # average queueing delay seen by bus request
toMemBus.addr_queued_1                      11.049988                       # average queueing delay seen by bus request
toMemBus.addr_queued_2                      10.924623                       # average queueing delay seen by bus request
toMemBus.addr_queued_3                      11.013645                       # average queueing delay seen by bus request
toMemBus.addr_queued_cycles                    105894                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_0                    7787                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_1                   44211                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_2                    8696                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_3                   45200                       # total number of queued cycles for all requests
toMemBus.addr_requests                           9623                       # number of transmissions on bus
toMemBus.addr_requests_0                          722                       # number of transmissions on bus
toMemBus.addr_requests_1                         4001                       # number of transmissions on bus
toMemBus.addr_requests_2                          796                       # number of transmissions on bus
toMemBus.addr_requests_3                         4104                       # number of transmissions on bus
toMemBus.bus_blocked                                0                       # number of times bus was blocked
toMemBus.bus_blocked_cycles                         0                       # number of cycles bus was blocked
toMemBus.bus_blocked_fraction                       0                       # fraction of time bus was blocked
toMemBus.data_idle_cycles                      621456                       # number of cycles bus was idle
toMemBus.data_idle_fraction                  0.939998                       # fraction of time data bus was idle
toMemBus.data_queued                         2.043722                       # average queueing delay seen by bus request
toMemBus.data_queued_0                       2.891967                       # average queueing delay seen by bus request
toMemBus.data_queued_1                       1.939211                       # average queueing delay seen by bus request
toMemBus.data_queued_2                       1.989950                       # average queueing delay seen by bus request
toMemBus.data_queued_3                       1.998831                       # average queueing delay seen by bus request
toMemBus.data_queued_cycles                     18230                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_0                    2088                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_1                    7720                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_2                    1584                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_3                    6838                       # total number of queued cycles for all requests
toMemBus.data_requests                           8920                       # number of transmissions on bus
toMemBus.data_requests_0                          722                       # number of transmissions on bus
toMemBus.data_requests_1                         3981                       # number of transmissions on bus
toMemBus.data_requests_2                          796                       # number of transmissions on bus
toMemBus.data_requests_3                         3421                       # number of transmissions on bus
toMemBus.null_grants                                0                       # number of null grants (wasted cycles)

---------- End Simulation Statistics   ----------
