
---------- Begin Simulation Statistics ----------
cpu.COM:IPB                                  6.499129                       # Committed instructions per branch
cpu.COM:IPB_0                                5.674010                       # Committed instructions per branch
cpu.COM:IPB_1                                6.325511                       # Committed instructions per branch
cpu.COM:IPB_2                                7.861951                       # Committed instructions per branch
cpu.COM:IPB_3                                6.211598                       # Committed instructions per branch
cpu.COM:IPC                                  3.876943                       # Committed instructions per cycle
cpu.COM:IPC_0                                1.448143                       # Committed instructions per cycle
cpu.COM:IPC_1                                0.298595                       # Committed instructions per cycle
cpu.COM:IPC_2                                1.445097                       # Committed instructions per cycle
cpu.COM:IPC_3                                0.685108                       # Committed instructions per cycle
cpu.COM:branches                               199780                       # Number of branches committed
cpu.COM:branches_0                              85475                       # Number of branches committed
cpu.COM:branches_1                              15809                       # Number of branches committed
cpu.COM:branches_2                              61558                       # Number of branches committed
cpu.COM:branches_3                              36938                       # Number of branches committed
cpu.COM:bw_lim_avg                            18.1304                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_0                           5.0126                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_1                           1.6390                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_2                           8.0078                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_3                           3.4709                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_events                           81482                       # number cycles where commit BW limit reached
cpu.COM:bw_lim_rate                            4.4112                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_0                          1.2196                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_1                          0.3988                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_2                          1.9483                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_3                          0.8445                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_stdev_0_mean                    5.0126                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_0_stdev                   7.3592                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_0_TOT       81482.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_1_mean                    1.6390                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_1_stdev                   7.0014                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_1_TOT       81482.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_2_mean                    8.0078                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_2_stdev                  16.8989                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_2_TOT       81482.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_3_mean                    3.4709                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_3_stdev                  11.6528                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_3_TOT       81482.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_limited                            1477303                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_0                           408440                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_1                           133553                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_2                           652492                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_3                           282818                       # number of insts not committed due to BW limits
cpu.COM:committed_per_cycle.start_dist                         # Number of insts commited each cycle
cpu.COM:committed_per_cycle.samples            267738                      
cpu.COM:committed_per_cycle.min_value               0                      
                               0         1060     39.59%           
                               1        40186   1500.94%           
                               2        32779   1224.29%           
                               3        30294   1131.48%           
                               4        26389    985.63%           
                               5        18226    680.74%           
                               6        15746    588.11%           
                               7        11603    433.37%           
                               8        91455   3415.84%           
cpu.COM:committed_per_cycle.max_value               8                      
cpu.COM:committed_per_cycle.end_dist

cpu.COM:count                                 1298396                       # Number of instructions committed
cpu.COM:count_0                                484986                       # Number of instructions committed
cpu.COM:count_1                                100000                       # Number of instructions committed
cpu.COM:count_2                                483966                       # Number of instructions committed
cpu.COM:count_3                                229444                       # Number of instructions committed
cpu.COM:loads                                  336320                       # Number of loads committed
cpu.COM:loads_0                                147538                       # Number of loads committed
cpu.COM:loads_1                                 26002                       # Number of loads committed
cpu.COM:loads_2                                123857                       # Number of loads committed
cpu.COM:loads_3                                 38923                       # Number of loads committed
cpu.COM:membars                                     0                       # Number of memory barriers committed
cpu.COM:membars_0                                   0                       # Number of memory barriers committed
cpu.COM:membars_1                                   0                       # Number of memory barriers committed
cpu.COM:membars_2                                   0                       # Number of memory barriers committed
cpu.COM:membars_3                                   0                       # Number of memory barriers committed
cpu.COM:refs                                   482160                       # Number of memory references committed
cpu.COM:refs_0                                 195357                       # Number of memory references committed
cpu.COM:refs_1                                  36320                       # Number of memory references committed
cpu.COM:refs_2                                 179689                       # Number of memory references committed
cpu.COM:refs_3                                  70794                       # Number of memory references committed
cpu.COM:stores                                 145840                       # Number of stores committed
cpu.COM:stores_0                                47819                       # Number of stores committed
cpu.COM:stores_1                                10318                       # Number of stores committed
cpu.COM:stores_2                                55832                       # Number of stores committed
cpu.COM:stores_3                                31871                       # Number of stores committed
cpu.COM:swp_count                                2253                       # Number of s/w prefetches committed
cpu.COM:swp_count_0                                 0                       # Number of s/w prefetches committed
cpu.COM:swp_count_1                               248                       # Number of s/w prefetches committed
cpu.COM:swp_count_2                                16                       # Number of s/w prefetches committed
cpu.COM:swp_count_3                              1989                       # Number of s/w prefetches committed
cpu.DDQ:count                                81821878                       # cum count of instructions
cpu.DDQ:count_0                              25114574                       # cum count of instructions
cpu.DDQ:count_1                              16388649                       # cum count of instructions
cpu.DDQ:count_2                              23831760                       # cum count of instructions
cpu.DDQ:count_3                              16486895                       # cum count of instructions
cpu.DDQ:rate                                      244                       # average number of instructions
cpu.DDQ:rate_0                                     75                       # average number of instructions
cpu.DDQ:rate_1                                     49                       # average number of instructions
cpu.DDQ:rate_2                                     71                       # average number of instructions
cpu.DDQ:rate_3                                     49                       # average number of instructions
cpu.DIS:chain_creation.start_dist
     Inst has no outstanding IDEPS            0      0.00%            # Reason that chain head was created
      IDEP chain reached max depth            0      0.00%            # Reason that chain head was created
                    Inst is a load            0      0.00%            # Reason that chain head was created
  Chain has multiple chained IDEPS            0      0.00%            # Reason that chain head was created
cpu.DIS:chain_creation.end_dist
cpu.DIS:chain_head_frac                             0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_0                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_1                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_2                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_3                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_heads                                 0                       # number insts that are chain heads
cpu.DIS:chain_heads_0                               0                       # number insts that are chain heads
cpu.DIS:chain_heads_1                               0                       # number insts that are chain heads
cpu.DIS:chain_heads_2                               0                       # number insts that are chain heads
cpu.DIS:chain_heads_3                               0                       # number insts that are chain heads
cpu.DIS:chains_insuf                                0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_0                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_1                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_2                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_3                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_rate                           0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_0                         0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_1                         0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_2                         0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_3                         0                       # rate that thread had insuf chains
cpu.DIS:count                                 1577787                       # cumulative count of dispatched insts
cpu.DIS:count_0                                581127                       # cumulative count of dispatched insts
cpu.DIS:count_1                                153361                       # cumulative count of dispatched insts
cpu.DIS:count_2                                524474                       # cumulative count of dispatched insts
cpu.DIS:count_3                                318825                       # cumulative count of dispatched insts
cpu.DIS:insufficient_chains                         0                       # Number of instances where dispatch stopped
cpu.DIS:mod_n_stall_avg_free                 no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_0               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_1               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_2               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_3               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_frac                            0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_0                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_1                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_2                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_3                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_free                            0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_0                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_1                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_2                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_3                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls                                0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_0                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_1                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_2                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_3                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:one_rdy_insts                               0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_0                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_1                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_2                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_3                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_ratio                        no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_0                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_1                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_2                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_3                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:op_count                              2160675                       # number of operations dispatched
cpu.DIS:op_count_0                             815999                       # number of operations dispatched
cpu.DIS:op_count_1                             209815                       # number of operations dispatched
cpu.DIS:op_count_2                             720401                       # number of operations dispatched
cpu.DIS:op_count_3                             414460                       # number of operations dispatched
cpu.DIS:op_rate                              6.451663                       # dispatched operations per cycle
cpu.DIS:op_rate_0                            2.436531                       # dispatched operations per cycle
cpu.DIS:op_rate_1                            0.626497                       # dispatched operations per cycle
cpu.DIS:op_rate_2                            2.151080                       # dispatched operations per cycle
cpu.DIS:op_rate_3                            1.237556                       # dispatched operations per cycle
cpu.DIS:rate                                 4.711190                       # dispatched_insts per cycle
cpu.DIS:rate_0                               1.735215                       # dispatched_insts per cycle
cpu.DIS:rate_1                               0.457928                       # dispatched_insts per cycle
cpu.DIS:rate_2                               1.566052                       # dispatched_insts per cycle
cpu.DIS:rate_3                               0.951995                       # dispatched_insts per cycle
cpu.DIS:second_choice_clust                         0                       # Number of instructions dispatched to second-choice cluster
cpu.DIS:second_choice_stall                         0                       # Number of instructions stalled when first choice not available
cpu.DIS:serialize_stall_cycles                      0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_0                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_1                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_2                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_3                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serializing_insts                           0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_0                         0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_1                         0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_2                         0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_3                         0                       # count of serializing insts dispatched
cpu.DIS:two_input_insts                             0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_0                           0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_1                           0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_2                           0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_3                           0                       # Number of two input instructions queued
cpu.DIS:two_input_ratio                             0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_0                           0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_1                           0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_2                           0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_3                           0                       # fraction of all insts having 2 inputs
cpu.FETCH:branch_count                         317761                       # Number of branches fetched
cpu.FETCH:branch_count_0                       129448                       # Number of branches fetched
cpu.FETCH:branch_count_1                        34646                       # Number of branches fetched
cpu.FETCH:branch_count_2                        77606                       # Number of branches fetched
cpu.FETCH:branch_count_3                        76061                       # Number of branches fetched
cpu.FETCH:branch_rate                        0.948818                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_0                      0.386525                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_1                      0.103451                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_2                      0.231727                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_3                      0.227114                       # Number of branch fetches per cycle
cpu.FETCH:chance_pct_0                       0.365522                       # Percentage of all fetch chances
cpu.FETCH:chance_pct_1                       0.118582                       # Percentage of all fetch chances
cpu.FETCH:chance_pct_2                       0.274006                       # Percentage of all fetch chances
cpu.FETCH:chance_pct_3                       0.241890                       # Percentage of all fetch chances
cpu.FETCH:chances                              314077                       # Number of fetch opportunities
cpu.FETCH:chances_0                            114802                       # Number of fetch opportunities
cpu.FETCH:chances_1                             37244                       # Number of fetch opportunities
cpu.FETCH:chances_2                             86059                       # Number of fetch opportunities
cpu.FETCH:chances_3                             75972                       # Number of fetch opportunities
cpu.FETCH:choice                               314077                       # Number of times we fetched from our first choice
cpu.FETCH:choice.start_dist
                               0       314077    100.00%            # Number of times we fetched from our first choice
                               1            0      0.00%            # Number of times we fetched from our first choice
                               2            0      0.00%            # Number of times we fetched from our first choice
                               3            0      0.00%            # Number of times we fetched from our first choice
cpu.FETCH:choice.end_dist
cpu.FETCH:count                               2383379                       # Number of instructions fetched
cpu.FETCH:count_0                              831937                       # Number of instructions fetched
cpu.FETCH:count_1                              290820                       # Number of instructions fetched
cpu.FETCH:count_2                              665949                       # Number of instructions fetched
cpu.FETCH:count_3                              594673                       # Number of instructions fetched
cpu.FETCH:decisions                            314077                       # number of times the fetch stage chose between threads
cpu.FETCH:idle_cycles                           20825                       # number of cycles where fetch stage was idle
cpu.FETCH:idle_icache_blocked_cycles                0                       # number of cycles where fetch was idle due to icache blocked
cpu.FETCH:idle_rate                              6.22                       # percent of cycles fetch stage was idle
cpu.FETCH:prio_changes                              0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_0                            0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_1                            0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_2                            0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_3                            0                       # Number of times priorities were changed
cpu.FETCH:rate                               7.116646                       # Number of inst fetches per cycle
cpu.FETCH:rate_0                             2.484121                       # Number of inst fetches per cycle
cpu.FETCH:rate_1                             0.868373                       # Number of inst fetches per cycle
cpu.FETCH:rate_2                             1.988489                       # Number of inst fetches per cycle
cpu.FETCH:rate_3                             1.775663                       # Number of inst fetches per cycle
cpu.FETCH:rate_dist.start_dist                                 # Number of instructions fetched each cycle (Total)
cpu.FETCH:rate_dist.samples                    314077                      
cpu.FETCH:rate_dist.min_value                       0                      
                               0         1071     34.10%           
                               1         1340     42.66%           
                               2         1504     47.89%           
                               3         1870     59.54%           
                               4         3244    103.29%           
                               5         4827    153.69%           
                               6        30316    965.24%           
                               7         4826    153.66%           
                               8       265079   8439.94%           
cpu.FETCH:rate_dist.max_value                       8                      
cpu.FETCH:rate_dist.end_dist

cpu.FETCH:rate_dist_0.start_dist                               # Number of instructions fetched each cycle (Thread 0)
cpu.FETCH:rate_dist_0.samples                  114802                      
cpu.FETCH:rate_dist_0.min_value                     0                      
                               0          649     56.53%           
                               1          795     69.25%           
                               2          856     74.56%           
                               3          975     84.93%           
                               4         1409    122.73%           
                               5         2614    227.70%           
                               6        25074   2184.11%           
                               7         2085    181.62%           
                               8        80345   6998.57%           
cpu.FETCH:rate_dist_0.max_value                     8                      
cpu.FETCH:rate_dist_0.end_dist

cpu.FETCH:rate_dist_1.start_dist                               # Number of instructions fetched each cycle (Thread 1)
cpu.FETCH:rate_dist_1.samples                   37244                      
cpu.FETCH:rate_dist_1.min_value                     0                      
                               0          255     68.47%           
                               1           71     19.06%           
                               2           93     24.97%           
                               3          144     38.66%           
                               4          327     87.80%           
                               5          194     52.09%           
                               6          383    102.84%           
                               7          661    177.48%           
                               8        35116   9428.63%           
cpu.FETCH:rate_dist_1.max_value                     8                      
cpu.FETCH:rate_dist_1.end_dist

cpu.FETCH:rate_dist_2.start_dist                               # Number of instructions fetched each cycle (Thread 2)
cpu.FETCH:rate_dist_2.samples                   86059                      
cpu.FETCH:rate_dist_2.min_value                     1                      
                               0            0      0.00%           
                               1          281     32.65%           
                               2          349     40.55%           
                               3          536     62.28%           
                               4          998    115.97%           
                               5         1437    166.98%           
                               6         3366    391.13%           
                               7          747     86.80%           
                               8        78345   9103.64%           
cpu.FETCH:rate_dist_2.max_value                     8                      
cpu.FETCH:rate_dist_2.end_dist

cpu.FETCH:rate_dist_3.start_dist                               # Number of instructions fetched each cycle (Thread 3)
cpu.FETCH:rate_dist_3.samples                   75972                      
cpu.FETCH:rate_dist_3.min_value                     0                      
                               0          167     21.98%           
                               1          193     25.40%           
                               2          206     27.12%           
                               3          215     28.30%           
                               4          510     67.13%           
                               5          582     76.61%           
                               6         1493    196.52%           
                               7         1333    175.46%           
                               8        71273   9381.48%           
cpu.FETCH:rate_dist_3.max_value                     8                      
cpu.FETCH:rate_dist_3.end_dist

cpu.IFQ:count                                15461965                       # cumulative IFQ occupancy
cpu.IFQ:full_count                             182492                       # cumulative IFQ full count
cpu.IFQ:full_count_0                            50622                       # cumulative IFQ full count
cpu.IFQ:full_count_1                            54287                       # cumulative IFQ full count
cpu.IFQ:full_count_2                            53574                       # cumulative IFQ full count
cpu.IFQ:full_count_3                            24009                       # cumulative IFQ full count
cpu.IFQ:full_rate                           54.491165                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_0                         15.115467                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_1                         16.209817                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_2                         15.996919                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_3                          7.168963                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:latency                              9.799780                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_0                           26.606860                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_1                          100.820711                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_2                           29.480899                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_3                           48.496714                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:occupancy                           46.168625                       # avg IFQ occupancy (inst's)
cpu.IFQ:qfull_iq_occ                          6879338                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_0                        1791844                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_1                        2297646                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_2                        1891615                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_3                         898233                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_0.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_0.samples            151433                      
cpu.IFQ:qfull_iq_occ_dist_0.min_value               0                      
                               0        64489   4258.58%           
                              10        64301   4246.17%           
                              20        17073   1127.43%           
                              30         4056    267.84%           
                              40          764     50.45%           
                              50          745     49.20%           
                              60            5      0.33%           
cpu.IFQ:qfull_iq_occ_dist_0.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_0.end_dist

cpu.IFQ:qfull_iq_occ_dist_1.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_1.samples            151433                      
cpu.IFQ:qfull_iq_occ_dist_1.min_value               0                      
                               0        54369   3590.30%           
                              10        49347   3258.67%           
                              20        31373   2071.74%           
                              30         8929    589.63%           
                              40         3826    252.65%           
                              50         2306    152.28%           
                              60         1283     84.72%           
cpu.IFQ:qfull_iq_occ_dist_1.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_1.end_dist

cpu.IFQ:qfull_iq_occ_dist_2.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_2.samples            151433                      
cpu.IFQ:qfull_iq_occ_dist_2.min_value               0                      
                               0        58623   3871.22%           
                              10        68807   4543.73%           
                              20        19863   1311.67%           
                              30         3756    248.03%           
                              40          186     12.28%           
                              50          169     11.16%           
                              60           29      1.92%           
cpu.IFQ:qfull_iq_occ_dist_2.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_2.end_dist

cpu.IFQ:qfull_iq_occ_dist_3.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_3.samples            151433                      
cpu.IFQ:qfull_iq_occ_dist_3.min_value               0                      
                               0       103849   6857.75%           
                              10        43457   2869.72%           
                              20         3603    237.93%           
                              30          356     23.51%           
                              40           39      2.58%           
                              50          121      7.99%           
                              60            8      0.53%           
cpu.IFQ:qfull_iq_occ_dist_3.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_3.end_dist

cpu.IFQ:qfull_rob_occ                        16357112                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_0                       4235464                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_1                       3558344                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_2                       5798396                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_3                       2764908                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_0.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_0.samples           151433                      
cpu.IFQ:qfull_rob_occ_dist_0.min_value              0                      
                               0        23994   1584.46%           
                              10        22960   1516.18%           
                              20        42537   2808.97%           
                              30        29560   1952.02%           
                              40        20290   1339.87%           
                              50         6799    448.98%           
                              60         2489    164.36%           
                              70          591     39.03%           
                              80          373     24.63%           
                              90          119      7.86%           
                             100           33      2.18%           
                             110          201     13.27%           
                             120           25      1.65%           
                             130           19      1.25%           
                             140          112      7.40%           
                             150           71      4.69%           
                             160           95      6.27%           
                             170           77      5.08%           
                             180          720     47.55%           
                             190          368     24.30%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_0.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_0.end_dist

cpu.IFQ:qfull_rob_occ_dist_1.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_1.samples           151433                      
cpu.IFQ:qfull_rob_occ_dist_1.min_value              0                      
                               0        37244   2459.44%           
                              10        16544   1092.50%           
                              20        52018   3435.05%           
                              30        26484   1748.89%           
                              40         8183    540.37%           
                              50         5161    340.81%           
                              60         2892    190.98%           
                              70         1713    113.12%           
                              80          265     17.50%           
                              90          307     20.27%           
                             100           56      3.70%           
                             110           82      5.41%           
                             120           88      5.81%           
                             130           47      3.10%           
                             140          149      9.84%           
                             150           84      5.55%           
                             160           93      6.14%           
                             170           21      1.39%           
                             180            2      0.13%           
                             190            0      0.00%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_1.max_value            183                      
cpu.IFQ:qfull_rob_occ_dist_1.end_dist

cpu.IFQ:qfull_rob_occ_dist_2.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_2.samples           151433                      
cpu.IFQ:qfull_rob_occ_dist_2.min_value              0                      
                               0        17540   1158.27%           
                              10        21216   1401.02%           
                              20        42933   2835.12%           
                              30        27343   1805.62%           
                              40        13599    898.02%           
                              50         6709    443.03%           
                              60         3927    259.32%           
                              70         1610    106.32%           
                              80         1999    132.01%           
                              90         1640    108.30%           
                             100         1844    121.77%           
                             110         1755    115.89%           
                             120         1387     91.59%           
                             130         2022    133.52%           
                             140         1958    129.30%           
                             150         1305     86.18%           
                             160          803     53.03%           
                             170          726     47.94%           
                             180          326     21.53%           
                             190          791     52.23%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_2.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_2.end_dist

cpu.IFQ:qfull_rob_occ_dist_3.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_3.samples           151433                      
cpu.IFQ:qfull_rob_occ_dist_3.min_value              0                      
                               0        60935   4023.89%           
                              10        22510   1486.47%           
                              20        37788   2495.36%           
                              30        14267    942.13%           
                              40         6869    453.60%           
                              50         3747    247.44%           
                              60         2417    159.61%           
                              70          877     57.91%           
                              80          730     48.21%           
                              90          161     10.63%           
                             100          255     16.84%           
                             110           65      4.29%           
                             120          142      9.38%           
                             130           53      3.50%           
                             140           67      4.42%           
                             150           56      3.70%           
                             160           79      5.22%           
                             170           26      1.72%           
                             180          282     18.62%           
                             190          107      7.07%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_3.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_3.end_dist

cpu.IQ:cap_events                                   0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_0                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_1                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_2                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_3                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_inst                                     0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_0                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_1                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_2                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_3                                   0                       # number of instructions held up by IQ cap
cpu.IQ:residence:(null).start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:(null).samples                     0                      
cpu.IQ:residence:(null).min_value                   0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:(null).max_value                   0                      
cpu.IQ:residence:(null).end_dist

cpu.IQ:residence:IntAlu.start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:IntAlu.samples                907745                      
cpu.IQ:residence:IntAlu.min_value                   1                      
                               0        94277   1038.58%   1038.58%
                               2       130835   1441.32%   2479.90%
                               4       113889   1254.64%   3734.54%
                               6       138767   1528.70%   5263.24%
                               8       117121   1290.24%   6553.48%
                              10       104372   1149.79%   7703.28%
                              12        75232    828.78%   8532.05%
                              14        51688    569.41%   9101.47%
                              16        32090    353.51%   9454.98%
                              18        18243    200.97%   9655.95%
                              20         7881     86.82%   9742.77%
                              22         3258     35.89%   9778.66%
                              24         1396     15.38%   9794.04%
                              26          606      6.68%   9800.71%
                              28          405      4.46%   9805.18%
                              30          319      3.51%   9808.69%
                              32          232      2.56%   9811.25%
                              34          201      2.21%   9813.46%
                              36          152      1.67%   9815.14%
                              38          102      1.12%   9816.26%
                              40           76      0.84%   9817.10%
                              42           72      0.79%   9817.89%
                              44           81      0.89%   9818.78%
                              46           81      0.89%   9819.67%
                              48           86      0.95%   9820.62%
                              50           78      0.86%   9821.48%
                              52           97      1.07%   9822.55%
                              54          142      1.56%   9824.11%
                              56          102      1.12%   9825.24%
                              58           89      0.98%   9826.22%
                              60          133      1.47%   9827.68%
                              62           92      1.01%   9828.70%
                              64          104      1.15%   9829.84%
                              66          126      1.39%   9831.23%
                              68          134      1.48%   9832.71%
                              70          115      1.27%   9833.97%
                              72           95      1.05%   9835.02%
                              74          101      1.11%   9836.13%
                              76           87      0.96%   9837.09%
                              78           97      1.07%   9838.16%
                              80           94      1.04%   9839.19%
                              82          112      1.23%   9840.43%
                              84          107      1.18%   9841.61%
                              86           90      0.99%   9842.60%
                              88          120      1.32%   9843.92%
                              90          104      1.15%   9845.07%
                              92          128      1.41%   9846.48%
                              94          134      1.48%   9847.95%
                              96          146      1.61%   9849.56%
                              98          137      1.51%   9851.07%
cpu.IQ:residence:IntAlu.overflows               13519                      
cpu.IQ:residence:IntAlu.max_value                1150                      
cpu.IQ:residence:IntAlu.end_dist

cpu.IQ:residence:IntMult.start_dist                            # cycles from dispatch to issue
cpu.IQ:residence:IntMult.samples                  271                      
cpu.IQ:residence:IntMult.min_value                  1                      
                               0            9    332.10%    332.10%
                               2           29   1070.11%   1402.21%
                               4           32   1180.81%   2583.03%
                               6           72   2656.83%   5239.85%
                               8           49   1808.12%   7047.97%
                              10           37   1365.31%   8413.28%
                              12           14    516.61%   8929.89%
                              14            9    332.10%   9261.99%
                              16            2     73.80%   9335.79%
                              18            0      0.00%   9335.79%
                              20            1     36.90%   9372.69%
                              22            2     73.80%   9446.49%
                              24            1     36.90%   9483.39%
                              26            0      0.00%   9483.39%
                              28            0      0.00%   9483.39%
                              30            0      0.00%   9483.39%
                              32            0      0.00%   9483.39%
                              34            0      0.00%   9483.39%
                              36            0      0.00%   9483.39%
                              38            0      0.00%   9483.39%
                              40            0      0.00%   9483.39%
                              42            0      0.00%   9483.39%
                              44            0      0.00%   9483.39%
                              46            0      0.00%   9483.39%
                              48            0      0.00%   9483.39%
                              50            0      0.00%   9483.39%
                              52            0      0.00%   9483.39%
                              54            0      0.00%   9483.39%
                              56            0      0.00%   9483.39%
                              58            0      0.00%   9483.39%
                              60            0      0.00%   9483.39%
                              62            0      0.00%   9483.39%
                              64            0      0.00%   9483.39%
                              66            0      0.00%   9483.39%
                              68            0      0.00%   9483.39%
                              70            0      0.00%   9483.39%
                              72            0      0.00%   9483.39%
                              74            0      0.00%   9483.39%
                              76            0      0.00%   9483.39%
                              78            0      0.00%   9483.39%
                              80            0      0.00%   9483.39%
                              82            0      0.00%   9483.39%
                              84            0      0.00%   9483.39%
                              86            1     36.90%   9520.30%
                              88            0      0.00%   9520.30%
                              90            1     36.90%   9557.20%
                              92            0      0.00%   9557.20%
                              94            0      0.00%   9557.20%
                              96            0      0.00%   9557.20%
                              98            1     36.90%   9594.10%
cpu.IQ:residence:IntMult.overflows                 11                      
cpu.IQ:residence:IntMult.max_value                138                      
cpu.IQ:residence:IntMult.end_dist

cpu.IQ:residence:IntDiv.start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:IntDiv.samples                     0                      
cpu.IQ:residence:IntDiv.min_value                   0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:IntDiv.max_value                   0                      
cpu.IQ:residence:IntDiv.end_dist

cpu.IQ:residence:FloatAdd.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatAdd.samples                  65                      
cpu.IQ:residence:FloatAdd.min_value                 1                      
                               0            6    923.08%    923.08%
                               2            8   1230.77%   2153.85%
                               4            1    153.85%   2307.69%
                               6            5    769.23%   3076.92%
                               8           11   1692.31%   4769.23%
                              10           14   2153.85%   6923.08%
                              12           10   1538.46%   8461.54%
                              14            4    615.38%   9076.92%
                              16            3    461.54%   9538.46%
                              18            0      0.00%   9538.46%
                              20            1    153.85%   9692.31%
                              22            0      0.00%   9692.31%
                              24            0      0.00%   9692.31%
                              26            0      0.00%   9692.31%
                              28            0      0.00%   9692.31%
                              30            0      0.00%   9692.31%
                              32            0      0.00%   9692.31%
                              34            0      0.00%   9692.31%
                              36            0      0.00%   9692.31%
                              38            0      0.00%   9692.31%
                              40            0      0.00%   9692.31%
                              42            0      0.00%   9692.31%
                              44            0      0.00%   9692.31%
                              46            0      0.00%   9692.31%
                              48            0      0.00%   9692.31%
                              50            0      0.00%   9692.31%
                              52            0      0.00%   9692.31%
                              54            0      0.00%   9692.31%
                              56            0      0.00%   9692.31%
                              58            0      0.00%   9692.31%
                              60            0      0.00%   9692.31%
                              62            0      0.00%   9692.31%
                              64            0      0.00%   9692.31%
                              66            0      0.00%   9692.31%
                              68            0      0.00%   9692.31%
                              70            0      0.00%   9692.31%
                              72            0      0.00%   9692.31%
                              74            0      0.00%   9692.31%
                              76            0      0.00%   9692.31%
                              78            0      0.00%   9692.31%
                              80            0      0.00%   9692.31%
                              82            0      0.00%   9692.31%
                              84            0      0.00%   9692.31%
                              86            0      0.00%   9692.31%
                              88            0      0.00%   9692.31%
                              90            0      0.00%   9692.31%
                              92            0      0.00%   9692.31%
                              94            0      0.00%   9692.31%
                              96            0      0.00%   9692.31%
                              98            0      0.00%   9692.31%
cpu.IQ:residence:FloatAdd.overflows                 2                      
cpu.IQ:residence:FloatAdd.max_value               149                      
cpu.IQ:residence:FloatAdd.end_dist

cpu.IQ:residence:FloatCmp.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatCmp.samples                   6                      
cpu.IQ:residence:FloatCmp.min_value                 7                      
                               0            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               6            1   1666.67%   1666.67%
                               8            2   3333.33%   5000.00%
                              10            2   3333.33%   8333.33%
                              12            0      0.00%   8333.33%
                              14            0      0.00%   8333.33%
                              16            0      0.00%   8333.33%
                              18            0      0.00%   8333.33%
                              20            0      0.00%   8333.33%
                              22            0      0.00%   8333.33%
                              24            0      0.00%   8333.33%
                              26            0      0.00%   8333.33%
                              28            0      0.00%   8333.33%
                              30            0      0.00%   8333.33%
                              32            0      0.00%   8333.33%
                              34            0      0.00%   8333.33%
                              36            0      0.00%   8333.33%
                              38            0      0.00%   8333.33%
                              40            0      0.00%   8333.33%
                              42            0      0.00%   8333.33%
                              44            0      0.00%   8333.33%
                              46            0      0.00%   8333.33%
                              48            0      0.00%   8333.33%
                              50            0      0.00%   8333.33%
                              52            0      0.00%   8333.33%
                              54            0      0.00%   8333.33%
                              56            0      0.00%   8333.33%
                              58            0      0.00%   8333.33%
                              60            0      0.00%   8333.33%
                              62            0      0.00%   8333.33%
                              64            0      0.00%   8333.33%
                              66            0      0.00%   8333.33%
                              68            0      0.00%   8333.33%
                              70            0      0.00%   8333.33%
                              72            0      0.00%   8333.33%
                              74            0      0.00%   8333.33%
                              76            0      0.00%   8333.33%
                              78            0      0.00%   8333.33%
                              80            0      0.00%   8333.33%
                              82            0      0.00%   8333.33%
                              84            0      0.00%   8333.33%
                              86            0      0.00%   8333.33%
                              88            0      0.00%   8333.33%
                              90            0      0.00%   8333.33%
                              92            0      0.00%   8333.33%
                              94            0      0.00%   8333.33%
                              96            0      0.00%   8333.33%
                              98            0      0.00%   8333.33%
cpu.IQ:residence:FloatCmp.overflows                 1                      
cpu.IQ:residence:FloatCmp.max_value               147                      
cpu.IQ:residence:FloatCmp.end_dist

cpu.IQ:residence:FloatCvt.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatCvt.samples                  49                      
cpu.IQ:residence:FloatCvt.min_value                 1                      
                               0            3    612.24%    612.24%
                               2            1    204.08%    816.33%
                               4           12   2448.98%   3265.31%
                               6            9   1836.73%   5102.04%
                               8           10   2040.82%   7142.86%
                              10            6   1224.49%   8367.35%
                              12            5   1020.41%   9387.76%
                              14            1    204.08%   9591.84%
                              16            0      0.00%   9591.84%
                              18            1    204.08%   9795.92%
                              20            0      0.00%   9795.92%
                              22            1    204.08%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.IQ:residence:FloatCvt.max_value                22                      
cpu.IQ:residence:FloatCvt.end_dist

cpu.IQ:residence:FloatMult.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:FloatMult.samples                  5                      
cpu.IQ:residence:FloatMult.min_value                6                      
                               0            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               6            2   4000.00%   4000.00%
                               8            2   4000.00%   8000.00%
                              10            0      0.00%   8000.00%
                              12            0      0.00%   8000.00%
                              14            0      0.00%   8000.00%
                              16            0      0.00%   8000.00%
                              18            0      0.00%   8000.00%
                              20            0      0.00%   8000.00%
                              22            0      0.00%   8000.00%
                              24            0      0.00%   8000.00%
                              26            0      0.00%   8000.00%
                              28            0      0.00%   8000.00%
                              30            0      0.00%   8000.00%
                              32            0      0.00%   8000.00%
                              34            0      0.00%   8000.00%
                              36            0      0.00%   8000.00%
                              38            0      0.00%   8000.00%
                              40            0      0.00%   8000.00%
                              42            0      0.00%   8000.00%
                              44            0      0.00%   8000.00%
                              46            0      0.00%   8000.00%
                              48            0      0.00%   8000.00%
                              50            0      0.00%   8000.00%
                              52            0      0.00%   8000.00%
                              54            0      0.00%   8000.00%
                              56            0      0.00%   8000.00%
                              58            0      0.00%   8000.00%
                              60            0      0.00%   8000.00%
                              62            0      0.00%   8000.00%
                              64            0      0.00%   8000.00%
                              66            0      0.00%   8000.00%
                              68            0      0.00%   8000.00%
                              70            0      0.00%   8000.00%
                              72            0      0.00%   8000.00%
                              74            0      0.00%   8000.00%
                              76            0      0.00%   8000.00%
                              78            0      0.00%   8000.00%
                              80            0      0.00%   8000.00%
                              82            0      0.00%   8000.00%
                              84            0      0.00%   8000.00%
                              86            0      0.00%   8000.00%
                              88            0      0.00%   8000.00%
                              90            0      0.00%   8000.00%
                              92            0      0.00%   8000.00%
                              94            0      0.00%   8000.00%
                              96            0      0.00%   8000.00%
                              98            0      0.00%   8000.00%
cpu.IQ:residence:FloatMult.overflows                1                      
cpu.IQ:residence:FloatMult.max_value              144                      
cpu.IQ:residence:FloatMult.end_dist

cpu.IQ:residence:FloatDiv.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatDiv.samples                   2                      
cpu.IQ:residence:FloatDiv.min_value                 5                      
                               0            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               4            1   5000.00%   5000.00%
                               6            0      0.00%   5000.00%
                               8            1   5000.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.IQ:residence:FloatDiv.max_value                 9                      
cpu.IQ:residence:FloatDiv.end_dist

cpu.IQ:residence:FloatSqrt.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:FloatSqrt.samples                  0                      
cpu.IQ:residence:FloatSqrt.min_value                0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:FloatSqrt.max_value                0                      
cpu.IQ:residence:FloatSqrt.end_dist

cpu.IQ:residence:MemRead.start_dist                            # cycles from dispatch to issue
cpu.IQ:residence:MemRead.samples               755959                      
cpu.IQ:residence:MemRead.min_value                  1                      
                               0        53958    713.77%    713.77%
                               2       155110   2051.83%   2765.60%
                               4       122832   1624.85%   4390.45%
                               6       144961   1917.58%   6308.03%
                               8       116333   1538.88%   7846.91%
                              10        81332   1075.88%   8922.79%
                              12        39290    519.74%   9442.52%
                              14        18480    244.46%   9686.98%
                              16         7975    105.50%   9792.48%
                              18         3211     42.48%   9834.95%
                              20         1215     16.07%   9851.02%
                              22          391      5.17%   9856.20%
                              24          154      2.04%   9858.23%
                              26           97      1.28%   9859.52%
                              28           91      1.20%   9860.72%
                              30          104      1.38%   9862.10%
                              32           61      0.81%   9862.90%
                              34           55      0.73%   9863.63%
                              36           47      0.62%   9864.25%
                              38           58      0.77%   9865.02%
                              40           51      0.67%   9865.69%
                              42           32      0.42%   9866.12%
                              44           55      0.73%   9866.84%
                              46           64      0.85%   9867.69%
                              48           67      0.89%   9868.58%
                              50           68      0.90%   9869.48%
                              52           60      0.79%   9870.27%
                              54           91      1.20%   9871.47%
                              56           95      1.26%   9872.73%
                              58           84      1.11%   9873.84%
                              60          136      1.80%   9875.64%
                              62          134      1.77%   9877.41%
                              64          138      1.83%   9879.24%
                              66          111      1.47%   9880.71%
                              68           48      0.63%   9881.34%
                              70           49      0.65%   9881.99%
                              72           48      0.63%   9882.63%
                              74           51      0.67%   9883.30%
                              76           51      0.67%   9883.98%
                              78           46      0.61%   9884.58%
                              80           55      0.73%   9885.31%
                              82           58      0.77%   9886.08%
                              84           41      0.54%   9886.62%
                              86           52      0.69%   9887.31%
                              88           89      1.18%   9888.49%
                              90           90      1.19%   9889.68%
                              92          101      1.34%   9891.01%
                              94          110      1.46%   9892.47%
                              96          114      1.51%   9893.98%
                              98          139      1.84%   9895.81%
cpu.IQ:residence:MemRead.overflows               7876                      
cpu.IQ:residence:MemRead.max_value               1021                      
cpu.IQ:residence:MemRead.end_dist

cpu.IQ:residence:MemWrite.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:MemWrite.samples              320987                      
cpu.IQ:residence:MemWrite.min_value                 1                      
                               0        24024    748.44%    748.44%
                               2        67791   2111.95%   2860.40%
                               4        51905   1617.04%   4477.44%
                               6        55293   1722.59%   6200.03%
                               8        46204   1439.44%   7639.47%
                              10        35939   1119.64%   8759.11%
                              12        18637    580.62%   9339.72%
                              14         8865    276.18%   9615.90%
                              16         4814    149.97%   9765.88%
                              18         2184     68.04%   9833.92%
                              20          625     19.47%   9853.39%
                              22          165      5.14%   9858.53%
                              24           88      2.74%   9861.27%
                              26           82      2.55%   9863.83%
                              28           47      1.46%   9865.29%
                              30           44      1.37%   9866.66%
                              32           44      1.37%   9868.03%
                              34           35      1.09%   9869.12%
                              36           40      1.25%   9870.37%
                              38           40      1.25%   9871.61%
                              40           35      1.09%   9872.71%
                              42           31      0.97%   9873.67%
                              44           25      0.78%   9874.45%
                              46           36      1.12%   9875.57%
                              48           42      1.31%   9876.88%
                              50           53      1.65%   9878.53%
                              52           36      1.12%   9879.65%
                              54           52      1.62%   9881.27%
                              56           68      2.12%   9883.39%
                              58           27      0.84%   9884.23%
                              60           52      1.62%   9885.85%
                              62           57      1.78%   9887.63%
                              64           27      0.84%   9888.47%
                              66           42      1.31%   9889.78%
                              68           30      0.93%   9890.71%
                              70           32      1.00%   9891.71%
                              72           29      0.90%   9892.61%
                              74           37      1.15%   9893.77%
                              76           37      1.15%   9894.92%
                              78           24      0.75%   9895.67%
                              80           30      0.93%   9896.60%
                              82           32      1.00%   9897.60%
                              84           69      2.15%   9899.75%
                              86           59      1.84%   9901.58%
                              88           67      2.09%   9903.67%
                              90           72      2.24%   9905.92%
                              92           62      1.93%   9907.85%
                              94           56      1.74%   9909.59%
                              96           94      2.93%   9912.52%
                              98          104      3.24%   9915.76%
cpu.IQ:residence:MemWrite.overflows              2704                      
cpu.IQ:residence:MemWrite.max_value               381                      
cpu.IQ:residence:MemWrite.end_dist

cpu.IQ:residence:IprAccess.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:IprAccess.samples                  0                      
cpu.IQ:residence:IprAccess.min_value                0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:IprAccess.max_value                0                      
cpu.IQ:residence:IprAccess.end_dist

cpu.IQ:residence:InstPrefetch.start_dist                       # cycles from dispatch to issue
cpu.IQ:residence:InstPrefetch.samples               0                      
cpu.IQ:residence:InstPrefetch.min_value             0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:InstPrefetch.max_value             0                      
cpu.IQ:residence:InstPrefetch.end_dist

cpu.ISSUE:(null)_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:(null)_delay.samples                      0                      
cpu.ISSUE:(null)_delay.min_value                    0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:(null)_delay.max_value                    0                      
cpu.ISSUE:(null)_delay.end_dist

cpu.ISSUE:IntAlu_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:IntAlu_delay.samples                 907745                      
cpu.ISSUE:IntAlu_delay.min_value                    0                      
                               0       665323   7329.40%   7329.40%
                               2        99741   1098.78%   8428.18%
                               4        61153    673.68%   9101.86%
                               6        43046    474.21%   9576.07%
                               8        26770    294.91%   9870.98%
                              10        11310    124.59%   9995.57%
                              12          402      4.43%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:IntAlu_delay.max_value                   13                      
cpu.ISSUE:IntAlu_delay.end_dist

cpu.ISSUE:IntMult_delay.start_dist                             # cycles from operands ready to issue
cpu.ISSUE:IntMult_delay.samples                   271                      
cpu.ISSUE:IntMult_delay.min_value                   0                      
                               0          242   8929.89%   8929.89%
                               2           17    627.31%   9557.20%
                               4           12    442.80%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:IntMult_delay.max_value                   5                      
cpu.ISSUE:IntMult_delay.end_dist

cpu.ISSUE:IntDiv_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:IntDiv_delay.samples                      0                      
cpu.ISSUE:IntDiv_delay.min_value                    0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:IntDiv_delay.max_value                    0                      
cpu.ISSUE:IntDiv_delay.end_dist

cpu.ISSUE:FloatAdd_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatAdd_delay.samples                   65                      
cpu.ISSUE:FloatAdd_delay.min_value                  0                      
                               0           62   9538.46%   9538.46%
                               2            3    461.54%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatAdd_delay.max_value                  3                      
cpu.ISSUE:FloatAdd_delay.end_dist

cpu.ISSUE:FloatCmp_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatCmp_delay.samples                    6                      
cpu.ISSUE:FloatCmp_delay.min_value                  0                      
                               0            6  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatCmp_delay.max_value                  0                      
cpu.ISSUE:FloatCmp_delay.end_dist

cpu.ISSUE:FloatCvt_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatCvt_delay.samples                   49                      
cpu.ISSUE:FloatCvt_delay.min_value                  0                      
                               0           47   9591.84%   9591.84%
                               2            1    204.08%   9795.92%
                               4            0      0.00%   9795.92%
                               6            1    204.08%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatCvt_delay.max_value                  7                      
cpu.ISSUE:FloatCvt_delay.end_dist

cpu.ISSUE:FloatMult_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:FloatMult_delay.samples                   5                      
cpu.ISSUE:FloatMult_delay.min_value                 0                      
                               0            5  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatMult_delay.max_value                 0                      
cpu.ISSUE:FloatMult_delay.end_dist

cpu.ISSUE:FloatDiv_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatDiv_delay.samples                    2                      
cpu.ISSUE:FloatDiv_delay.min_value                  0                      
                               0            2  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatDiv_delay.max_value                  0                      
cpu.ISSUE:FloatDiv_delay.end_dist

cpu.ISSUE:FloatSqrt_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:FloatSqrt_delay.samples                   0                      
cpu.ISSUE:FloatSqrt_delay.min_value                 0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:FloatSqrt_delay.max_value                 0                      
cpu.ISSUE:FloatSqrt_delay.end_dist

cpu.ISSUE:MemRead_delay.start_dist                             # cycles from operands ready to issue
cpu.ISSUE:MemRead_delay.samples                755959                      
cpu.ISSUE:MemRead_delay.min_value                   0                      
                               0       598772   7920.69%   7920.69%
                               2        67759    896.33%   8817.03%
                               4        37170    491.69%   9308.72%
                               6        25863    342.12%   9650.84%
                               8        16609    219.71%   9870.55%
                              10         6884     91.06%   9961.61%
                              12          235      3.11%   9964.72%
                              14           36      0.48%   9965.20%
                              16           35      0.46%   9965.66%
                              18           28      0.37%   9966.03%
                              20           13      0.17%   9966.20%
                              22           40      0.53%   9966.73%
                              24           26      0.34%   9967.07%
                              26           21      0.28%   9967.35%
                              28            4      0.05%   9967.41%
                              30           11      0.15%   9967.55%
                              32           15      0.20%   9967.75%
                              34            6      0.08%   9967.83%
                              36           10      0.13%   9967.96%
                              38           18      0.24%   9968.20%
                              40           30      0.40%   9968.60%
                              42           18      0.24%   9968.83%
                              44           22      0.29%   9969.13%
                              46           35      0.46%   9969.59%
                              48           42      0.56%   9970.14%
                              50           61      0.81%   9970.95%
                              52           96      1.27%   9972.22%
                              54           69      0.91%   9973.13%
                              56           62      0.82%   9973.95%
                              58           38      0.50%   9974.46%
                              60           14      0.19%   9974.64%
                              62            7      0.09%   9974.73%
                              64           12      0.16%   9974.89%
                              66            4      0.05%   9974.95%
                              68           19      0.25%   9975.20%
                              70           17      0.22%   9975.42%
                              72           18      0.24%   9975.66%
                              74           22      0.29%   9975.95%
                              76           16      0.21%   9976.16%
                              78           19      0.25%   9976.41%
                              80           21      0.28%   9976.69%
                              82           19      0.25%   9976.94%
                              84           33      0.44%   9977.38%
                              86           47      0.62%   9978.00%
                              88           84      1.11%   9979.11%
                              90           68      0.90%   9980.01%
                              92           47      0.62%   9980.63%
                              94           66      0.87%   9981.51%
                              96           99      1.31%   9982.82%
                              98          119      1.57%   9984.39%
cpu.ISSUE:MemRead_delay.overflows                1180                      
cpu.ISSUE:MemRead_delay.max_value                 134                      
cpu.ISSUE:MemRead_delay.end_dist

cpu.ISSUE:MemWrite_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:MemWrite_delay.samples               320987                      
cpu.ISSUE:MemWrite_delay.min_value                  0                      
                               0       247512   7710.97%   7710.97%
                               2        34693   1080.82%   8791.79%
                               4        18051    562.36%   9354.15%
                               6        10070    313.72%   9667.87%
                               8         6353    197.92%   9865.79%
                              10         2442     76.08%   9941.87%
                              12           77      2.40%   9944.27%
                              14            0      0.00%   9944.27%
                              16           10      0.31%   9944.58%
                              18            4      0.12%   9944.70%
                              20            4      0.12%   9944.83%
                              22            5      0.16%   9944.98%
                              24            5      0.16%   9945.14%
                              26            5      0.16%   9945.29%
                              28            6      0.19%   9945.48%
                              30            3      0.09%   9945.57%
                              32            3      0.09%   9945.67%
                              34            9      0.28%   9945.95%
                              36            6      0.19%   9946.13%
                              38            3      0.09%   9946.23%
                              40            6      0.19%   9946.42%
                              42           15      0.47%   9946.88%
                              44           15      0.47%   9947.35%
                              46           19      0.59%   9947.94%
                              48           38      1.18%   9949.13%
                              50           53      1.65%   9950.78%
                              52           26      0.81%   9951.59%
                              54           22      0.69%   9952.27%
                              56           15      0.47%   9952.74%
                              58            8      0.25%   9952.99%
                              60            5      0.16%   9953.14%
                              62            2      0.06%   9953.21%
                              64           14      0.44%   9953.64%
                              66            6      0.19%   9953.83%
                              68           11      0.34%   9954.17%
                              70            5      0.16%   9954.33%
                              72           15      0.47%   9954.80%
                              74            7      0.22%   9955.01%
                              76           15      0.47%   9955.48%
                              78           20      0.62%   9956.10%
                              80           35      1.09%   9957.19%
                              82           22      0.69%   9957.88%
                              84           33      1.03%   9958.91%
                              86           35      1.09%   9960.00%
                              88           47      1.46%   9961.46%
                              90           76      2.37%   9963.83%
                              92           71      2.21%   9966.04%
                              94          113      3.52%   9969.56%
                              96          100      3.12%   9972.68%
                              98          106      3.30%   9975.98%
cpu.ISSUE:MemWrite_delay.overflows                771                      
cpu.ISSUE:MemWrite_delay.max_value                126                      
cpu.ISSUE:MemWrite_delay.end_dist

cpu.ISSUE:IprAccess_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:IprAccess_delay.samples                   0                      
cpu.ISSUE:IprAccess_delay.min_value                 0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:IprAccess_delay.max_value                 0                      
cpu.ISSUE:IprAccess_delay.end_dist

cpu.ISSUE:InstPrefetch_delay.start_dist                        # cycles from operands ready to issue
cpu.ISSUE:InstPrefetch_delay.samples                0                      
cpu.ISSUE:InstPrefetch_delay.min_value              0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:InstPrefetch_delay.max_value              0                      
cpu.ISSUE:InstPrefetch_delay.end_dist

cpu.ISSUE:FU_type_0                            750671                       # Type of FU issued
cpu.ISSUE:FU_type_0.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu       539158     71.82%            # Type of FU issued
                         IntMult            0      0.00%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd            0      0.00%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       163694     21.81%            # Type of FU issued
                        MemWrite        47819      6.37%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_0.end_dist
cpu.ISSUE:FU_type_1                            175300                       # Type of FU issued
cpu.ISSUE:FU_type_1.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu       130718     74.57%            # Type of FU issued
                         IntMult           86      0.05%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd            6      0.00%            # Type of FU issued
                        FloatCmp            0      0.00%            # Type of FU issued
                        FloatCvt            6      0.00%            # Type of FU issued
                       FloatMult            0      0.00%            # Type of FU issued
                        FloatDiv            2      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead        34164     19.49%            # Type of FU issued
                        MemWrite        10318      5.89%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_1.end_dist
cpu.ISSUE:FU_type_2                            691085                       # Type of FU issued
cpu.ISSUE:FU_type_2.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu       504951     73.07%            # Type of FU issued
                         IntMult            2      0.00%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd           20      0.00%            # Type of FU issued
                        FloatCmp            4      0.00%            # Type of FU issued
                        FloatCvt            0      0.00%            # Type of FU issued
                       FloatMult            3      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       130273     18.85%            # Type of FU issued
                        MemWrite        55832      8.08%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_2.end_dist
cpu.ISSUE:FU_type_3                            356294                       # Type of FU issued
cpu.ISSUE:FU_type_3.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu       276918     77.72%            # Type of FU issued
                         IntMult          183      0.05%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd           39      0.01%            # Type of FU issued
                        FloatCmp            2      0.00%            # Type of FU issued
                        FloatCvt           43      0.01%            # Type of FU issued
                       FloatMult            2      0.00%            # Type of FU issued
                        FloatDiv            0      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead        47236     13.26%            # Type of FU issued
                        MemWrite        31871      8.95%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_3.end_dist
cpu.ISSUE:FU_type                             1973350                       # Type of FU issued
cpu.ISSUE:FU_type.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu      1451745     73.57%            # Type of FU issued
                         IntMult          271      0.01%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd           65      0.00%            # Type of FU issued
                        FloatCmp            6      0.00%            # Type of FU issued
                        FloatCvt           49      0.00%            # Type of FU issued
                       FloatMult            5      0.00%            # Type of FU issued
                        FloatDiv            2      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       375367     19.02%            # Type of FU issued
                        MemWrite       145840      7.39%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type.end_dist
cpu.ISSUE:IQ_0:fu_full.start_dist
                          (null)            0      0.00%           
                          IntAlu       710299     94.07%           
                         IntMult            7      0.00%           
                          IntDiv            0      0.00%           
                        FloatAdd            0      0.00%           
                        FloatCmp            0      0.00%           
                        FloatCvt            0      0.00%           
                       FloatMult            0      0.00%           
                        FloatDiv            0      0.00%           
                       FloatSqrt            0      0.00%           
                         MemRead        41196      5.46%           
                        MemWrite         3569      0.47%           
                       IprAccess            0      0.00%           
                    InstPrefetch            0      0.00%           
cpu.ISSUE:IQ_0:fu_full.end_dist
cpu.ISSUE:MSIPC                              0.452126                       # Misspec issue rate
cpu.ISSUE:MSIPC_0                            0.161755                       # Misspec issue rate
cpu.ISSUE:MSIPC_1                            0.091212                       # Misspec issue rate
cpu.ISSUE:MSIPC_2                            0.062699                       # Misspec issue rate
cpu.ISSUE:MSIPC_3                            0.136461                       # Misspec issue rate
cpu.ISSUE:addr_loads                              601                       # number of invalid-address loads
cpu.ISSUE:addr_loads_0                             44                       # number of invalid-address loads
cpu.ISSUE:addr_loads_1                            265                       # number of invalid-address loads
cpu.ISSUE:addr_loads_2                             15                       # number of invalid-address loads
cpu.ISSUE:addr_loads_3                            277                       # number of invalid-address loads
cpu.ISSUE:addr_swpfs                                0                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_0                              0                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_1                              0                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_2                              0                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_3                              0                       # number of invalid-address SW prefetches
cpu.ISSUE:branches                             219488                       # Number of branches issued
cpu.ISSUE:branches_0                            92259                       # Number of branches issued
cpu.ISSUE:branches_1                            19589                       # Number of branches issued
cpu.ISSUE:branches_2                            64234                       # Number of branches issued
cpu.ISSUE:branches_3                            43406                       # Number of branches issued
cpu.ISSUE:count                               1449814                       # number of insts issued
cpu.ISSUE:count_0                              539158                       # number of insts issued
cpu.ISSUE:count_1                              130547                       # number of insts issued
cpu.ISSUE:count_2                              504964                       # number of insts issued
cpu.ISSUE:count_3                              275145                       # number of insts issued
cpu.ISSUE:fu_busy_cnt                          755071                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_0                        268367                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_1                         98747                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_2                        217277                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_3                        170680                       # FU busy when requested
cpu.ISSUE:fu_busy_rate                       0.520805                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_0                     0.497752                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_1                     0.756410                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_2                     0.430282                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_3                     0.620327                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_full.start_dist
                          (null)            0      0.00%            # attempts to use FU when none available
                          IntAlu       710299     94.07%            # attempts to use FU when none available
                         IntMult            7      0.00%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead        41196      5.46%            # attempts to use FU when none available
                        MemWrite         3569      0.47%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
cpu.ISSUE:fu_full.end_dist
cpu.ISSUE:issued_per_cycle                     318791                       # Number of insts issued each cycle
cpu.ISSUE:issued_per_cycle.start_dist
                               0        17074      5.36%            # Number of insts issued each cycle
                               1         9815      3.08%            # Number of insts issued each cycle
                               2        10494      3.29%            # Number of insts issued each cycle
                               3        11357      3.56%            # Number of insts issued each cycle
                               4        12435      3.90%            # Number of insts issued each cycle
                               5        13188      4.14%            # Number of insts issued each cycle
                               6        45428     14.25%            # Number of insts issued each cycle
                               7        60033     18.83%            # Number of insts issued each cycle
                               8       138967     43.59%            # Number of insts issued each cycle
cpu.ISSUE:issued_per_cycle.end_dist
cpu.ISSUE:loads                                380592                       # number of load insts issued
cpu.ISSUE:loads_0                              165551                       # number of load insts issued
cpu.ISSUE:loads_1                               35218                       # number of load insts issued
cpu.ISSUE:loads_2                              131203                       # number of load insts issued
cpu.ISSUE:loads_3                               48620                       # number of load insts issued
cpu.ISSUE:lsq_inv_rate                              0                       # Early LSQ issues per cycle
cpu.ISSUE:lsq_invert                                0                       # Number of times LSQ instruction issued early
cpu.ISSUE:misspec_cnt                          151418                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_0                         54172                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_1                         30547                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_2                         20998                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_3                         45701                       # Number of misspeculated insts issued
cpu.ISSUE:nop                                  131279                       # number of nop insts issued
cpu.ISSUE:nop_0                                 23154                       # number of nop insts issued
cpu.ISSUE:nop_1                                 25486                       # number of nop insts issued
cpu.ISSUE:nop_2                                 35732                       # number of nop insts issued
cpu.ISSUE:nop_3                                 46907                       # number of nop insts issued
cpu.ISSUE:op_count                            1985089                       # number of insts issued
cpu.ISSUE:op_count_0                           755169                       # number of insts issued
cpu.ISSUE:op_count_1                           177770                       # number of insts issued
cpu.ISSUE:op_count_2                           692747                       # number of insts issued
cpu.ISSUE:op_count_3                           359403                       # number of insts issued
cpu.ISSUE:op_rate                            5.927373                       # Operation issue rate
cpu.ISSUE:op_rate_0                          2.254895                       # Operation issue rate
cpu.ISSUE:op_rate_1                          0.530812                       # Operation issue rate
cpu.ISSUE:op_rate_2                          2.068507                       # Operation issue rate
cpu.ISSUE:op_rate_3                          1.073159                       # Operation issue rate
cpu.ISSUE:rate                               4.329069                       # Inst issue rate
cpu.ISSUE:rate_0                             1.609898                       # Inst issue rate
cpu.ISSUE:rate_1                             0.389807                       # Inst issue rate
cpu.ISSUE:rate_2                             1.507796                       # Inst issue rate
cpu.ISSUE:rate_3                             0.821569                       # Inst issue rate
cpu.ISSUE:refs                                 544000                       # number of memory reference insts issued
cpu.ISSUE:refs_0                               220448                       # number of memory reference insts issued
cpu.ISSUE:refs_1                                48985                       # number of memory reference insts issued
cpu.ISSUE:refs_2                               189546                       # number of memory reference insts issued
cpu.ISSUE:refs_3                                85021                       # number of memory reference insts issued
cpu.ISSUE:stores                               163408                       # Number of stores issued
cpu.ISSUE:stores_0                              54897                       # Number of stores issued
cpu.ISSUE:stores_1                              13767                       # Number of stores issued
cpu.ISSUE:stores_2                              58343                       # Number of stores issued
cpu.ISSUE:stores_3                              36401                       # Number of stores issued
cpu.ISSUE:swp                                    2329                       # number of swp insts issued
cpu.ISSUE:swp_0                                     0                       # number of swp insts issued
cpu.ISSUE:swp_1                                   271                       # number of swp insts issued
cpu.ISSUE:swp_2                                    16                       # number of swp insts issued
cpu.ISSUE:swp_3                                  2042                       # number of swp insts issued
cpu.ISSUE:unissued_cause.start_dist
                          (null)            0      0.00%            # Reason ready instruction not issued
                          IntAlu       710299     92.27%            # Reason ready instruction not issued
                         IntMult            7      0.00%            # Reason ready instruction not issued
                          IntDiv            0      0.00%            # Reason ready instruction not issued
                        FloatAdd            0      0.00%            # Reason ready instruction not issued
                        FloatCmp            0      0.00%            # Reason ready instruction not issued
                        FloatCvt            0      0.00%            # Reason ready instruction not issued
                       FloatMult            0      0.00%            # Reason ready instruction not issued
                        FloatDiv            0      0.00%            # Reason ready instruction not issued
                       FloatSqrt            0      0.00%            # Reason ready instruction not issued
                         MemRead        41196      5.35%            # Reason ready instruction not issued
                        MemWrite            0      0.00%            # Reason ready instruction not issued
                       IprAccess            0      0.00%            # Reason ready instruction not issued
                    InstPrefetch            0      0.00%            # Reason ready instruction not issued
                  DCache_Blocked        18286      2.38%            # Reason ready instruction not issued
                       Too_Young            0      0.00%            # Reason ready instruction not issued
cpu.ISSUE:unissued_cause.end_dist
cpu.LSQ:RQ:rdy_inst                            964133                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_0                          343066                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_1                           97894                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_2                          298843                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_3                          224330                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_dist_0_mean              1.024377                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_0_stdev             1.808422                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_0_TOT       334902                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_1_mean              0.292306                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_1_stdev             1.144783                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_1_TOT       334902                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_2_mean              0.892330                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_2_stdev             1.583024                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_2_TOT       334902                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_3_mean              0.669838                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_3_stdev             2.151498                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_3_TOT       334902                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_rate                          2.878851                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_0                        1.024377                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_1                        0.292306                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_2                        0.892330                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_3                        0.669838                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_x_count                         533495                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_0                       216206                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_1                        47099                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_2                       187837                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_3                        82353                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_max                               21                       # largest number of insts that become ready
cpu.LSQ:RQ:rdy_x_rate                        1.592988                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_0                      0.645580                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_1                      0.140635                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_2                      0.560872                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_3                      0.245902                       # number of insts that become ready per cycle
cpu.LSQ:avg_residency                        3.963966                       # Average IQ residency
cpu.LSQ:avg_residency_0                      3.608222                       # Average IQ residency
cpu.LSQ:avg_residency_1                      9.257754                       # Average IQ residency
cpu.LSQ:avg_residency_2                      3.363707                       # Average IQ residency
cpu.LSQ:avg_residency_3                      3.250969                       # Average IQ residency
cpu.LSQ:blocked_loads                          118316                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_0                         16647                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_1                         21638                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_2                         57702                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_3                         22329                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:cum_num_insts                         5747013                       # Total occupancy
cpu.LSQ:cum_num_insts_0                       1945402                       # Total occupancy
cpu.LSQ:cum_num_insts_1                       1208572                       # Total occupancy
cpu.LSQ:cum_num_insts_2                       1698551                       # Total occupancy
cpu.LSQ:cum_num_insts_3                        894488                       # Total occupancy
cpu.LSQ:current_count                              25                       # Occupancy this cycle
cpu.LSQ:empty_count                              6010                       # Number of empty cycles
cpu.LSQ:empty_rate                           1.794555                       # Fraction of cycles empty
cpu.LSQ:forw_loads                                 28                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_0                               14                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_1                                5                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_2                                0                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_3                                9                       # number of loads forwarded via LSQ
cpu.LSQ:full_count                                  0                       # Number of full cycles
cpu.LSQ:full_rate                                   0                       # Fraction of cycles full
cpu.LSQ:occ_dist_0.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_0.samples                     334902                      
cpu.LSQ:occ_dist_0.min_value                        0                      
                               0        89245              2664.81%
                               2        30254              3568.18%
                               4        46426              4954.43%
                               6        49697              6438.36%
                               8        46097              7814.79%
                              10        34325              8839.72%
                              12        18297              9386.06%
                              14         9916              9682.15%
                              16         6298              9870.20%
                              18         2079              9932.28%
                              20         1042              9963.39%
                              22          457              9977.04%
                              24          232              9983.97%
                              26          140              9988.15%
                              28          170              9993.22%
                              30           39              9994.39%
                              32          188             10000.00%
cpu.LSQ:occ_dist_0.max_value                       32                      
cpu.LSQ:occ_dist_0.end_dist

cpu.LSQ:occ_dist_1.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_1.samples                     334902                      
cpu.LSQ:occ_dist_1.min_value                        0                      
                               0       157308              4697.14%
                               2        26818              5497.91%
                               4        54137              7114.41%
                               6        42972              8397.53%
                               8        20266              9002.66%
                              10        15922              9478.09%
                              12         6260              9665.01%
                              14         5452              9827.80%
                              16         3151              9921.89%
                              18         1173              9956.91%
                              20          982              9986.23%
                              22          243              9993.49%
                              24          133              9997.46%
                              26           19              9998.03%
                              28           66             10000.00%
                              30            0             10000.00%
                              32            0             10000.00%
cpu.LSQ:occ_dist_1.max_value                       29                      
cpu.LSQ:occ_dist_1.end_dist

cpu.LSQ:occ_dist_2.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_2.samples                     334902                      
cpu.LSQ:occ_dist_2.min_value                        0                      
                               0        74421              2222.17%
                               2        47342              3635.78%
                               4        69371              5707.16%
                               6        60891              7525.34%
                               8        41594              8767.31%
                              10        20595              9382.27%
                              12        12506              9755.69%
                              14         5126              9908.75%
                              16         1731              9960.44%
                              18          529              9976.23%
                              20          276              9984.47%
                              22          172              9989.61%
                              24          220              9996.18%
                              26          105              9999.31%
                              28           15              9999.76%
                              30            2              9999.82%
                              32            6             10000.00%
cpu.LSQ:occ_dist_2.max_value                       32                      
cpu.LSQ:occ_dist_2.end_dist

cpu.LSQ:occ_dist_3.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_3.samples                     334902                      
cpu.LSQ:occ_dist_3.min_value                        0                      
                               0       196265              5860.37%
                               2        43427              7157.08%
                               4        31261              8090.52%
                               6        20761              8710.43%
                               8        15223              9164.98%
                              10        13972              9582.18%
                              12         5907              9758.56%
                              14         4198              9883.91%
                              16         1665              9933.62%
                              18          901              9960.53%
                              20          425              9973.22%
                              22          229              9980.05%
                              24          257              9987.73%
                              26          140              9991.91%
                              28          127              9995.70%
                              30           66              9997.67%
                              32           78             10000.00%
cpu.LSQ:occ_dist_3.max_value                       32                      
cpu.LSQ:occ_dist_3.end_dist

cpu.LSQ:occ_rate                            17.160283                       # Average occupancy
cpu.LSQ:occ_rate_0                           5.808869                       # Average occupancy
cpu.LSQ:occ_rate_1                           3.608733                       # Average occupancy
cpu.LSQ:occ_rate_2                           5.071785                       # Average occupancy
cpu.LSQ:occ_rate_3                           2.670895                       # Average occupancy
cpu.LSQ:peak_occupancy                            125                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_0                           32                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_1                           29                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_2                           32                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_3                           32                       # Peak IQ occupancy
cpu.REG:fp:full                                     0                       # number of cycles where there were no FP registers
cpu.REG:fp:occ                                   8336                       # Cumulative count of FP register usage
cpu.REG:fp:occ_0                                    0                       # Cumulative count of FP register usage
cpu.REG:fp:occ_1                                 3220                       # Cumulative count of FP register usage
cpu.REG:fp:occ_2                                 1399                       # Cumulative count of FP register usage
cpu.REG:fp:occ_3                                 3717                       # Cumulative count of FP register usage
cpu.REG:fp:occ_rate                                 0                       # Average FP register usage
cpu.REG:fp:occ_rate_0                               0                       # Average FP register usage
cpu.REG:fp:occ_rate_1                               0                       # Average FP register usage
cpu.REG:fp:occ_rate_2                               0                       # Average FP register usage
cpu.REG:fp:occ_rate_3                               0                       # Average FP register usage
cpu.REG:int:full                                    0                       # number of cycles where there were no INT registers
cpu.REG:int:occ                              24445315                       # Cumulative count of INT register usage
cpu.REG:int:occ_0                             6670242                       # Cumulative count of INT register usage
cpu.REG:int:occ_1                             4881131                       # Cumulative count of INT register usage
cpu.REG:int:occ_2                             8697203                       # Cumulative count of INT register usage
cpu.REG:int:occ_3                             4196739                       # Cumulative count of INT register usage
cpu.REG:int:occ_rate                               73                       # Average INT register usage
cpu.REG:int:occ_rate_0                             20                       # Average INT register usage
cpu.REG:int:occ_rate_1                             15                       # Average INT register usage
cpu.REG:int:occ_rate_2                             26                       # Average INT register usage
cpu.REG:int:occ_rate_3                             13                       # Average INT register usage
cpu.ROB:cap_events                                  0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_0                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_1                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_2                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_3                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_inst                                    0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_0                                  0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_1                                  0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_2                                  0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_3                                  0                       # number of instructions held up by ROB cap
cpu.ROB:current_count                              89                       # Current ROB occupancy
cpu.ROB:full_count                              15731                       # number of cycles where ROB was full
cpu.ROB:full_rate                            0.046972                       # ROB full per cycle
cpu.ROB:occ_dist_0.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_0.samples                     334902                      
cpu.ROB:occ_dist_0.min_value                        0                      
                               0        50084              1495.48%
                               2         1370              1536.39%
                               4         3390              1637.61%
                               6         5196              1792.76%
                               8         9483              2075.92%
                              10         6495              2269.86%
                              12         6974              2478.10%
                              14         9510              2762.06%
                              16        13579              3167.52%
                              18        11783              3519.36%
                              20        15239              3974.39%
                              22        17396              4493.82%
                              24        20415              5103.40%
                              26        16113              5584.53%
                              28        16949              6090.62%
                              30        15311              6547.80%
                              32        15272              7003.81%
                              34        11416              7344.69%
                              36        10928              7670.99%
                              38        10197              7975.47%
                              40         8948              8242.65%
                              42         7471              8465.73%
                              44         6748              8667.22%
                              46         6415              8858.77%
                              48         5456              9021.68%
                              50         5305              9180.09%
                              52         4082              9301.97%
                              54         3803              9415.53%
                              56         3216              9511.56%
                              58         2281              9579.67%
                              60         2120              9642.97%
                              62         1654              9692.36%
                              64         1157              9726.91%
                              66          755              9749.45%
                              68          888              9775.96%
                              70          420              9788.51%
                              72          448              9801.88%
                              74          577              9819.11%
                              76          292              9827.83%
                              78          173              9833.00%
                              80          229              9839.83%
                              82          272              9847.96%
                              84          188              9853.57%
                              86           95              9856.41%
                              88          207              9862.59%
                              90          178              9867.90%
                              92          218              9874.41%
                              94          188              9880.02%
                              96          119              9883.58%
                              98           60              9885.37%
                             100          109              9888.62%
                             102           40              9889.82%
                             104           49              9891.28%
                             106          132              9895.22%
                             108           32              9896.18%
                             110          253              9903.73%
                             112           35              9904.78%
                             114           27              9905.58%
                             116           37              9906.69%
                             118           28              9907.53%
                             120           27              9908.33%
                             122           44              9909.65%
                             124           23              9910.33%
                             126           64              9912.24%
                             128           22              9912.90%
                             130           65              9914.84%
                             132           51              9916.36%
                             134           74              9918.57%
                             136           20              9919.17%
                             138           20              9919.77%
                             140           19              9920.33%
                             142           77              9922.63%
                             144          120              9926.22%
                             146           16              9926.69%
                             148           11              9927.02%
                             150           46              9928.40%
                             152           98              9931.32%
                             154           10              9931.62%
                             156           28              9932.46%
                             158           21              9933.08%
                             160           19              9933.65%
                             162           40              9934.85%
                             164           44              9936.16%
                             166           45              9937.50%
                             168           92              9940.25%
                             170           29              9941.12%
                             172           93              9943.89%
                             174           37              9945.00%
                             176           17              9945.51%
                             178           42              9946.76%
                             180          249              9954.20%
                             182          171              9959.30%
                             184          244              9966.59%
                             186          324              9976.26%
                             188           66              9978.23%
                             190          193              9984.00%
                             192          176              9989.25%
                             194           19              9989.82%
                             196          341             10000.00%
cpu.ROB:occ_dist_0.max_value                      196                      
cpu.ROB:occ_dist_0.end_dist

cpu.ROB:occ_dist_1.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_1.samples                     334902                      
cpu.ROB:occ_dist_1.min_value                        0                      
                               0       114395              3415.78%
                               2         7950              3653.16%
                               4         7035              3863.22%
                               6         7741              4094.36%
                               8         7763              4326.16%
                              10         5507              4490.60%
                              12         6088              4672.38%
                              14         8251              4918.75%
                              16         8634              5176.56%
                              18         8050              5416.93%
                              20        12227              5782.02%
                              22        13036              6171.27%
                              24        16438              6662.10%
                              26        12705              7041.46%
                              28        15376              7500.58%
                              30        12091              7861.61%
                              32         7941              8098.73%
                              34         9797              8391.26%
                              36         3855              8506.37%
                              38         4764              8648.62%
                              40         4702              8789.02%
                              42         3393              8890.33%
                              44         4570              9026.79%
                              46         2311              9095.80%
                              48         2319              9165.04%
                              50         2670              9244.76%
                              52         1448              9288.00%
                              54         3246              9384.92%
                              56         1410              9427.03%
                              58         1720              9478.38%
                              60         1316              9517.68%
                              62         1192              9553.27%
                              64         1807              9607.23%
                              66          774              9630.34%
                              68          879              9656.59%
                              70          520              9672.11%
                              72          390              9683.76%
                              74          875              9709.89%
                              76          364              9720.75%
                              78          515              9736.13%
                              80          523              9751.75%
                              82          395              9763.54%
                              84          307              9772.71%
                              86          469              9786.71%
                              88          308              9795.91%
                              90          428              9808.69%
                              92          255              9816.30%
                              94          281              9824.69%
                              96          314              9834.07%
                              98          336              9844.10%
                             100          305              9853.21%
                             102          300              9862.17%
                             104          387              9873.72%
                             106          186              9879.28%
                             108          127              9883.07%
                             110          220              9889.64%
                             112           91              9892.36%
                             114          160              9897.13%
                             116          199              9903.08%
                             118           77              9905.38%
                             120          133              9909.35%
                             122          189              9914.99%
                             124          132              9918.93%
                             126          215              9925.35%
                             128          306              9934.49%
                             130          222              9941.12%
                             132          272              9949.24%
                             134          164              9954.14%
                             136          272              9962.26%
                             138           72              9964.41%
                             140          103              9967.48%
                             142          129              9971.33%
                             144          221              9977.93%
                             146           50              9979.43%
                             148          133              9983.40%
                             150           44              9984.71%
                             152           27              9985.52%
                             154           83              9988.00%
                             156           19              9988.56%
                             158           13              9988.95%
                             160           47              9990.36%
                             162           14              9990.77%
                             164            7              9990.98%
                             166           24              9991.70%
                             168          108              9994.92%
                             170           34              9995.94%
                             172            3              9996.03%
                             174           23              9996.72%
                             176           12              9997.07%
                             178            2              9997.13%
                             180            2              9997.19%
                             182            7              9997.40%
                             184            3              9997.49%
                             186            3              9997.58%
                             188            2              9997.64%
                             190           55              9999.28%
                             192            0              9999.28%
                             194            2              9999.34%
                             196           22             10000.00%
cpu.ROB:occ_dist_1.max_value                      196                      
cpu.ROB:occ_dist_1.end_dist

cpu.ROB:occ_dist_2.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_2.samples                     334902                      
cpu.ROB:occ_dist_2.min_value                        0                      
                               0        38429              1147.47%
                               2         2415              1219.58%
                               4         3594              1326.90%
                               6         5480              1490.53%
                               8         8731              1751.23%
                              10         5401              1912.50%
                              12         6932              2119.49%
                              14         9370              2399.27%
                              16        11832              2752.57%
                              18        11331              3090.90%
                              20        16041              3569.88%
                              22        18281              4115.74%
                              24        18423              4665.84%
                              26        16199              5149.54%
                              28        16855              5652.82%
                              30        17134              6164.43%
                              32        12081              6525.16%
                              34        11113              6856.99%
                              36        11899              7212.29%
                              38         8619              7469.65%
                              40         7218              7685.17%
                              42         6441              7877.50%
                              44         6864              8082.45%
                              46         5739              8253.82%
                              48         4714              8394.58%
                              50         4514              8529.36%
                              52         4388              8660.38%
                              54         3497              8764.80%
                              56         2912              8851.75%
                              58         2574              8928.61%
                              60         2111              8991.65%
                              62         1950              9049.87%
                              64         1667              9099.65%
                              66         1821              9154.02%
                              68         1279              9192.21%
                              70          900              9219.08%
                              72          753              9241.57%
                              74          845              9266.80%
                              76          596              9284.60%
                              78          641              9303.74%
                              80          656              9323.32%
                              82          607              9341.45%
                              84          617              9359.87%
                              86          598              9377.73%
                              88          556              9394.33%
                              90          516              9409.74%
                              92          339              9419.86%
                              94          464              9433.71%
                              96          740              9455.81%
                              98          428              9468.59%
                             100          513              9483.91%
                             102          611              9502.15%
                             104          359              9512.87%
                             106          547              9529.21%
                             108          411              9541.48%
                             110          450              9554.91%
                             112          581              9572.26%
                             114          501              9587.22%
                             116          759              9609.89%
                             118          337              9619.95%
                             120          293              9628.70%
                             122          388              9640.28%
                             124          525              9655.96%
                             126          559              9672.65%
                             128          394              9684.42%
                             130          443              9697.64%
                             132          265              9705.56%
                             134          651              9724.99%
                             136          531              9740.85%
                             138          565              9757.72%
                             140          387              9769.28%
                             142          553              9785.79%
                             144          336              9795.82%
                             146          353              9806.36%
                             148          433              9819.29%
                             150          691              9839.92%
                             152          417              9852.37%
                             154          331              9862.26%
                             156          399              9874.17%
                             158          294              9882.95%
                             160          240              9890.12%
                             162          199              9896.06%
                             164          283              9904.51%
                             166          323              9914.15%
                             168          453              9927.68%
                             170          241              9934.88%
                             172          399              9946.79%
                             174          224              9953.48%
                             176          186              9959.03%
                             178           94              9961.84%
                             180           86              9964.41%
                             182          162              9969.24%
                             184           63              9971.13%
                             186          105              9974.26%
                             188           17              9974.77%
                             190          194              9980.56%
                             192           89              9983.22%
                             194           59              9984.98%
                             196          503             10000.00%
cpu.ROB:occ_dist_2.max_value                      196                      
cpu.ROB:occ_dist_2.end_dist

cpu.ROB:occ_dist_3.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_3.samples                     334902                      
cpu.ROB:occ_dist_3.min_value                        0                      
                               0       124504              3717.62%
                               2         6557              3913.41%
                               4         7178              4127.74%
                               6         7975              4365.87%
                               8        10454              4678.03%
                              10         7120              4890.62%
                              12         8985              5158.91%
                              14        10953              5485.96%
                              16        12446              5857.59%
                              18        11110              6189.33%
                              20        13394              6589.27%
                              22        15702              7058.12%
                              24        13114              7449.70%
                              26        12131              7811.93%
                              28        10225              8117.24%
                              30         9049              8387.44%
                              32         6799              8590.45%
                              34         5479              8754.05%
                              36         3520              8859.16%
                              38         3429              8961.55%
                              40         3410              9063.37%
                              42         3044              9154.26%
                              44         1821              9208.63%
                              46         2149              9272.80%
                              48         2041              9333.75%
                              50         1332              9373.52%
                              52         1782              9426.73%
                              54         1460              9470.32%
                              56          906              9497.38%
                              58         1032              9528.19%
                              60          983              9557.54%
                              62          991              9587.13%
                              64          868              9613.05%
                              66          807              9637.15%
                              68          685              9657.60%
                              70          586              9675.10%
                              72          573              9692.21%
                              74          589              9709.80%
                              76          514              9725.14%
                              78          597              9742.97%
                              80          279              9751.30%
                              82          496              9766.11%
                              84          504              9781.16%
                              86          245              9788.48%
                              88          467              9802.42%
                              90          311              9811.71%
                              92          208              9817.92%
                              94          231              9824.81%
                              96          169              9829.86%
                              98          270              9837.92%
                             100          207              9844.10%
                             102          170              9849.18%
                             104          279              9857.51%
                             106          275              9865.72%
                             108          199              9871.66%
                             110          284              9880.14%
                             112          251              9887.64%
                             114          139              9891.79%
                             116          181              9897.19%
                             118          125              9900.93%
                             120          133              9904.90%
                             122          132              9908.84%
                             124          222              9915.47%
                             126          142              9919.71%
                             128          195              9925.53%
                             130          110              9928.81%
                             132          110              9932.10%
                             134          127              9935.89%
                             136          160              9940.67%
                             138           87              9943.27%
                             140           74              9945.48%
                             142           70              9947.57%
                             144          154              9952.17%
                             146           89              9954.82%
                             148          124              9958.53%
                             150          138              9962.65%
                             152           78              9964.97%
                             154           57              9966.68%
                             156           73              9968.86%
                             158          110              9972.14%
                             160           79              9974.50%
                             162          135              9978.53%
                             164           46              9979.90%
                             166           75              9982.14%
                             168           60              9983.94%
                             170           35              9984.98%
                             172           24              9985.70%
                             174           35              9986.74%
                             176           73              9988.92%
                             178           25              9989.67%
                             180           19              9990.24%
                             182           34              9991.25%
                             184          122              9994.89%
                             186           87              9997.49%
                             188            2              9997.55%
                             190            1              9997.58%
                             192            1              9997.61%
                             194            0              9997.61%
                             196           80             10000.00%
cpu.ROB:occ_dist_3.max_value                      196                      
cpu.ROB:occ_dist_3.end_dist

cpu.ROB:occ_rate                            97.229610                       # ROB occupancy rate
cpu.ROB:occ_rate_0                          26.881831                       # ROB occupancy rate
cpu.ROB:occ_rate_1                          19.735078                       # ROB occupancy rate
cpu.ROB:occ_rate_2                          33.168222                       # ROB occupancy rate
cpu.ROB:occ_rate_3                          17.444479                       # ROB occupancy rate
cpu.ROB:occupancy                            32562391                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_0                           9002779                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_1                           6609317                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_2                          11108104                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_3                           5842191                       # cpu.ROB occupancy (cumulative)
cpu.SB:RQ:rdy_inst                             221300                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_0                            64392                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_1                            17009                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_2                            77871                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_3                            62028                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_dist_0_mean               0.192271                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_0_stdev              0.645893                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_0_TOT        334902                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_1_mean               0.050788                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_1_stdev              0.369682                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_1_TOT        334902                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_2_mean               0.232519                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_2_stdev              0.697190                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_2_TOT        334902                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_3_mean               0.185212                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_3_stdev              0.828030                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_3_TOT        334902                       # standard deviation of ready rate
cpu.SB:RQ:rdy_rate                           0.660790                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_0                         0.192271                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_1                         0.050788                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_2                         0.232519                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_3                         0.185212                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_x_count                          145840                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_0                         47819                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_1                         10318                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_2                         55832                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_3                         31871                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_max                                 8                       # largest number of insts that become ready
cpu.SB:RQ:rdy_x_rate                         0.435471                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_0                       0.142785                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_1                       0.030809                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_2                       0.166711                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_3                       0.095165                       # number of insts that become ready per cycle
cpu.SB:full_count                                1304                       # store buffer full events (cumulative)
cpu.SB:full_rate                             0.003894                       # store buffer full rate
cpu.SB:occ_rate                              4.038889                       # store buffer occupancy rate
cpu.SB:occ_rate_0                            0.626115                       # store buffer occupancy rate
cpu.SB:occ_rate_1                            0.385937                       # store buffer occupancy rate
cpu.SB:occ_rate_2                            0.787245                       # store buffer occupancy rate
cpu.SB:occ_rate_3                            2.239592                       # store buffer occupancy rate
cpu.SB:occupancy                              1352632                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_0                             209687                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_1                             129251                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_2                             263650                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_3                             750044                       # store buffer occupancy (cumulative)
cpu.SB:write_barrier_pending_cycles_0               0                       # number of cycles write barriers were pending
cpu.SB:write_barrier_pending_cycles_1               0                       # number of cycles write barriers were pending
cpu.SB:write_barrier_pending_cycles_2               0                       # number of cycles write barriers were pending
cpu.SB:write_barrier_pending_cycles_3               0                       # number of cycles write barriers were pending
cpu.SB:write_barriers                               0                       # number of write barrier operations
cpu.SB:write_barriers_0                             0                       # number of write barrier operations
cpu.SB:write_barriers_1                             0                       # number of write barrier operations
cpu.SB:write_barriers_2                             0                       # number of write barrier operations
cpu.SB:write_barriers_3                             0                       # number of write barrier operations
cpu.WB:consumers                              1738647                       # num instructions consuming a value
cpu.WB:consumers_0                             670810                       # num instructions consuming a value
cpu.WB:consumers_1                             144264                       # num instructions consuming a value
cpu.WB:consumers_2                             615141                       # num instructions consuming a value
cpu.WB:consumers_3                             308432                       # num instructions consuming a value
cpu.WB:count                                  1950942                       # cumulative count of insts written-back
cpu.WB:count_0                                 742931                       # cumulative count of insts written-back
cpu.WB:count_1                                 171925                       # cumulative count of insts written-back
cpu.WB:count_2                                 687403                       # cumulative count of insts written-back
cpu.WB:count_3                                 348683                       # cumulative count of insts written-back
cpu.WB:fanout                                0.918776                       # average fanout of values written-back
cpu.WB:fanout_0                              0.901570                       # average fanout of values written-back
cpu.WB:fanout_1                              0.980203                       # average fanout of values written-back
cpu.WB:fanout_2                              0.936093                       # average fanout of values written-back
cpu.WB:fanout_3                              0.892933                       # average fanout of values written-back
cpu.WB:penalized                                    0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_0                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_1                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_2                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_3                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_rate                               0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_0                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_1                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_2                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_3                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:pred_error.start_dist                                   # error in predicted writeback times
cpu.WB:pred_error.samples                     1950942                      
cpu.WB:pred_error.min_value                       147                      
                             -10            0      0.00%      0.00%
                              -9            0      0.00%      0.00%
                              -8            0      0.00%      0.00%
                              -7            0      0.00%      0.00%
                              -6            0      0.00%      0.00%
                              -5            0      0.00%      0.00%
                              -4            0      0.00%      0.00%
                              -3            0      0.00%      0.00%
                              -2            0      0.00%      0.00%
                              -1            0      0.00%      0.00%
                               0            0      0.00%      0.00%
                               1            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               3            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               5            0      0.00%      0.00%
                               6            0      0.00%      0.00%
                               7            0      0.00%      0.00%
                               8            0      0.00%      0.00%
                               9            0      0.00%      0.00%
                              10            0      0.00%      0.00%
                              11            0      0.00%      0.00%
                              12            0      0.00%      0.00%
                              13            0      0.00%      0.00%
                              14            0      0.00%      0.00%
                              15            0      0.00%      0.00%
                              16            0      0.00%      0.00%
                              17            0      0.00%      0.00%
                              18            0      0.00%      0.00%
                              19            0      0.00%      0.00%
                              20            0      0.00%      0.00%
                              21            0      0.00%      0.00%
                              22            0      0.00%      0.00%
                              23            0      0.00%      0.00%
                              24            0      0.00%      0.00%
                              25            0      0.00%      0.00%
                              26            0      0.00%      0.00%
                              27            0      0.00%      0.00%
                              28            0      0.00%      0.00%
                              29            0      0.00%      0.00%
                              30            0      0.00%      0.00%
                              31            0      0.00%      0.00%
                              32            0      0.00%      0.00%
                              33            0      0.00%      0.00%
                              34            0      0.00%      0.00%
                              35            0      0.00%      0.00%
                              36            0      0.00%      0.00%
                              37            0      0.00%      0.00%
                              38            0      0.00%      0.00%
                              39            0      0.00%      0.00%
                              40            0      0.00%      0.00%
                              41            0      0.00%      0.00%
                              42            0      0.00%      0.00%
                              43            0      0.00%      0.00%
                              44            0      0.00%      0.00%
                              45            0      0.00%      0.00%
                              46            0      0.00%      0.00%
                              47            0      0.00%      0.00%
                              48            0      0.00%      0.00%
                              49            0      0.00%      0.00%
                              50            0      0.00%      0.00%
                              51            0      0.00%      0.00%
                              52            0      0.00%      0.00%
                              53            0      0.00%      0.00%
                              54            0      0.00%      0.00%
                              55            0      0.00%      0.00%
                              56            0      0.00%      0.00%
                              57            0      0.00%      0.00%
                              58            0      0.00%      0.00%
                              59            0      0.00%      0.00%
                              60            0      0.00%      0.00%
                              61            0      0.00%      0.00%
                              62            0      0.00%      0.00%
                              63            0      0.00%      0.00%
                              64            0      0.00%      0.00%
                              65            0      0.00%      0.00%
                              66            0      0.00%      0.00%
                              67            0      0.00%      0.00%
                              68            0      0.00%      0.00%
                              69            0      0.00%      0.00%
                              70            0      0.00%      0.00%
                              71            0      0.00%      0.00%
                              72            0      0.00%      0.00%
                              73            0      0.00%      0.00%
                              74            0      0.00%      0.00%
                              75            0      0.00%      0.00%
                              76            0      0.00%      0.00%
                              77            0      0.00%      0.00%
                              78            0      0.00%      0.00%
                              79            0      0.00%      0.00%
                              80            0      0.00%      0.00%
                              81            0      0.00%      0.00%
                              82            0      0.00%      0.00%
                              83            0      0.00%      0.00%
                              84            0      0.00%      0.00%
                              85            0      0.00%      0.00%
                              86            0      0.00%      0.00%
                              87            0      0.00%      0.00%
                              88            0      0.00%      0.00%
                              89            0      0.00%      0.00%
                              90            0      0.00%      0.00%
                              91            0      0.00%      0.00%
                              92            0      0.00%      0.00%
                              93            0      0.00%      0.00%
                              94            0      0.00%      0.00%
                              95            0      0.00%      0.00%
                              96            0      0.00%      0.00%
                              97            0      0.00%      0.00%
                              98            0      0.00%      0.00%
                              99            0      0.00%      0.00%
                             100            0      0.00%      0.00%
cpu.WB:pred_error.overflows                   1950942                      
cpu.WB:pred_error.max_value                    334902                      
cpu.WB:pred_error.end_dist

cpu.WB:producers                              1597428                       # num instructions producing a value
cpu.WB:producers_0                             604782                       # num instructions producing a value
cpu.WB:producers_1                             141408                       # num instructions producing a value
cpu.WB:producers_2                             575829                       # num instructions producing a value
cpu.WB:producers_3                             275409                       # num instructions producing a value
cpu.WB:rate                                  5.825412                       # insts written-back per cycle
cpu.WB:rate_0                                2.218353                       # insts written-back per cycle
cpu.WB:rate_1                                0.513359                       # insts written-back per cycle
cpu.WB:rate_2                                2.052550                       # insts written-back per cycle
cpu.WB:rate_3                                1.041149                       # insts written-back per cycle
cpu.branch_pred.btb_accuracy                 0.995955                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_0                      1                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_1               0.970868                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_2                      1                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_3               0.987169                       # fraction of BTB targets correct
cpu.branch_pred.btb_correct                    122852                       # num correct BTB predictions
cpu.branch_pred.btb_correct_0                   53294                       # num correct BTB predictions
cpu.branch_pred.btb_correct_1                    8365                       # num correct BTB predictions
cpu.branch_pred.btb_correct_2                   42113                       # num correct BTB predictions
cpu.branch_pred.btb_correct_3                   19080                       # num correct BTB predictions
cpu.branch_pred.btb_hit_rate                 0.926362                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_0               0.976169                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_1               0.777062                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_2               0.982335                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_3               0.866393                       # BTB hit ratio
cpu.branch_pred.btb_hits                       219193                       # Number of BTB hits
cpu.branch_pred.btb_hits_0                      89913                       # Number of BTB hits
cpu.branch_pred.btb_hits_1                      22074                       # Number of BTB hits
cpu.branch_pred.btb_hits_2                      56055                       # Number of BTB hits
cpu.branch_pred.btb_hits_3                      51151                       # Number of BTB hits
cpu.branch_pred.btb_lookups                    236617                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_0                   92108                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_1                   28407                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_2                   57063                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_3                   59039                       # Number of BTB lookups
cpu.branch_pred.cond_correct                   125713                       # num correct dir predictions
cpu.branch_pred.cond_correct_0                  53545                       # num correct dir predictions
cpu.branch_pred.cond_correct_1                  11019                       # num correct dir predictions
cpu.branch_pred.cond_correct_2                  34530                       # num correct dir predictions
cpu.branch_pred.cond_correct_3                  26619                       # num correct dir predictions
cpu.branch_pred.cond_predicted                 134950                       # num committed conditional branches
cpu.branch_pred.cond_predicted_0                56174                       # num committed conditional branches
cpu.branch_pred.cond_predicted_1                12993                       # num committed conditional branches
cpu.branch_pred.cond_predicted_2                35872                       # num committed conditional branches
cpu.branch_pred.cond_predicted_3                29911                       # num committed conditional branches
cpu.branch_pred.dir_accuracy                 0.931552                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_0               0.953199                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_1               0.848072                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_2               0.962589                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_3               0.889940                       # fraction of predictions correct
cpu.branch_pred.lookup_rate                  1.040761                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_0                0.415548                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_1                0.120304                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_2                0.241297                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_3                0.263611                       # Rate of bpred lookups
cpu.branch_pred.lookups                        348553                       # num BP lookups
cpu.branch_pred.lookups_0                      139168                       # num BP lookups
cpu.branch_pred.lookups_1                       40290                       # num BP lookups
cpu.branch_pred.lookups_2                       80811                       # num BP lookups
cpu.branch_pred.lookups_3                       88284                       # num BP lookups
cpu.branch_pred.ras_accuracy                 0.964346                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_0               0.980181                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_1               0.851515                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_2               0.995527                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_3               0.861152                       # fraction of RAS targets correct
cpu.branch_pred.ras_correct                     16445                       # num correct RAS predictions
cpu.branch_pred.ras_correct_0                    4649                       # num correct RAS predictions
cpu.branch_pred.ras_correct_1                     562                       # num correct RAS predictions
cpu.branch_pred.ras_correct_2                    8902                       # num correct RAS predictions
cpu.branch_pred.ras_correct_3                    2332                       # num correct RAS predictions
cpu.branch_pred.used_btb                       123351                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_0                      53294                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_1                       8616                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_2                      42113                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_3                      19328                       # num committed branches using target from BTB
cpu.branch_pred.used_ras                        17053                       # num returns predicted using RAS
cpu.branch_pred.used_ras_0                       4743                       # num returns predicted using RAS
cpu.branch_pred.used_ras_1                        660                       # num returns predicted using RAS
cpu.branch_pred.used_ras_2                       8942                       # num returns predicted using RAS
cpu.branch_pred.used_ras_3                       2708                       # num returns predicted using RAS
cpu.dcache.advance_pool_dist.start_dist                        # Dist. of Repl. across pools
cpu.dcache.advance_pool_dist.samples            36156                      
cpu.dcache.advance_pool_dist.min_value              0                      
                               0         4740   1310.99%           
                               1         2345    648.58%           
                               2         1575    435.61%           
                               3         1217    336.60%           
                               4         1105    305.62%           
                               5         1047    289.58%           
                               6         1129    312.26%           
                               7         1190    329.13%           
                               8         1363    376.98%           
                               9         1069    295.66%           
                              10         1002    277.13%           
                              11          941    260.26%           
                              12         1084    299.81%           
                              13         1264    349.60%           
                              14         2106    582.48%           
                              15        10821   2992.86%           
                              16         2158    596.86%           
cpu.dcache.advance_pool_dist.max_value             16                      
cpu.dcache.advance_pool_dist.end_dist

cpu.dcache.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
cpu.dcache.avg_blocked_cycles_no_targets    88.511962                       # average number of cycles each access was blocked
cpu.dcache.avg_refs                        119.489077                       # Average number of references to valid blocks.
cpu.dcache.blocked_no_mshrs                         0                       # number of cycles access was blocked
cpu.dcache.blocked_no_targets                     209                       # number of cycles access was blocked
cpu.dcache.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
cpu.dcache.blocked_cycles_no_targets            18499                       # number of cycles access was blocked
cpu.dcache.cache_copies                             0                       # number of cache copies performed
cpu.dcache.demand_accesses                     520386                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_0                   211455                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_1                    44188                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_2                   186074                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_3                    78669                       # number of demand (read+write) accesses
cpu.dcache.demand_avg_miss_latency         110.599376                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_0        98.136937                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_1       113.331556                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_2       102.178620                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_3       111.169504                       # average overall miss latency
cpu.dcache.demand_avg_mshr_miss_latency    110.725445                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_0    99.611296                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_1   110.238589                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_2   104.002114                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_3   116.803746                       # average overall mshr miss latency
cpu.dcache.demand_hits                         508844                       # number of demand (read+write) hits
cpu.dcache.demand_hits_0                       210900                       # number of demand (read+write) hits
cpu.dcache.demand_hits_1                        40813                       # number of demand (read+write) hits
cpu.dcache.demand_hits_2                       185335                       # number of demand (read+write) hits
cpu.dcache.demand_hits_3                        71796                       # number of demand (read+write) hits
cpu.dcache.demand_miss_latency                1276538                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_0                54466                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_1               382494                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_2                75510                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_3               764068                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_rate                  0.022180                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_0                0.002625                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_1                0.076378                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_2                0.003972                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_3                0.087366                       # miss rate for demand accesses
cpu.dcache.demand_misses                        11542                       # number of demand (read+write) misses
cpu.dcache.demand_misses_0                        555                       # number of demand (read+write) misses
cpu.dcache.demand_misses_1                       3375                       # number of demand (read+write) misses
cpu.dcache.demand_misses_2                        739                       # number of demand (read+write) misses
cpu.dcache.demand_misses_3                       6873                       # number of demand (read+write) misses
cpu.dcache.demand_mshr_hits                      7612                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_0                     254                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_1                    1447                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_2                     266                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_3                    5645                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_miss_latency            435151                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_0           29983                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_1          212540                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_2           49193                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_3          143435                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_rate             0.007552                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_0           0.001423                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_1           0.043632                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_2           0.002542                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_3           0.015610                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_misses                    3930                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_0                   301                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_1                  1928                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_2                   473                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_3                  1228                       # number of demand (read+write) MSHR misses
cpu.dcache.demote_pool_dist.start_dist                         # Dist. of Repl. across pools
cpu.dcache.demote_pool_dist.samples            254238                      
cpu.dcache.demote_pool_dist.min_value               0                      
                               0       200106   7870.81%           
                               1         8632    339.52%           
                               2         6269    246.58%           
                               3         5544    218.06%           
                               4         5199    204.49%           
                               5         5113    201.11%           
                               6         5075    199.62%           
                               7         5177    203.63%           
                               8         3182    125.16%           
                               9         1216     47.83%           
                              10          927     36.46%           
                              11          860     33.83%           
                              12          803     31.58%           
                              13          948     37.29%           
                              14         1132     44.53%           
                              15         1986     78.12%           
                              16         2069     81.38%           
cpu.dcache.demote_pool_dist.max_value              16                      
cpu.dcache.demote_pool_dist.end_dist

cpu.dcache.fast_writes                            265                       # number of fast writes performed
cpu.dcache.hash_hit                            508665                       # Total of hites in hash table
cpu.dcache.hash_miss                            11913                       # Total of misses in hash table
cpu.dcache.hit_depth_total                     508665                       # Total of hit depths
cpu.dcache.hit_hash_depth_dist.start_dist                      # Dist. of Hash lookup depths
cpu.dcache.hit_hash_depth_dist.samples         508665                      
cpu.dcache.hit_hash_depth_dist.min_value            1                      
                               0            0      0.00%           
                               1       508665  10000.00%           
                               2            0      0.00%           
                               3            0      0.00%           
                               4            0      0.00%           
                               5            0      0.00%           
                               6            0      0.00%           
                               7            0      0.00%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
                              17            0      0.00%           
                              18            0      0.00%           
                              19            0      0.00%           
                              20            0      0.00%           
cpu.dcache.hit_hash_depth_dist.max_value            1                      
cpu.dcache.hit_hash_depth_dist.end_dist

cpu.dcache.miss_depth_total                     16255                       # Total of miss depths
cpu.dcache.miss_hash_depth_dist.start_dist                     # Dist. of Hash lookup depths
cpu.dcache.miss_hash_depth_dist.samples         11913                      
cpu.dcache.miss_hash_depth_dist.min_value            1                      
                               0            0      0.00%           
                               1         9109   7646.27%           
                               2         1647   1382.52%           
                               3          876    735.33%           
                               4          202    169.56%           
                               5           59     49.53%           
                               6           19     15.95%           
                               7            1      0.84%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
                              17            0      0.00%           
                              18            0      0.00%           
                              19            0      0.00%           
                              20            0      0.00%           
cpu.dcache.miss_hash_depth_dist.max_value            7                      
cpu.dcache.miss_hash_depth_dist.end_dist

cpu.dcache.mshr_cap_events                          0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_0                        0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_1                        0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_2                        0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_3                        0                       # number of times MSHR cap was activated
cpu.dcache.no_allocate_misses                       0                       # Number of misses that were no-allocate
cpu.dcache.overall_accesses                    520578                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_0                  211455                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_1                   44212                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_2                  186090                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_3                   78821                       # number of overall (read+write) accesses
cpu.dcache.overall_avg_miss_latency        110.724073                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_0       98.136937                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_1      113.292762                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_2      102.566265                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_3      111.353972                       # average overall miss latency
cpu.dcache.overall_avg_mshr_miss_latency   110.943401                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_0    99.611296                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_1   110.222567                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_2   104.523909                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_3   117.113370                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_2 <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_3 <err: div-0>                       # average overall mshr uncacheable latency
cpu.dcache.overall_hits                        508930                       # number of overall hits
cpu.dcache.overall_hits_0                      210900                       # number of overall hits
cpu.dcache.overall_hits_1                       40827                       # number of overall hits
cpu.dcache.overall_hits_2                      185343                       # number of overall hits
cpu.dcache.overall_hits_3                       71860                       # number of overall hits
cpu.dcache.overall_miss_latency               1289714                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_0               54466                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_1              383496                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_2               76617                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_3              775135                       # number of overall miss cycles
cpu.dcache.overall_miss_rate                 0.022375                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_0               0.002625                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_1               0.076563                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_2               0.004014                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_3               0.088314                       # miss rate for overall accesses
cpu.dcache.overall_misses                       11648                       # number of overall misses
cpu.dcache.overall_misses_0                       555                       # number of overall misses
cpu.dcache.overall_misses_1                      3385                       # number of overall misses
cpu.dcache.overall_misses_2                       747                       # number of overall misses
cpu.dcache.overall_misses_3                      6961                       # number of overall misses
cpu.dcache.overall_mshr_hits                     7655                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_0                    254                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_1                   1453                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_2                    266                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_3                   5682                       # number of overall MSHR hits
cpu.dcache.overall_mshr_miss_latency           442997                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_0          29983                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_1         212950                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_2          50276                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_3         149788                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_rate            0.007670                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_0          0.001423                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_1          0.043699                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_2          0.002585                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_3          0.016227                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_misses                   3993                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_0                  301                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_1                 1932                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_2                  481                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_3                 1279                       # number of overall MSHR misses
cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_2            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_3            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_2            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_3            0                       # number of overall MSHR uncacheable misses
cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.dcache.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
cpu.dcache.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.dcache.read_accesses                       374546                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_0                     163636                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_1                      33870                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_2                     130242                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_3                      46798                       # number of read accesses(hits+misses)
cpu.dcache.read_avg_miss_latency           106.273524                       # average read miss latency
cpu.dcache.read_avg_miss_latency_0          97.229205                       # average read miss latency
cpu.dcache.read_avg_miss_latency_1         114.115959                       # average read miss latency
cpu.dcache.read_avg_miss_latency_2          99.888693                       # average read miss latency
cpu.dcache.read_avg_miss_latency_3          98.439869                       # average read miss latency
cpu.dcache.read_avg_mshr_miss_latency      105.963619                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_0     99.295302                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_1    109.851934                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_2    100.549763                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_3    101.161458                       # average read mshr miss latency
cpu.dcache.read_hits                           369296                       # number of read hits
cpu.dcache.read_hits_0                         163095                       # number of read hits
cpu.dcache.read_hits_1                          31257                       # number of read hits
cpu.dcache.read_hits_2                         129676                       # number of read hits
cpu.dcache.read_hits_3                          45268                       # number of read hits
cpu.dcache.read_miss_latency                   557936                       # number of read miss cycles
cpu.dcache.read_miss_latency_0                  52601                       # number of read miss cycles
cpu.dcache.read_miss_latency_1                 298185                       # number of read miss cycles
cpu.dcache.read_miss_latency_2                  56537                       # number of read miss cycles
cpu.dcache.read_miss_latency_3                 150613                       # number of read miss cycles
cpu.dcache.read_miss_rate                    0.014017                       # miss rate for read accesses
cpu.dcache.read_miss_rate_0                  0.003306                       # miss rate for read accesses
cpu.dcache.read_miss_rate_1                  0.077148                       # miss rate for read accesses
cpu.dcache.read_miss_rate_2                  0.004346                       # miss rate for read accesses
cpu.dcache.read_miss_rate_3                  0.032694                       # miss rate for read accesses
cpu.dcache.read_misses                           5250                       # number of read misses
cpu.dcache.read_misses_0                          541                       # number of read misses
cpu.dcache.read_misses_1                         2613                       # number of read misses
cpu.dcache.read_misses_2                          566                       # number of read misses
cpu.dcache.read_misses_3                         1530                       # number of read misses
cpu.dcache.read_mshr_hits                        2144                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_0                       243                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_1                       803                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_2                       144                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_3                       954                       # number of read MSHR hits
cpu.dcache.read_mshr_miss_latency              329123                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_0             29590                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_1            198832                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_2             42432                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_3             58269                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_rate               0.008293                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_0             0.001821                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_1             0.053440                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_2             0.003240                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_3             0.012308                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_misses                      3106                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_0                     298                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_1                    1810                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_2                     422                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_3                     576                       # number of read MSHR misses
cpu.dcache.repl_pool_dist.start_dist                           # Dist. of Repl. across pools
cpu.dcache.repl_pool_dist.samples                3233                      
cpu.dcache.repl_pool_dist.min_value                 0                      
                               0         3233  10000.00%           
                               1            0      0.00%           
                               2            0      0.00%           
                               3            0      0.00%           
                               4            0      0.00%           
                               5            0      0.00%           
                               6            0      0.00%           
                               7            0      0.00%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
cpu.dcache.repl_pool_dist.max_value                 0                      
cpu.dcache.repl_pool_dist.end_dist

cpu.dcache.replacements                          3233                       # number of replacements
cpu.dcache.replacements_0                         147                       # number of replacements
cpu.dcache.replacements_1                        1575                       # number of replacements
cpu.dcache.replacements_2                         392                       # number of replacements
cpu.dcache.replacements_3                        1119                       # number of replacements
cpu.dcache.sampled_refs                          4257                       # Sample count of references to valid blocks.
cpu.dcache.set_access_dist.start_dist                          # Dist. of Accesses across sets
cpu.dcache.set_access_dist.samples             520578                      
cpu.dcache.set_access_dist.min_value                0                      
                               0           92      1.77%           
                               1           46      0.88%           
                               2           66      1.27%           
                               3           61      1.17%           
                               4           50      0.96%           
                               5           63      1.21%           
                               6          428      8.22%           
                               7         7289    140.02%           
                               8         5300    101.81%           
                               9        36900    708.83%           
                              10          137      2.63%           
                              11           99      1.90%           
                              12           51      0.98%           
                              13           74      1.42%           
                              14           47      0.90%           
                              15           51      0.98%           
                              16           63      1.21%           
                              17           55      1.06%           
                              18           67      1.29%           
                              19           65      1.25%           
                              20           77      1.48%           
                              21           87      1.67%           
                              22           49      0.94%           
                              23           67      1.29%           
                              24           86      1.65%           
                              25           72      1.38%           
                              26          115      2.21%           
                              27         1662     31.93%           
                              28           81      1.56%           
                              29           97      1.86%           
                              30           43      0.83%           
                              31         9669    185.74%           
                              32           56      1.08%           
                              33           67      1.29%           
                              34          758     14.56%           
                              35           61      1.17%           
                              36           61      1.17%           
                              37           66      1.27%           
                              38           49      0.94%           
                              39           66      1.27%           
                              40           43      0.83%           
                              41         9533    183.12%           
                              42           79      1.52%           
                              43           67      1.29%           
                              44          206      3.96%           
                              45          193      3.71%           
                              46          105      2.02%           
                              47           56      1.08%           
                              48           46      0.88%           
                              49           90      1.73%           
                              50         3895     74.82%           
                              51          963     18.50%           
                              52           45      0.86%           
                              53           31      0.60%           
                              54           49      0.94%           
                              55          150      2.88%           
                              56          386      7.41%           
                              57          299      5.74%           
                              58          176      3.38%           
                              59         1077     20.69%           
                              60          108      2.07%           
                              61           91      1.75%           
                              62          664     12.76%           
                              63          122      2.34%           
                              64          411      7.90%           
                              65          178      3.42%           
                              66          125      2.40%           
                              67          293      5.63%           
                              68         5524    106.11%           
                              69         7685    147.62%           
                              70          352      6.76%           
                              71          875     16.81%           
                              72        10327    198.38%           
                              73        85564   1643.63%           
                              74        20262    389.22%           
                              75        19226    369.32%           
                              76         7687    147.66%           
                              77          117      2.25%           
                              78        21895    420.59%           
                              79          263      5.05%           
                              80           32      0.61%           
                              81          346      6.65%           
                              82           46      0.88%           
                              83           44      0.85%           
                              84          224      4.30%           
                              85          244      4.69%           
                              86          864     16.60%           
                              87           91      1.75%           
                              88          189      3.63%           
                              89          189      3.63%           
                              90         9081    174.44%           
                              91          279      5.36%           
                              92        11114    213.49%           
                              93          417      8.01%           
                              94          232      4.46%           
                              95          577     11.08%           
                              96         4045     77.70%           
                              97          460      8.84%           
                              98          517      9.93%           
                              99         3443     66.14%           
                             100         2212     42.49%           
                             101         6410    123.13%           
                             102         1832     35.19%           
                             103          910     17.48%           
                             104          179      3.44%           
                             105         4544     87.29%           
                             106         1156     22.21%           
                             107         1096     21.05%           
                             108          311      5.97%           
                             109          244      4.69%           
                             110         2594     49.83%           
                             111          590     11.33%           
                             112          192      3.69%           
                             113          174      3.34%           
                             114          159      3.05%           
                             115          190      3.65%           
                             116          280      5.38%           
                             117          398      7.65%           
                             118          205      3.94%           
                             119          206      3.96%           
                             120         1181     22.69%           
                             121          176      3.38%           
                             122          289      5.55%           
                             123         1120     21.51%           
                             124          274      5.26%           
                             125          283      5.44%           
                             126          322      6.19%           
                             127          309      5.94%           
                             128          362      6.95%           
                             129          355      6.82%           
                             130          401      7.70%           
                             131          403      7.74%           
                             132          317      6.09%           
                             133          314      6.03%           
                             134          304      5.84%           
                             135          344      6.61%           
                             136          429      8.24%           
                             137          379      7.28%           
                             138          387      7.43%           
                             139          433      8.32%           
                             140          372      7.15%           
                             141          384      7.38%           
                             142          389      7.47%           
                             143          354      6.80%           
                             144          322      6.19%           
                             145          347      6.67%           
                             146          350      6.72%           
                             147          332      6.38%           
                             148          301      5.78%           
                             149          290      5.57%           
                             150          316      6.07%           
                             151          363      6.97%           
                             152          369      7.09%           
                             153          314      6.03%           
                             154          306      5.88%           
                             155          296      5.69%           
                             156          492      9.45%           
                             157          503      9.66%           
                             158         1366     26.24%           
                             159         1195     22.96%           
                             160          976     18.75%           
                             161          807     15.50%           
                             162         1530     29.39%           
                             163         1240     23.82%           
                             164         1777     34.14%           
                             165         1657     31.83%           
                             166         2521     48.43%           
                             167         2042     39.23%           
                             168         3380     64.93%           
                             169         3110     59.74%           
                             170         4407     84.66%           
                             171         3891     74.74%           
                             172          444      8.53%           
                             173          401      7.70%           
                             174          386      7.41%           
                             175          430      8.26%           
                             176          419      8.05%           
                             177          610     11.72%           
                             178          442      8.49%           
                             179          469      9.01%           
                             180          417      8.01%           
                             181          411      7.90%           
                             182          566     10.87%           
                             183          524     10.07%           
                             184          396      7.61%           
                             185          320      6.15%           
                             186          346      6.65%           
                             187          419      8.05%           
                             188          334      6.42%           
                             189          378      7.26%           
                             190          406      7.80%           
                             191          518      9.95%           
                             192          220      4.23%           
                             193          211      4.05%           
                             194          204      3.92%           
                             195          225      4.32%           
                             196          266      5.11%           
                             197          251      4.82%           
                             198          219      4.21%           
                             199          198      3.80%           
                             200          242      4.65%           
                             201          234      4.50%           
                             202          279      5.36%           
                             203          235      4.51%           
                             204          251      4.82%           
                             205          216      4.15%           
                             206          224      4.30%           
                             207          245      4.71%           
                             208          285      5.47%           
                             209          347      6.67%           
                             210          289      5.55%           
                             211          367      7.05%           
                             212          351      6.74%           
                             213          285      5.47%           
                             214         2192     42.11%           
                             215         2306     44.30%           
                             216          204      3.92%           
                             217          235      4.51%           
                             218          250      4.80%           
                             219          312      5.99%           
                             220          269      5.17%           
                             221          508      9.76%           
                             222          195      3.75%           
                             223          245      4.71%           
                             224          518      9.95%           
                             225          263      5.05%           
                             226          252      4.84%           
                             227          240      4.61%           
                             228          241      4.63%           
                             229          518      9.95%           
                             230          432      8.30%           
                             231          263      5.05%           
                             232          285      5.47%           
                             233          314      6.03%           
                             234          276      5.30%           
                             235          327      6.28%           
                             236          398      7.65%           
                             237          713     13.70%           
                             238          335      6.44%           
                             239          361      6.93%           
                             240          234      4.50%           
                             241          264      5.07%           
                             242          243      4.67%           
                             243          253      4.86%           
                             244          269      5.17%           
                             245         1080     20.75%           
                             246        10667    204.91%           
                             247          258      4.96%           
                             248          300      5.76%           
                             249          242      4.65%           
                             250          229      4.40%           
                             251          235      4.51%           
                             252          222      4.26%           
                             253          258      4.96%           
                             254          271      5.21%           
                             255          265      5.09%           
                             256         1854     35.61%           
                             257          369      7.09%           
                             258          150      2.88%           
                             259          226      4.34%           
                             260           78      1.50%           
                             261           64      1.23%           
                             262          149      2.86%           
                             263          139      2.67%           
                             264           83      1.59%           
                             265          723     13.89%           
                             266          288      5.53%           
                             267          150      2.88%           
                             268          189      3.63%           
                             269          885     17.00%           
                             270          883     16.96%           
                             271         1004     19.29%           
                             272        24341    467.58%           
                             273          163      3.13%           
                             274         1268     24.36%           
                             275          398      7.65%           
                             276          126      2.42%           
                             277           96      1.84%           
                             278         1951     37.48%           
                             279          906     17.40%           
                             280          117      2.25%           
                             281          650     12.49%           
                             282          372      7.15%           
                             283          135      2.59%           
                             284          155      2.98%           
                             285          177      3.40%           
                             286          145      2.79%           
                             287           90      1.73%           
                             288          543     10.43%           
                             289          153      2.94%           
                             290          419      8.05%           
                             291          567     10.89%           
                             292          569     10.93%           
                             293          157      3.02%           
                             294          126      2.42%           
                             295           62      1.19%           
                             296          721     13.85%           
                             297          401      7.70%           
                             298          453      8.70%           
                             299          873     16.77%           
                             300          362      6.95%           
                             301         1210     23.24%           
                             302          158      3.04%           
                             303          454      8.72%           
                             304          441      8.47%           
                             305          146      2.80%           
                             306          557     10.70%           
                             307          582     11.18%           
                             308          103      1.98%           
                             309          791     15.19%           
                             310          147      2.82%           
                             311          209      4.01%           
                             312          405      7.78%           
                             313           72      1.38%           
                             314          543     10.43%           
                             315          286      5.49%           
                             316          405      7.78%           
                             317          440      8.45%           
                             318          475      9.12%           
                             319          250      4.80%           
                             320          177      3.40%           
                             321          417      8.01%           
                             322          186      3.57%           
                             323          444      8.53%           
                             324          163      3.13%           
                             325          209      4.01%           
                             326          312      5.99%           
                             327          177      3.40%           
                             328          495      9.51%           
                             329          839     16.12%           
                             330          647     12.43%           
                             331          468      8.99%           
                             332          737     14.16%           
                             333          384      7.38%           
                             334          435      8.36%           
                             335          595     11.43%           
                             336          244      4.69%           
                             337          126      2.42%           
                             338          342      6.57%           
                             339          534     10.26%           
                             340          716     13.75%           
                             341          434      8.34%           
                             342          152      2.92%           
                             343          691     13.27%           
                             344          719     13.81%           
                             345          125      2.40%           
                             346          216      4.15%           
                             347          462      8.87%           
                             348          190      3.65%           
                             349          466      8.95%           
                             350          393      7.55%           
                             351          242      4.65%           
                             352          349      6.70%           
                             353         9202    176.77%           
                             354         8720    167.51%           
                             355         1300     24.97%           
                             356          720     13.83%           
                             357          877     16.85%           
                             358          151      2.90%           
                             359          989     19.00%           
                             360          227      4.36%           
                             361          319      6.13%           
                             362          880     16.90%           
                             363          793     15.23%           
                             364          141      2.71%           
                             365           99      1.90%           
                             366          602     11.56%           
                             367          414      7.95%           
                             368          351      6.74%           
                             369          745     14.31%           
                             370           31      0.60%           
                             371          339      6.51%           
                             372          208      4.00%           
                             373          269      5.17%           
                             374         2259     43.39%           
                             375         1484     28.51%           
                             376           57      1.09%           
                             377          560     10.76%           
                             378          497      9.55%           
                             379          280      5.38%           
                             380          652     12.52%           
                             381          441      8.47%           
                             382          510      9.80%           
                             383           70      1.34%           
                             384           48      0.92%           
                             385           48      0.92%           
                             386           67      1.29%           
                             387           63      1.21%           
                             388           86      1.65%           
                             389           59      1.13%           
                             390         3138     60.28%           
                             391         2603     50.00%           
                             392           71      1.36%           
                             393          113      2.17%           
                             394           95      1.82%           
                             395          222      4.26%           
                             396           62      1.19%           
                             397           42      0.81%           
                             398           48      0.92%           
                             399           59      1.13%           
                             400           58      1.11%           
                             401           73      1.40%           
                             402          375      7.20%           
                             403           54      1.04%           
                             404           54      1.04%           
                             405           66      1.27%           
                             406           54      1.04%           
                             407           59      1.13%           
                             408           59      1.13%           
                             409           48      0.92%           
                             410           48      0.92%           
                             411           48      0.92%           
                             412           53      1.02%           
                             413           57      1.09%           
                             414           85      1.63%           
                             415           42      0.81%           
                             416           44      0.85%           
                             417           51      0.98%           
                             418           45      0.86%           
                             419           78      1.50%           
                             420           21      0.40%           
                             421           27      0.52%           
                             422           63      1.21%           
                             423           48      0.92%           
                             424         2276     43.72%           
                             425           72      1.38%           
                             426           98      1.88%           
                             427           60      1.15%           
                             428           52      1.00%           
                             429           51      0.98%           
                             430           52      1.00%           
                             431           80      1.54%           
                             432           35      0.67%           
                             433           38      0.73%           
                             434           38      0.73%           
                             435           31      0.60%           
                             436           34      0.65%           
                             437           34      0.65%           
                             438           23      0.44%           
                             439           32      0.61%           
                             440           33      0.63%           
                             441          106      2.04%           
                             442           75      1.44%           
                             443           31      0.60%           
                             444           30      0.58%           
                             445           35      0.67%           
                             446           37      0.71%           
                             447           35      0.67%           
                             448           26      0.50%           
                             449           36      0.69%           
                             450           26      0.50%           
                             451           26      0.50%           
                             452           36      0.69%           
                             453           46      0.88%           
                             454           46      0.88%           
                             455           25      0.48%           
                             456           22      0.42%           
                             457           25      0.48%           
                             458           35      0.67%           
                             459           12      0.23%           
                             460           15      0.29%           
                             461           56      1.08%           
                             462           25      0.48%           
                             463           39      0.75%           
                             464           44      0.85%           
                             465           95      1.82%           
                             466           22      0.42%           
                             467           40      0.77%           
                             468           13      0.25%           
                             469           13      0.25%           
                             470           14      0.27%           
                             471           29      0.56%           
                             472           18      0.35%           
                             473           10      0.19%           
                             474           14      0.27%           
                             475           18      0.35%           
                             476           23      0.44%           
                             477           24      0.46%           
                             478           21      0.40%           
                             479           30      0.58%           
                             480           17      0.33%           
                             481           14      0.27%           
                             482           22      0.42%           
                             483           14      0.27%           
                             484           11      0.21%           
                             485           29      0.56%           
                             486           41      0.79%           
                             487           38      0.73%           
                             488           43      0.83%           
                             489           54      1.04%           
                             490           41      0.79%           
                             491           34      0.65%           
                             492           31      0.60%           
                             493           54      1.04%           
                             494           70      1.34%           
                             495           42      0.81%           
                             496           38      0.73%           
                             497           56      1.08%           
                             498           37      0.71%           
                             499           40      0.77%           
                             500           52      1.00%           
                             501           44      0.85%           
                             502           66      1.27%           
                             503           26      0.50%           
                             504          174      3.34%           
                             505           49      0.94%           
                             506           44      0.85%           
                             507           31      0.60%           
                             508         1178     22.63%           
                             509          149      2.86%           
                             510           23      0.44%           
                             511           23      0.44%           
                             512            0      0.00%           
cpu.dcache.set_access_dist.max_value              511                      
cpu.dcache.set_access_dist.end_dist

cpu.dcache.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_0                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_1                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_2                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_3                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.swpf_accesses                          192                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_1                         24                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_2                         16                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_3                        152                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_avg_miss_latency           124.301887                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_1         100.200000                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_2         138.375000                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_3         125.761364                       # average swpf miss latency
cpu.dcache.swpf_avg_mshr_miss_latency      124.539683                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_1    102.500000                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_2    135.375000                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_3    124.568627                       # average swpf mshr miss latency
cpu.dcache.swpf_hits                               86                       # number of swpf hits
cpu.dcache.swpf_hits_1                             14                       # number of swpf hits
cpu.dcache.swpf_hits_2                              8                       # number of swpf hits
cpu.dcache.swpf_hits_3                             64                       # number of swpf hits
cpu.dcache.swpf_miss_latency                    13176                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_1                   1002                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_2                   1107                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_3                  11067                       # number of swpf miss cycles
cpu.dcache.swpf_miss_rate                    0.552083                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_1                  0.416667                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_2                  0.500000                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_3                  0.578947                       # miss rate for swpf accesses
cpu.dcache.swpf_misses                            106                       # number of swpf misses
cpu.dcache.swpf_misses_1                           10                       # number of swpf misses
cpu.dcache.swpf_misses_2                            8                       # number of swpf misses
cpu.dcache.swpf_misses_3                           88                       # number of swpf misses
cpu.dcache.swpf_mshr_hits                          43                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_1                         6                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_3                        37                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_miss_latency                7846                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_1               410                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_2              1083                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_3              6353                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_rate               0.328125                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_1             0.166667                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_2             0.500000                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_3             0.335526                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_misses                        63                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_1                       4                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_2                       8                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_3                      51                       # number of swpf MSHR misses
cpu.dcache.tagsinuse                       920.372210                       # Cycle average of tags in use
cpu.dcache.total_refs                          508665                       # Total number of references to valid blocks.
cpu.dcache.warmup_cycle                         81079                       # Cycle when the warmup percentage was hit.
cpu.dcache.write_accesses                      145840                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_0                     47819                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_1                     10318                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_2                     55832                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_3                     31871                       # number of write accesses(hits+misses)
cpu.dcache.write_avg_miss_latency          114.208837                       # average write miss latency
cpu.dcache.write_avg_miss_latency_0        133.214286                       # average write miss latency
cpu.dcache.write_avg_miss_latency_1        110.641732                       # average write miss latency
cpu.dcache.write_avg_miss_latency_2        109.670520                       # average write miss latency
cpu.dcache.write_avg_miss_latency_3        114.814711                       # average write miss latency
cpu.dcache.write_avg_mshr_miss_latency     128.674757                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_0          131                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_1   116.169492                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_2   132.568627                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_3   130.622699                       # average write mshr miss latency
cpu.dcache.write_hits                          139548                       # number of write hits
cpu.dcache.write_hits_0                         47805                       # number of write hits
cpu.dcache.write_hits_1                          9556                       # number of write hits
cpu.dcache.write_hits_2                         55659                       # number of write hits
cpu.dcache.write_hits_3                         26528                       # number of write hits
cpu.dcache.write_miss_latency                  718602                       # number of write miss cycles
cpu.dcache.write_miss_latency_0                  1865                       # number of write miss cycles
cpu.dcache.write_miss_latency_1                 84309                       # number of write miss cycles
cpu.dcache.write_miss_latency_2                 18973                       # number of write miss cycles
cpu.dcache.write_miss_latency_3                613455                       # number of write miss cycles
cpu.dcache.write_miss_rate                   0.043143                       # miss rate for write accesses
cpu.dcache.write_miss_rate_0                 0.000293                       # miss rate for write accesses
cpu.dcache.write_miss_rate_1                 0.073852                       # miss rate for write accesses
cpu.dcache.write_miss_rate_2                 0.003099                       # miss rate for write accesses
cpu.dcache.write_miss_rate_3                 0.167645                       # miss rate for write accesses
cpu.dcache.write_misses                          6292                       # number of write misses
cpu.dcache.write_misses_0                          14                       # number of write misses
cpu.dcache.write_misses_1                         762                       # number of write misses
cpu.dcache.write_misses_2                         173                       # number of write misses
cpu.dcache.write_misses_3                        5343                       # number of write misses
cpu.dcache.write_mshr_hits                       5468                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_0                       11                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_1                      644                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_2                      122                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_3                     4691                       # number of write MSHR hits
cpu.dcache.write_mshr_miss_latency             106028                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_0              393                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_1            13708                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_2             6761                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_3            85166                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_rate              0.005650                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_0            0.000063                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_1            0.011436                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_2            0.000913                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_3            0.020457                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_misses                      824                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_0                      3                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_1                    118                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_2                     51                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_3                    652                       # number of write MSHR misses
cpu.dcache.writebacks                            1082                       # number of writebacks
cpu.dcache.writebacks_0                             6                       # number of writebacks
cpu.dcache.writebacks_1                           125                       # number of writebacks
cpu.dcache.writebacks_2                           214                       # number of writebacks
cpu.dcache.writebacks_3                           737                       # number of writebacks
cpu.floss.fetch_0.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_0.end_dist
cpu.floss.fetch_1.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_1.end_dist
cpu.floss.fetch_2.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_2.end_dist
cpu.floss.fetch_3.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_3.end_dist
cpu.floss.icache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_0.end_dist
cpu.floss.icache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_1.end_dist
cpu.floss.icache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_2.end_dist
cpu.floss.icache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_3.end_dist
cpu.floss.iq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_0.end_dist
cpu.floss.iq_full_1.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_1.end_dist
cpu.floss.iq_full_2.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_2.end_dist
cpu.floss.iq_full_3.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_3.end_dist
cpu.floss.iq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_0.end_dist
cpu.floss.iq_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_1.end_dist
cpu.floss.iq_full_dcache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_2.end_dist
cpu.floss.iq_full_dcache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_3.end_dist
cpu.floss.iq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_0.end_dist
cpu.floss.iq_full_deps_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_1.end_dist
cpu.floss.iq_full_deps_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_2.end_dist
cpu.floss.iq_full_deps_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_3.end_dist
cpu.floss.iq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_0.end_dist
cpu.floss.iq_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_1.end_dist
cpu.floss.iq_full_fu_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_2.end_dist
cpu.floss.iq_full_fu_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_3.end_dist
cpu.floss.lsq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_0.end_dist
cpu.floss.lsq_full_1.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_1.end_dist
cpu.floss.lsq_full_2.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_2.end_dist
cpu.floss.lsq_full_3.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_3.end_dist
cpu.floss.lsq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_0.end_dist
cpu.floss.lsq_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_1.end_dist
cpu.floss.lsq_full_dcache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_2.end_dist
cpu.floss.lsq_full_dcache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_3.end_dist
cpu.floss.lsq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_0.end_dist
cpu.floss.lsq_full_deps_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_1.end_dist
cpu.floss.lsq_full_deps_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_2.end_dist
cpu.floss.lsq_full_deps_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_3.end_dist
cpu.floss.lsq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_0.end_dist
cpu.floss.lsq_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_1.end_dist
cpu.floss.lsq_full_fu_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_2.end_dist
cpu.floss.lsq_full_fu_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_3.end_dist
cpu.floss.qfull_0.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_0.end_dist
cpu.floss.qfull_1.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_1.end_dist
cpu.floss.qfull_2.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_2.end_dist
cpu.floss.qfull_3.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_3.end_dist
cpu.floss.rob_full_0.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_0.end_dist
cpu.floss.rob_full_1.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_1.end_dist
cpu.floss.rob_full_2.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_2.end_dist
cpu.floss.rob_full_3.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_3.end_dist
cpu.floss.rob_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_0.end_dist
cpu.floss.rob_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_1.end_dist
cpu.floss.rob_full_dcache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_2.end_dist
cpu.floss.rob_full_dcache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_3.end_dist
cpu.floss.rob_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_0.end_dist
cpu.floss.rob_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_1.end_dist
cpu.floss.rob_full_fu_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_2.end_dist
cpu.floss.rob_full_fu_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_3.end_dist
cpu.icache.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
cpu.icache.avg_refs                         90.985732                       # Average number of references to valid blocks.
cpu.icache.blocked_no_mshrs                         0                       # number of cycles access was blocked
cpu.icache.blocked_no_targets                       0                       # number of cycles access was blocked
cpu.icache.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
cpu.icache.blocked_cycles_no_targets                0                       # number of cycles access was blocked
cpu.icache.cache_copies                             0                       # number of cache copies performed
cpu.icache.demand_accesses                     600757                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_0                   197851                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_1                    68882                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_2                   184525                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_3                   149499                       # number of demand (read+write) accesses
cpu.icache.demand_avg_miss_latency          34.620462                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_0        23.047423                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_1        35.847576                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_2        56.515152                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_3        32.093527                       # average overall miss latency
cpu.icache.demand_avg_mshr_miss_latency     54.379565                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_0    31.118644                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_1    53.015441                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_2    87.389189                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_3    55.510719                       # average overall mshr miss latency
cpu.icache.demand_hits                         593045                       # number of demand (read+write) hits
cpu.icache.demand_hits_0                       197366                       # number of demand (read+write) hits
cpu.icache.demand_hits_1                        65313                       # number of demand (read+write) hits
cpu.icache.demand_hits_2                       184096                       # number of demand (read+write) hits
cpu.icache.demand_hits_3                       146270                       # number of demand (read+write) hits
cpu.icache.demand_miss_latency                 266993                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_0                11178                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_1               127940                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_2                24245                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_3               103630                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_rate                  0.012837                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_0                0.002451                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_1                0.051813                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_2                0.002325                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_3                0.021599                       # miss rate for demand accesses
cpu.icache.demand_misses                         7712                       # number of demand (read+write) misses
cpu.icache.demand_misses_0                        485                       # number of demand (read+write) misses
cpu.icache.demand_misses_1                       3569                       # number of demand (read+write) misses
cpu.icache.demand_misses_2                        429                       # number of demand (read+write) misses
cpu.icache.demand_misses_3                       3229                       # number of demand (read+write) misses
cpu.icache.demand_mshr_hits                       675                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_0                      13                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_1                     266                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_2                      59                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_3                     337                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_miss_latency            382669                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_0           14688                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_1          175110                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_2           32334                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_3          160537                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_rate             0.011714                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_0           0.002386                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_1           0.047952                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_2           0.002005                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_3           0.019345                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_misses                    7037                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_0                   472                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_1                  3303                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_2                   370                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_3                  2892                       # number of demand (read+write) MSHR misses
cpu.icache.fast_writes                              0                       # number of fast writes performed
cpu.icache.mshr_cap_events                          0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_0                        0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_1                        0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_2                        0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_3                        0                       # number of times MSHR cap was activated
cpu.icache.no_allocate_misses                       0                       # Number of misses that were no-allocate
cpu.icache.overall_accesses                    600757                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_0                  197851                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_1                   68882                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_2                  184525                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_3                  149499                       # number of overall (read+write) accesses
cpu.icache.overall_avg_miss_latency         34.620462                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_0       23.047423                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_1       35.847576                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_2       56.515152                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_3       32.093527                       # average overall miss latency
cpu.icache.overall_avg_mshr_miss_latency    54.379565                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_0    31.118644                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_1    53.015441                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_2    87.389189                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_3    55.510719                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_2 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_3 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_hits                        593045                       # number of overall hits
cpu.icache.overall_hits_0                      197366                       # number of overall hits
cpu.icache.overall_hits_1                       65313                       # number of overall hits
cpu.icache.overall_hits_2                      184096                       # number of overall hits
cpu.icache.overall_hits_3                      146270                       # number of overall hits
cpu.icache.overall_miss_latency                266993                       # number of overall miss cycles
cpu.icache.overall_miss_latency_0               11178                       # number of overall miss cycles
cpu.icache.overall_miss_latency_1              127940                       # number of overall miss cycles
cpu.icache.overall_miss_latency_2               24245                       # number of overall miss cycles
cpu.icache.overall_miss_latency_3              103630                       # number of overall miss cycles
cpu.icache.overall_miss_rate                 0.012837                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_0               0.002451                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_1               0.051813                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_2               0.002325                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_3               0.021599                       # miss rate for overall accesses
cpu.icache.overall_misses                        7712                       # number of overall misses
cpu.icache.overall_misses_0                       485                       # number of overall misses
cpu.icache.overall_misses_1                      3569                       # number of overall misses
cpu.icache.overall_misses_2                       429                       # number of overall misses
cpu.icache.overall_misses_3                      3229                       # number of overall misses
cpu.icache.overall_mshr_hits                      675                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_0                     13                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_1                    266                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_2                     59                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_3                    337                       # number of overall MSHR hits
cpu.icache.overall_mshr_miss_latency           382669                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_0          14688                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_1         175110                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_2          32334                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_3         160537                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_rate            0.011714                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_0          0.002386                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_1          0.047952                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_2          0.002005                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_3          0.019345                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_misses                   7037                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_0                  472                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_1                 3303                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_2                  370                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_3                 2892                       # number of overall MSHR misses
cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_2            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_3            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_2            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_3            0                       # number of overall MSHR uncacheable misses
cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.icache.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
cpu.icache.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.icache.read_accesses                       600757                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_0                     197851                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_1                      68882                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_2                     184525                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_3                     149499                       # number of read accesses(hits+misses)
cpu.icache.read_avg_miss_latency            34.620462                       # average read miss latency
cpu.icache.read_avg_miss_latency_0          23.047423                       # average read miss latency
cpu.icache.read_avg_miss_latency_1          35.847576                       # average read miss latency
cpu.icache.read_avg_miss_latency_2          56.515152                       # average read miss latency
cpu.icache.read_avg_miss_latency_3          32.093527                       # average read miss latency
cpu.icache.read_avg_mshr_miss_latency       54.379565                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_0     31.118644                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_1     53.015441                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_2     87.389189                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_3     55.510719                       # average read mshr miss latency
cpu.icache.read_hits                           593045                       # number of read hits
cpu.icache.read_hits_0                         197366                       # number of read hits
cpu.icache.read_hits_1                          65313                       # number of read hits
cpu.icache.read_hits_2                         184096                       # number of read hits
cpu.icache.read_hits_3                         146270                       # number of read hits
cpu.icache.read_miss_latency                   266993                       # number of read miss cycles
cpu.icache.read_miss_latency_0                  11178                       # number of read miss cycles
cpu.icache.read_miss_latency_1                 127940                       # number of read miss cycles
cpu.icache.read_miss_latency_2                  24245                       # number of read miss cycles
cpu.icache.read_miss_latency_3                 103630                       # number of read miss cycles
cpu.icache.read_miss_rate                    0.012837                       # miss rate for read accesses
cpu.icache.read_miss_rate_0                  0.002451                       # miss rate for read accesses
cpu.icache.read_miss_rate_1                  0.051813                       # miss rate for read accesses
cpu.icache.read_miss_rate_2                  0.002325                       # miss rate for read accesses
cpu.icache.read_miss_rate_3                  0.021599                       # miss rate for read accesses
cpu.icache.read_misses                           7712                       # number of read misses
cpu.icache.read_misses_0                          485                       # number of read misses
cpu.icache.read_misses_1                         3569                       # number of read misses
cpu.icache.read_misses_2                          429                       # number of read misses
cpu.icache.read_misses_3                         3229                       # number of read misses
cpu.icache.read_mshr_hits                         675                       # number of read MSHR hits
cpu.icache.read_mshr_hits_0                        13                       # number of read MSHR hits
cpu.icache.read_mshr_hits_1                       266                       # number of read MSHR hits
cpu.icache.read_mshr_hits_2                        59                       # number of read MSHR hits
cpu.icache.read_mshr_hits_3                       337                       # number of read MSHR hits
cpu.icache.read_mshr_miss_latency              382669                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_0             14688                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_1            175110                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_2             32334                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_3            160537                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_rate               0.011714                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_0             0.002386                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_1             0.047952                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_2             0.002005                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_3             0.019345                       # mshr miss rate for read accesses
cpu.icache.read_mshr_misses                      7037                       # number of read MSHR misses
cpu.icache.read_mshr_misses_0                     472                       # number of read MSHR misses
cpu.icache.read_mshr_misses_1                    3303                       # number of read MSHR misses
cpu.icache.read_mshr_misses_2                     370                       # number of read MSHR misses
cpu.icache.read_mshr_misses_3                    2892                       # number of read MSHR misses
cpu.icache.replacements                          5534                       # number of replacements
cpu.icache.replacements_0                         381                       # number of replacements
cpu.icache.replacements_1                        2595                       # number of replacements
cpu.icache.replacements_2                         295                       # number of replacements
cpu.icache.replacements_3                        2263                       # number of replacements
cpu.icache.sampled_refs                          6518                       # Sample count of references to valid blocks.
cpu.icache.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_0                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_1                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_2                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_3                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.tagsinuse                       824.222779                       # Cycle average of tags in use
cpu.icache.total_refs                          593045                       # Total number of references to valid blocks.
cpu.icache.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
cpu.icache.writebacks                               0                       # number of writebacks
cpu.icache.writebacks_0                             0                       # number of writebacks
cpu.icache.writebacks_1                             0                       # number of writebacks
cpu.icache.writebacks_2                             0                       # number of writebacks
cpu.icache.writebacks_3                             0                       # number of writebacks
cpu.iq:RQ:rdy_inst                            3379094                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_0                          1236017                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_1                           379776                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_2                          1065142                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_3                           698159                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_dist_0_mean               3.690683                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_0_stdev              3.378529                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_0_TOT        334902                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_1_mean               1.133991                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_1_stdev              2.546063                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_1_TOT        334902                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_2_mean               3.180459                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_2_stdev              2.963840                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_2_TOT        334902                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_3_mean               2.084667                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_3_stdev              3.143584                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_3_TOT        334902                       # standard deviation of ready rate
cpu.iq:RQ:rdy_rate                          10.089799                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_0                         3.690683                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_1                         1.133991                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_2                         3.180459                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_3                         2.084667                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_x_count                         1484160                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_0                        548637                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_1                        138077                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_2                        509031                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_3                        288415                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_max                                31                       # largest number of insts that become ready
cpu.iq:RQ:rdy_x_rate                         4.431625                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_0                       1.638202                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_1                       0.412291                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_2                       1.519940                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_3                       0.861192                       # number of insts that become ready per cycle
cpu.iq:avg_residency                        10.111256                       # Average IQ residency
cpu.iq:avg_residency_0                       7.894856                       # Average IQ residency
cpu.iq:avg_residency_1                      28.039702                       # Average IQ residency
cpu.iq:avg_residency_2                       8.576136                       # Average IQ residency
cpu.iq:avg_residency_3                       8.765291                       # Average IQ residency
cpu.iq:cum_num_insts                         14659440                       # Total occupancy
cpu.iq:cum_num_insts_0                        4256575                       # Total occupancy
cpu.iq:cum_num_insts_1                        3660499                       # Total occupancy
cpu.iq:cum_num_insts_2                        4330640                       # Total occupancy
cpu.iq:cum_num_insts_3                        2411726                       # Total occupancy
cpu.iq:current_count                               64                       # Occupancy this cycle
cpu.iq:empty_count                               2632                       # Number of empty cycles
cpu.iq:empty_rate                            0.785902                       # Fraction of cycles empty
cpu.iq:full_count                               96814                       # Number of full cycles
cpu.iq:full_rate                            28.908158                       # Fraction of cycles full
cpu.iq:occ_dist_0.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_0.samples                      334902                      
cpu.iq:occ_dist_0.min_value                         0                      
                               0        59602              1779.68%
                               2        15362              2238.39%
                               4        14993              2686.07%
                               6        17172              3198.82%
                               8        23909              3912.73%
                              10        22520              4585.16%
                              12        25258              5339.35%
                              14        30996              6264.88%
                              16        29100              7133.79%
                              18        24914              7877.71%
                              20        18919              8442.62%
                              22        14174              8865.85%
                              24         7481              9089.23%
                              26         4866              9234.52%
                              28         4893              9380.62%
                              30         7055              9591.28%
                              32         5424              9753.24%
                              34         2875              9839.09%
                              36          838              9864.11%
                              38          633              9883.01%
                              40          582              9900.39%
                              42          437              9913.44%
                              44          741              9935.56%
                              46          444              9948.82%
                              48          414              9961.18%
                              50          404              9973.25%
                              52          360              9984.00%
                              54          250              9991.46%
                              56           58              9993.19%
                              58           65              9995.13%
                              60          100              9998.12%
                              62           48              9999.55%
                              64           15             10000.00%
cpu.iq:occ_dist_0.max_value                        64                      
cpu.iq:occ_dist_0.end_dist

cpu.iq:occ_dist_1.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_1.samples                      334902                      
cpu.iq:occ_dist_1.min_value                         0                      
                               0       131404              3923.66%
                               2        16889              4427.95%
                               4        10503              4741.57%
                               6        10672              5060.23%
                               8        11496              5403.49%
                              10         8954              5670.85%
                              12        11008              5999.55%
                              14        19436              6579.90%
                              16        22593              7254.51%
                              18        19015              7822.29%
                              20        11702              8171.70%
                              22        14625              8608.40%
                              24        13040              8997.77%
                              26         3156              9092.00%
                              28         3297              9190.45%
                              30         2874              9276.27%
                              32         6093              9458.20%
                              34         2521              9533.48%
                              36         1808              9587.46%
                              38         1559              9634.01%
                              40         1121              9667.48%
                              42         2105              9730.34%
                              44         1573              9777.31%
                              46         1858              9832.79%
                              48          777              9855.99%
                              50          810              9880.17%
                              52          748              9902.51%
                              54         1230              9939.24%
                              56          733              9961.12%
                              58          358              9971.81%
                              60           59              9973.57%
                              62           77              9975.87%
                              64          808             10000.00%
cpu.iq:occ_dist_1.max_value                        64                      
cpu.iq:occ_dist_1.end_dist

cpu.iq:occ_dist_2.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_2.samples                      334902                      
cpu.iq:occ_dist_2.min_value                         0                      
                               0        48957              1461.83%
                               2        15327              1919.49%
                               4        15314              2376.75%
                               6        20114              2977.35%
                               8        25190              3729.51%
                              10        22191              4392.12%
                              12        26435              5181.46%
                              14        32430              6149.80%
                              16        30329              7055.41%
                              18        27158              7866.33%
                              20        20437              8476.57%
                              22        14246              8901.95%
                              24         7679              9131.24%
                              26         5087              9283.13%
                              28         5630              9451.24%
                              30         6800              9654.29%
                              32         5713              9824.87%
                              34         3140              9918.63%
                              36          658              9938.28%
                              38          442              9951.48%
                              40          303              9960.53%
                              42          293              9969.27%
                              44          277              9977.55%
                              46          148              9981.96%
                              48          152              9986.50%
                              50           86              9989.07%
                              52           61              9990.89%
                              54           52              9992.45%
                              56           49              9993.91%
                              58          115              9997.34%
                              60           26              9998.12%
                              62           29              9998.98%
                              64           34             10000.00%
cpu.iq:occ_dist_2.max_value                        64                      
cpu.iq:occ_dist_2.end_dist

cpu.iq:occ_dist_3.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_3.samples                      334902                      
cpu.iq:occ_dist_3.min_value                         0                      
                               0       153196              4574.35%
                               2        16230              5058.97%
                               4        14193              5482.77%
                               6        13634              5889.87%
                               8        17094              6400.29%
                              10        13698              6809.31%
                              12        17418              7329.40%
                              14        24712              8067.29%
                              16        21309              8703.56%
                              18        15335              9161.46%
                              20         9821              9454.71%
                              22         7030              9664.62%
                              24         3727              9775.90%
                              26         1473              9819.89%
                              28         1215              9856.17%
                              30         1068              9888.06%
                              32         1038              9919.05%
                              34          374              9930.22%
                              36          248              9937.62%
                              38          251              9945.12%
                              40          456              9958.73%
                              42          181              9964.14%
                              44          164              9969.04%
                              46           65              9970.98%
                              48          187              9976.56%
                              50           97              9979.46%
                              52           89              9982.11%
                              54          136              9986.18%
                              56           19              9986.74%
                              58          119              9990.30%
                              60           20              9990.89%
                              62           24              9991.61%
                              64          281             10000.00%
cpu.iq:occ_dist_3.max_value                        64                      
cpu.iq:occ_dist_3.end_dist

cpu.iq:occ_rate                             43.772327                       # Average occupancy
cpu.iq:occ_rate_0                           12.709912                       # Average occupancy
cpu.iq:occ_rate_1                           10.930060                       # Average occupancy
cpu.iq:occ_rate_2                           12.931066                       # Average occupancy
cpu.iq:occ_rate_3                            7.201289                       # Average occupancy
cpu.iq:peak_occupancy                             256                       # Peak IQ occupancy
cpu.iq:peak_occupancy_0                            64                       # Peak IQ occupancy
cpu.iq:peak_occupancy_1                            64                       # Peak IQ occupancy
cpu.iq:peak_occupancy_2                            64                       # Peak IQ occupancy
cpu.iq:peak_occupancy_3                            64                       # Peak IQ occupancy
cpu.l2.avg_blocked_cycles_no_mshrs       <err: div-0>                       # average number of cycles each access was blocked
cpu.l2.avg_blocked_cycles_no_targets     <err: div-0>                       # average number of cycles each access was blocked
cpu.l2.avg_refs                          <err: div-0>                       # Average number of references to valid blocks.
cpu.l2.blocked_no_mshrs                             0                       # number of cycles access was blocked
cpu.l2.blocked_no_targets                           0                       # number of cycles access was blocked
cpu.l2.blocked_cycles_no_mshrs                      0                       # number of cycles access was blocked
cpu.l2.blocked_cycles_no_targets                    0                       # number of cycles access was blocked
cpu.l2.cache_copies                                 0                       # number of cache copies performed
cpu.l2.demand_accesses                          10512                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_0                          744                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_1                         5019                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_2                          813                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_3                         3936                       # number of demand (read+write) accesses
cpu.l2.demand_avg_miss_latency             128.192673                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_0           130.943463                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_1           128.191584                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_2           128.073770                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_3           127.870938                       # average overall miss latency
cpu.l2.demand_avg_mshr_miss_latency        114.132538                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_0      116.095406                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_1      114.077150                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_2      113.960656                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_3      113.994966                       # average overall mshr miss latency
cpu.l2.demand_hits                               4725                       # number of demand (read+write) hits
cpu.l2.demand_hits_0                              461                       # number of demand (read+write) hits
cpu.l2.demand_hits_1                             2310                       # number of demand (read+write) hits
cpu.l2.demand_hits_2                              203                       # number of demand (read+write) hits
cpu.l2.demand_hits_3                             1751                       # number of demand (read+write) hits
cpu.l2.demand_miss_latency                     741851                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_0                    37057                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_1                   347271                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_2                    78125                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_3                   279398                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_rate                      0.550514                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_0                    0.380376                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_1                    0.539749                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_2                    0.750308                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_3                    0.555132                       # miss rate for demand accesses
cpu.l2.demand_misses                             5787                       # number of demand (read+write) misses
cpu.l2.demand_misses_0                            283                       # number of demand (read+write) misses
cpu.l2.demand_misses_1                           2709                       # number of demand (read+write) misses
cpu.l2.demand_misses_2                            610                       # number of demand (read+write) misses
cpu.l2.demand_misses_3                           2185                       # number of demand (read+write) misses
cpu.l2.demand_mshr_hits                             0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_0                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_1                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_2                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_3                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_miss_latency                660485                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_0               32855                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_1              309035                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_2               69516                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_3              249079                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_rate                 0.550514                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_0               0.380376                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_1               0.539749                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_2               0.750308                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_3               0.555132                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_misses                        5787                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_0                       283                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_1                      2709                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_2                       610                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_3                      2185                       # number of demand (read+write) MSHR misses
cpu.l2.falru_accesses                           11594                       # The number of accesses to the FA LRU cache.
cpu.l2.falru_hits_128K                           4177                       # Hits in a 128K cache
cpu.l2.falru_hits_256K                           5406                       # Hits in a 256K cache
cpu.l2.falru_hits_512K                           5596                       # Hits in a 512K cache
cpu.l2.falru_hits_1M                             5596                       # Hits in a 1M cache
cpu.l2.falru_hits_2M                             5596                       # Hits in a 2M cache
cpu.l2.falru_misses_128K                         7417                       # Misses in a 128K cache
cpu.l2.falru_misses_256K                         6188                       # Misses in a 256K cache
cpu.l2.falru_misses_512K                         5998                       # Misses in a 512K cache
cpu.l2.falru_misses_1M                           5998                       # Misses in a 1M cache
cpu.l2.falru_misses_2M                           5998                       # Misses in a 2M cache
cpu.l2.fast_writes                                  0                       # number of fast writes performed
cpu.l2.mshr_cap_events                              0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_0                            0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_1                            0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_2                            0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_3                            0                       # number of times MSHR cap was activated
cpu.l2.no_allocate_misses                           0                       # Number of misses that were no-allocate
cpu.l2.overall_accesses                         11594                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_0                         750                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_1                        5144                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_2                        1027                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_3                        4673                       # number of overall (read+write) accesses
cpu.l2.overall_avg_miss_latency            123.683061                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_0          130.943463                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_1          127.767108                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_2          128.073770                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_3          117.049853                       # average overall miss latency
cpu.l2.overall_avg_mshr_miss_latency       114.132538                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_0     116.095406                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_1     114.077150                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_2     113.960656                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_3     113.994966                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_2 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_3 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_hits                              5596                       # number of overall hits
cpu.l2.overall_hits_0                             467                       # number of overall hits
cpu.l2.overall_hits_1                            2426                       # number of overall hits
cpu.l2.overall_hits_2                             417                       # number of overall hits
cpu.l2.overall_hits_3                            2286                       # number of overall hits
cpu.l2.overall_miss_latency                    741851                       # number of overall miss cycles
cpu.l2.overall_miss_latency_0                   37057                       # number of overall miss cycles
cpu.l2.overall_miss_latency_1                  347271                       # number of overall miss cycles
cpu.l2.overall_miss_latency_2                   78125                       # number of overall miss cycles
cpu.l2.overall_miss_latency_3                  279398                       # number of overall miss cycles
cpu.l2.overall_miss_rate                     0.517337                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_0                   0.377333                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_1                   0.528383                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_2                   0.593963                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_3                   0.510807                       # miss rate for overall accesses
cpu.l2.overall_misses                            5998                       # number of overall misses
cpu.l2.overall_misses_0                           283                       # number of overall misses
cpu.l2.overall_misses_1                          2718                       # number of overall misses
cpu.l2.overall_misses_2                           610                       # number of overall misses
cpu.l2.overall_misses_3                          2387                       # number of overall misses
cpu.l2.overall_mshr_hits                            0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_0                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_1                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_2                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_3                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_miss_latency               660485                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_0              32855                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_1             309035                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_2              69516                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_3             249079                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_rate                0.499137                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_0              0.377333                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_1              0.526633                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_2              0.593963                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_3              0.467580                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_misses                       5787                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_0                      283                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_1                     2709                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_2                      610                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_3                     2185                       # number of overall MSHR misses
cpu.l2.overall_mshr_uncacheable_latency             0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_2            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_3            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_misses              0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_2            0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_3            0                       # number of overall MSHR uncacheable misses
cpu.l2.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.l2.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.l2.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.l2.prefetcher.num_hwpf_evicted                  0                       # number of hwpf removed due to no buffer left
cpu.l2.prefetcher.num_hwpf_identified               0                       # number of hwpf identified
cpu.l2.prefetcher.num_hwpf_issued                   0                       # number of hwpf issued
cpu.l2.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.l2.prefetcher.num_hwpf_span_page                0                       # number of hwpf spanning a virtual page
cpu.l2.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.l2.read_accesses                            10512                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_0                            744                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_1                           5019                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_2                            813                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_3                           3936                       # number of read accesses(hits+misses)
cpu.l2.read_avg_miss_latency               128.192673                       # average read miss latency
cpu.l2.read_avg_miss_latency_0             130.943463                       # average read miss latency
cpu.l2.read_avg_miss_latency_1             128.191584                       # average read miss latency
cpu.l2.read_avg_miss_latency_2             128.073770                       # average read miss latency
cpu.l2.read_avg_miss_latency_3             127.870938                       # average read miss latency
cpu.l2.read_avg_mshr_miss_latency          114.132538                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_0        116.095406                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_1        114.077150                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_2        113.960656                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_3        113.994966                       # average read mshr miss latency
cpu.l2.read_hits                                 4725                       # number of read hits
cpu.l2.read_hits_0                                461                       # number of read hits
cpu.l2.read_hits_1                               2310                       # number of read hits
cpu.l2.read_hits_2                                203                       # number of read hits
cpu.l2.read_hits_3                               1751                       # number of read hits
cpu.l2.read_miss_latency                       741851                       # number of read miss cycles
cpu.l2.read_miss_latency_0                      37057                       # number of read miss cycles
cpu.l2.read_miss_latency_1                     347271                       # number of read miss cycles
cpu.l2.read_miss_latency_2                      78125                       # number of read miss cycles
cpu.l2.read_miss_latency_3                     279398                       # number of read miss cycles
cpu.l2.read_miss_rate                        0.550514                       # miss rate for read accesses
cpu.l2.read_miss_rate_0                      0.380376                       # miss rate for read accesses
cpu.l2.read_miss_rate_1                      0.539749                       # miss rate for read accesses
cpu.l2.read_miss_rate_2                      0.750308                       # miss rate for read accesses
cpu.l2.read_miss_rate_3                      0.555132                       # miss rate for read accesses
cpu.l2.read_misses                               5787                       # number of read misses
cpu.l2.read_misses_0                              283                       # number of read misses
cpu.l2.read_misses_1                             2709                       # number of read misses
cpu.l2.read_misses_2                              610                       # number of read misses
cpu.l2.read_misses_3                             2185                       # number of read misses
cpu.l2.read_mshr_miss_latency                  660485                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_0                 32855                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_1                309035                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_2                 69516                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_3                249079                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_rate                   0.550514                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_0                 0.380376                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_1                 0.539749                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_2                 0.750308                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_3                 0.555132                       # mshr miss rate for read accesses
cpu.l2.read_mshr_misses                          5787                       # number of read MSHR misses
cpu.l2.read_mshr_misses_0                         283                       # number of read MSHR misses
cpu.l2.read_mshr_misses_1                        2709                       # number of read MSHR misses
cpu.l2.read_mshr_misses_2                         610                       # number of read MSHR misses
cpu.l2.read_mshr_misses_3                        2185                       # number of read MSHR misses
cpu.l2.replacements                                 0                       # number of replacements
cpu.l2.replacements_0                               0                       # number of replacements
cpu.l2.replacements_1                               0                       # number of replacements
cpu.l2.replacements_2                               0                       # number of replacements
cpu.l2.replacements_3                               0                       # number of replacements
cpu.l2.sampled_refs                                 0                       # Sample count of references to valid blocks.
cpu.l2.soft_prefetch_mshr_full                      0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_0                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_1                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_2                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_3                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.tagsinuse                          3550.655168                       # Cycle average of tags in use
cpu.l2.total_refs                                   0                       # Total number of references to valid blocks.
cpu.l2.warmup_cycle                                 0                       # Cycle when the warmup percentage was hit.
cpu.l2.writeback_accesses                        1082                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_0                         6                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_1                       125                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_2                       214                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_3                       737                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_hits                             871                       # number of writeback hits
cpu.l2.writeback_hits_0                             6                       # number of writeback hits
cpu.l2.writeback_hits_1                           116                       # number of writeback hits
cpu.l2.writeback_hits_2                           214                       # number of writeback hits
cpu.l2.writeback_hits_3                           535                       # number of writeback hits
cpu.l2.writeback_miss_rate                   0.195009                       # miss rate for writeback accesses
cpu.l2.writeback_miss_rate_1                 0.072000                       # miss rate for writeback accesses
cpu.l2.writeback_miss_rate_3                 0.274084                       # miss rate for writeback accesses
cpu.l2.writeback_misses                           211                       # number of writeback misses
cpu.l2.writeback_misses_1                           9                       # number of writeback misses
cpu.l2.writeback_misses_3                         202                       # number of writeback misses
cpu.l2.writeback_mshr_miss_rate              0.195009                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_miss_rate_1            0.072000                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_miss_rate_3            0.274084                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_misses                      211                       # number of writeback MSHR misses
cpu.l2.writeback_mshr_misses_1                      9                       # number of writeback MSHR misses
cpu.l2.writeback_mshr_misses_3                    202                       # number of writeback MSHR misses
cpu.l2.writebacks                                   0                       # number of writebacks
cpu.l2.writebacks_0                                 0                       # number of writebacks
cpu.l2.writebacks_1                                 0                       # number of writebacks
cpu.l2.writebacks_2                                 0                       # number of writebacks
cpu.l2.writebacks_3                                 0                       # number of writebacks
cpu.numCycles                                  334902                       # number of cpu cycles simulated
cpu.toL2Bus.addr_idle_cycles                   323299                       # number of cycles bus was idle
cpu.toL2Bus.addr_idle_fraction               0.965357                       # fraction of time addr bus was idle
cpu.toL2Bus.addr_queued                      3.548301                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_0                    3.877333                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_1                    3.675933                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_2                    3.698150                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_3                    3.322063                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_cycles                  41139                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_0                 2908                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_1                18909                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_2                 3798                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_3                15524                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_requests                       11594                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_0                       750                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_1                      5144                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_2                      1027                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_3                      4673                       # number of transmissions on bus
cpu.toL2Bus.bus_blocked                             0                       # number of times bus was blocked
cpu.toL2Bus.bus_blocked_cycles                      0                       # number of cycles bus was blocked
cpu.toL2Bus.bus_blocked_fraction                    0                       # fraction of time bus was blocked
cpu.toL2Bus.data_idle_cycles                   323284                       # number of cycles bus was idle
cpu.toL2Bus.data_idle_fraction               0.965312                       # fraction of time data bus was idle
cpu.toL2Bus.data_queued                      1.024548                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_0                    1.009421                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_1                    1.032277                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_2                    1.014760                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_3                    1.019568                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_cycles                  10768                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_0                  750                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_1                 5181                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_2                  825                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_3                 4012                       # total number of queued cycles for all requests
cpu.toL2Bus.data_requests                       10510                       # number of transmissions on bus
cpu.toL2Bus.data_requests_0                       743                       # number of transmissions on bus
cpu.toL2Bus.data_requests_1                      5019                       # number of transmissions on bus
cpu.toL2Bus.data_requests_2                       813                       # number of transmissions on bus
cpu.toL2Bus.data_requests_3                      3935                       # number of transmissions on bus
cpu.toL2Bus.null_grants                           304                       # number of null grants (wasted cycles)
cpu.workload0.MainMem.page_count                    0                       # total number of pages allocated
cpu.workload0.MainMem.page_mem                      0                       # total size of memory pages allocated
cpu.workload0.MainMem.ptab_accesses           1172100                       # total page table accessess
cpu.workload0.MainMem.ptab_miss_rate           0.0107                       # first level page table miss rate
cpu.workload0.MainMem.ptab_misses               12518                       # total first level page table misses
cpu.workload0.PROG:num_syscalls                   514                       # Number of system calls
cpu.workload1.MainMem.page_count                    1                       # total number of pages allocated
cpu.workload1.MainMem.page_mem                      8                       # total size of memory pages allocated
cpu.workload1.MainMem.ptab_accesses            377878                       # total page table accessess
cpu.workload1.MainMem.ptab_miss_rate           0.0071                       # first level page table miss rate
cpu.workload1.MainMem.ptab_misses                2678                       # total first level page table misses
cpu.workload1.PROG:num_syscalls                     4                       # Number of system calls
cpu.workload2.MainMem.page_count                    7                       # total number of pages allocated
cpu.workload2.MainMem.page_mem                     56                       # total size of memory pages allocated
cpu.workload2.MainMem.ptab_accesses            943431                       # total page table accessess
cpu.workload2.MainMem.ptab_miss_rate           0.0943                       # first level page table miss rate
cpu.workload2.MainMem.ptab_misses               88928                       # total first level page table misses
cpu.workload2.PROG:num_syscalls                    11                       # Number of system calls
cpu.workload3.MainMem.page_count                   21                       # total number of pages allocated
cpu.workload3.MainMem.page_mem                    168                       # total size of memory pages allocated
cpu.workload3.MainMem.ptab_accesses            748829                       # total page table accessess
cpu.workload3.MainMem.ptab_miss_rate           0.0035                       # first level page table miss rate
cpu.workload3.MainMem.ptab_misses                2617                       # total first level page table misses
cpu.workload3.PROG:num_syscalls                     8                       # Number of system calls
cpuinst_class_dist.start_dist
                   All ops ready            0      0.00%            # Operand status at dispatch
                One op not ready            0      0.00%            # Operand status at dispatch
           None rdy, mult chains            0      0.00%            # Operand status at dispatch
           None rdy, one chained            0      0.00%            # Operand status at dispatch
        None rdy, all self-timed            0      0.00%            # Operand status at dispatch
cpuinst_class_dist.end_dist
host_inst_rate                                  71220                       # Simulator instruction rate (inst/s)
host_mem_usage                                  21896                       # Number of bytes of host memory used
host_seconds                                    18.23                       # Real time elapsed on the host
host_tick_rate                                  18370                       # Simulator tick rate (ticks/s)
ram.accesses                                     5998                       # total number of accesses
ram.accesses_0                                    283                       # total number of accesses
ram.accesses_1                                   2718                       # total number of accesses
ram.accesses_2                                    610                       # total number of accesses
ram.accesses_3                                   2387                       # total number of accesses
ram.bytes_requested                                 0                       # total number of bytes requested
ram.bytes_requested_0                               0                       # total number of bytes requested
ram.bytes_requested_1                               0                       # total number of bytes requested
ram.bytes_requested_2                               0                       # total number of bytes requested
ram.bytes_requested_3                               0                       # total number of bytes requested
ram.bytes_sent                                      0                       # total number of bytes sent
ram.bytes_sent_0                                    0                       # total number of bytes sent
ram.bytes_sent_1                                    0                       # total number of bytes sent
ram.bytes_sent_2                                    0                       # total number of bytes sent
ram.bytes_sent_3                                    0                       # total number of bytes sent
ram.compressed_responses                            0                       # total number of accesses that are compressed
ram.compressed_responses_0                          0                       # total number of accesses that are compressed
ram.compressed_responses_1                          0                       # total number of accesses that are compressed
ram.compressed_responses_2                          0                       # total number of accesses that are compressed
ram.compressed_responses_3                          0                       # total number of accesses that are compressed
sim_freq                                    200000000                       # Frequency of simulated ticks
sim_insts                                     1298396                       # Number of instructions simulated
sim_seconds                                  0.001675                       # Number of seconds simulated
sim_ticks                                      334901                       # Number of ticks simulated
toMemBus.addr_idle_cycles                      328837                       # number of cycles bus was idle
toMemBus.addr_idle_fraction                  0.981893                       # fraction of time addr bus was idle
toMemBus.addr_queued                        11.025175                       # average queueing delay seen by bus request
toMemBus.addr_queued_0                       9.819788                       # average queueing delay seen by bus request
toMemBus.addr_queued_1                      11.021707                       # average queueing delay seen by bus request
toMemBus.addr_queued_2                      10.778689                       # average queueing delay seen by bus request
toMemBus.addr_queued_3                      11.235023                       # average queueing delay seen by bus request
toMemBus.addr_queued_cycles                     66129                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_0                    2779                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_1                   29957                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_2                    6575                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_3                   26818                       # total number of queued cycles for all requests
toMemBus.addr_requests                           5998                       # number of transmissions on bus
toMemBus.addr_requests_0                          283                       # number of transmissions on bus
toMemBus.addr_requests_1                         2718                       # number of transmissions on bus
toMemBus.addr_requests_2                          610                       # number of transmissions on bus
toMemBus.addr_requests_3                         2387                       # number of transmissions on bus
toMemBus.bus_blocked                                0                       # number of times bus was blocked
toMemBus.bus_blocked_cycles                         0                       # number of cycles bus was blocked
toMemBus.bus_blocked_fraction                       0                       # fraction of time bus was blocked
toMemBus.data_idle_cycles                      310851                       # number of cycles bus was idle
toMemBus.data_idle_fraction                  0.928188                       # fraction of time data bus was idle
toMemBus.data_queued                         2.155029                       # average queueing delay seen by bus request
toMemBus.data_queued_0                       5.275618                       # average queueing delay seen by bus request
toMemBus.data_queued_1                       2.060170                       # average queueing delay seen by bus request
toMemBus.data_queued_2                       2.181967                       # average queueing delay seen by bus request
toMemBus.data_queued_3                       1.860806                       # average queueing delay seen by bus request
toMemBus.data_queued_cycles                     12469                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_0                    1493                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_1                    5581                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_2                    1331                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_3                    4064                       # total number of queued cycles for all requests
toMemBus.data_requests                           5786                       # number of transmissions on bus
toMemBus.data_requests_0                          283                       # number of transmissions on bus
toMemBus.data_requests_1                         2709                       # number of transmissions on bus
toMemBus.data_requests_2                          610                       # number of transmissions on bus
toMemBus.data_requests_3                         2184                       # number of transmissions on bus
toMemBus.null_grants                                0                       # number of null grants (wasted cycles)

---------- End Simulation Statistics   ----------
