
---------- Begin Simulation Statistics ----------
cpu.COM:IPB                                  6.214547                       # Committed instructions per branch
cpu.COM:IPB_0                                6.199268                       # Committed instructions per branch
cpu.COM:IPB_1                                6.198540                       # Committed instructions per branch
cpu.COM:IPB_2                                6.252234                       # Committed instructions per branch
cpu.COM:IPB_3                                6.204270                       # Committed instructions per branch
cpu.COM:IPC                                  2.083710                       # Committed instructions per cycle
cpu.COM:IPC_0                                0.504032                       # Committed instructions per cycle
cpu.COM:IPC_1                                0.503763                       # Committed instructions per cycle
cpu.COM:IPC_2                                0.562903                       # Committed instructions per cycle
cpu.COM:IPC_3                                0.513012                       # Committed instructions per cycle
cpu.COM:branches                               595655                       # Number of branches committed
cpu.COM:branches_0                             144439                       # Number of branches committed
cpu.COM:branches_1                             144379                       # Number of branches committed
cpu.COM:branches_2                             159943                       # Number of branches committed
cpu.COM:branches_3                             146894                       # Number of branches committed
cpu.COM:bw_lim_avg                            22.8013                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_0                           5.0727                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_1                           5.0811                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_2                           7.1676                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_avg_3                           5.4799                       # Avg number not committed in cycles BW limited
cpu.COM:bw_lim_events                          165901                       # number cycles where commit BW limit reached
cpu.COM:bw_lim_rate                            2.1293                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_0                          0.4737                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_1                          0.4745                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_2                          0.6694                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_rate_3                          0.5117                       # Average number not committed due to BW (over all cycles)
cpu.COM:bw_lim_stdev_0_mean                    5.0727                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_0_stdev                  12.2792                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_0_TOT      165901.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_1_mean                    5.0811                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_1_stdev                  12.3074                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_1_TOT      165901.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_2_mean                    7.1676                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_2_stdev                  15.5043                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_2_TOT      165901.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_3_mean                    5.4799                       # standard deviation of bw_lim_avg value
cpu.COM:bw_lim_stdev_3_stdev                  13.3864                       # standard deviation of bw_lim_avg value
**Ignore: cpu.COM:bw_lim_stdev_3_TOT      165901.0000                       # standard deviation of bw_lim_avg value
cpu.COM:bw_limited                            3782760                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_0                           841568                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_1                           842960                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_2                          1189118                       # number of insts not committed due to BW limits
cpu.COM:bw_limited_3                           909114                       # number of insts not committed due to BW limits
cpu.COM:committed_per_cycle.start_dist                         # Number of insts commited each cycle
cpu.COM:committed_per_cycle.samples           1005154                      
cpu.COM:committed_per_cycle.min_value               0                      
                               0         4746     47.22%           
                               1       273820   2724.16%           
                               2       176446   1755.41%           
                               3       125476   1248.33%           
                               4        93388    929.09%           
                               5        61204    608.90%           
                               6        49082    488.30%           
                               7        35082    349.02%           
                               8       185910   1849.57%           
cpu.COM:committed_per_cycle.max_value               8                      
cpu.COM:committed_per_cycle.end_dist

cpu.COM:count                                 3701726                       # Number of instructions committed
cpu.COM:count_0                                895416                       # Number of instructions committed
cpu.COM:count_1                                894939                       # Number of instructions committed
cpu.COM:count_2                               1000001                       # Number of instructions committed
cpu.COM:count_3                                911370                       # Number of instructions committed
cpu.COM:loads                                  878865                       # Number of loads committed
cpu.COM:loads_0                                212159                       # Number of loads committed
cpu.COM:loads_1                                212040                       # Number of loads committed
cpu.COM:loads_2                                238693                       # Number of loads committed
cpu.COM:loads_3                                215973                       # Number of loads committed
cpu.COM:membars                                     0                       # Number of memory barriers committed
cpu.COM:membars_0                                   0                       # Number of memory barriers committed
cpu.COM:membars_1                                   0                       # Number of memory barriers committed
cpu.COM:membars_2                                   0                       # Number of memory barriers committed
cpu.COM:membars_3                                   0                       # Number of memory barriers committed
cpu.COM:refs                                  1328846                       # Number of memory references committed
cpu.COM:refs_0                                 321250                       # Number of memory references committed
cpu.COM:refs_1                                 321089                       # Number of memory references committed
cpu.COM:refs_2                                 359521                       # Number of memory references committed
cpu.COM:refs_3                                 326986                       # Number of memory references committed
cpu.COM:stores                                 449981                       # Number of stores committed
cpu.COM:stores_0                               109091                       # Number of stores committed
cpu.COM:stores_1                               109049                       # Number of stores committed
cpu.COM:stores_2                               120828                       # Number of stores committed
cpu.COM:stores_3                               111013                       # Number of stores committed
cpu.COM:swp_count                                8332                       # Number of s/w prefetches committed
cpu.COM:swp_count_0                              2004                       # Number of s/w prefetches committed
cpu.COM:swp_count_1                              2004                       # Number of s/w prefetches committed
cpu.COM:swp_count_2                              2263                       # Number of s/w prefetches committed
cpu.COM:swp_count_3                              2061                       # Number of s/w prefetches committed
cpu.DDQ:count                               160616057                       # cum count of instructions
cpu.DDQ:count_0                              37448236                       # cum count of instructions
cpu.DDQ:count_1                              37778563                       # cum count of instructions
cpu.DDQ:count_2                              45654426                       # cum count of instructions
cpu.DDQ:count_3                              39734832                       # cum count of instructions
cpu.DDQ:rate                                       90                       # average number of instructions
cpu.DDQ:rate_0                                     21                       # average number of instructions
cpu.DDQ:rate_1                                     21                       # average number of instructions
cpu.DDQ:rate_2                                     26                       # average number of instructions
cpu.DDQ:rate_3                                     22                       # average number of instructions
cpu.DIS:chain_creation.start_dist
     Inst has no outstanding IDEPS            0      0.00%            # Reason that chain head was created
      IDEP chain reached max depth            0      0.00%            # Reason that chain head was created
                    Inst is a load            0      0.00%            # Reason that chain head was created
  Chain has multiple chained IDEPS            0      0.00%            # Reason that chain head was created
cpu.DIS:chain_creation.end_dist
cpu.DIS:chain_head_frac                             0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_0                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_1                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_2                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_head_frac_3                           0                       # fraction of insts that are chain heads
cpu.DIS:chain_heads                                 0                       # number insts that are chain heads
cpu.DIS:chain_heads_0                               0                       # number insts that are chain heads
cpu.DIS:chain_heads_1                               0                       # number insts that are chain heads
cpu.DIS:chain_heads_2                               0                       # number insts that are chain heads
cpu.DIS:chain_heads_3                               0                       # number insts that are chain heads
cpu.DIS:chains_insuf                                0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_0                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_1                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_2                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_3                              0                       # number of times thread had insuf chains
cpu.DIS:chains_insuf_rate                           0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_0                         0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_1                         0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_2                         0                       # rate that thread had insuf chains
cpu.DIS:chains_insuf_rate_3                         0                       # rate that thread had insuf chains
cpu.DIS:count                                 4535632                       # cumulative count of dispatched insts
cpu.DIS:count_0                               1047260                       # cumulative count of dispatched insts
cpu.DIS:count_1                               1053895                       # cumulative count of dispatched insts
cpu.DIS:count_2                               1316461                       # cumulative count of dispatched insts
cpu.DIS:count_3                               1118016                       # cumulative count of dispatched insts
cpu.DIS:insufficient_chains                         0                       # Number of instances where dispatch stopped
cpu.DIS:mod_n_stall_avg_free                 no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_0               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_1               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_2               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_avg_free_3               no value                       # avg free slots per cycle
cpu.DIS:mod_n_stall_frac                            0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_0                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_1                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_2                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_frac_3                          0                       # avg stalls per cycle
cpu.DIS:mod_n_stall_free                            0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_0                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_1                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_2                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stall_free_3                          0                       # free slots when dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls                                0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_0                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_1                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_2                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:mod_n_stalls_3                              0                       # cycles where dispatch stalled due to mod-n
cpu.DIS:one_rdy_insts                               0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_0                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_1                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_2                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_insts_3                             0                       # number of 2-op insts w/ one rdy op
cpu.DIS:one_rdy_ratio                        no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_0                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_1                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_2                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:one_rdy_ratio_3                      no value                       # fraction of 2-op insts w/ one ready op
cpu.DIS:op_count                              6159963                       # number of operations dispatched
cpu.DIS:op_count_0                            1421754                       # number of operations dispatched
cpu.DIS:op_count_1                            1431239                       # number of operations dispatched
cpu.DIS:op_count_2                            1787980                       # number of operations dispatched
cpu.DIS:op_count_3                            1518990                       # number of operations dispatched
cpu.DIS:op_rate                              3.467458                       # dispatched operations per cycle
cpu.DIS:op_rate_0                            0.800309                       # dispatched operations per cycle
cpu.DIS:op_rate_1                            0.805648                       # dispatched operations per cycle
cpu.DIS:op_rate_2                            1.006458                       # dispatched operations per cycle
cpu.DIS:op_rate_3                            0.855043                       # dispatched operations per cycle
cpu.DIS:rate                                 2.553118                       # dispatched_insts per cycle
cpu.DIS:rate_0                               0.589505                       # dispatched_insts per cycle
cpu.DIS:rate_1                               0.593240                       # dispatched_insts per cycle
cpu.DIS:rate_2                               0.741039                       # dispatched_insts per cycle
cpu.DIS:rate_3                               0.629334                       # dispatched_insts per cycle
cpu.DIS:second_choice_clust                         0                       # Number of instructions dispatched to second-choice cluster
cpu.DIS:second_choice_stall                         0                       # Number of instructions stalled when first choice not available
cpu.DIS:serialize_stall_cycles                      0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_0                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_1                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_2                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serialize_stall_cycles_3                    0                       # count of cycles dispatch stalled for serializing inst
cpu.DIS:serializing_insts                           0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_0                         0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_1                         0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_2                         0                       # count of serializing insts dispatched
cpu.DIS:serializing_insts_3                         0                       # count of serializing insts dispatched
cpu.DIS:two_input_insts                             0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_0                           0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_1                           0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_2                           0                       # Number of two input instructions queued
cpu.DIS:two_input_insts_3                           0                       # Number of two input instructions queued
cpu.DIS:two_input_ratio                             0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_0                           0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_1                           0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_2                           0                       # fraction of all insts having 2 inputs
cpu.DIS:two_input_ratio_3                           0                       # fraction of all insts having 2 inputs
cpu.FETCH:branch_count                         797317                       # Number of branches fetched
cpu.FETCH:branch_count_0                       177043                       # Number of branches fetched
cpu.FETCH:branch_count_1                       178092                       # Number of branches fetched
cpu.FETCH:branch_count_2                       245297                       # Number of branches fetched
cpu.FETCH:branch_count_3                       196885                       # Number of branches fetched
cpu.FETCH:branch_rate                        0.448812                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_0                      0.099658                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_1                      0.100248                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_2                      0.138078                       # Number of branch fetches per cycle
cpu.FETCH:branch_rate_3                      0.110827                       # Number of branch fetches per cycle
cpu.FETCH:chance_pct_0                       0.223364                       # Percentage of all fetch chances
cpu.FETCH:chance_pct_1                       0.225093                       # Percentage of all fetch chances
cpu.FETCH:chance_pct_2                       0.304266                       # Percentage of all fetch chances
cpu.FETCH:chance_pct_3                       0.247278                       # Percentage of all fetch chances
cpu.FETCH:chances                              844488                       # Number of fetch opportunities
cpu.FETCH:chances_0                            188628                       # Number of fetch opportunities
cpu.FETCH:chances_1                            190088                       # Number of fetch opportunities
cpu.FETCH:chances_2                            256949                       # Number of fetch opportunities
cpu.FETCH:chances_3                            208823                       # Number of fetch opportunities
cpu.FETCH:choice                               844488                       # Number of times we fetched from our first choice
cpu.FETCH:choice.start_dist
                               0       844488    100.00%            # Number of times we fetched from our first choice
                               1            0      0.00%            # Number of times we fetched from our first choice
                               2            0      0.00%            # Number of times we fetched from our first choice
                               3            0      0.00%            # Number of times we fetched from our first choice
cpu.FETCH:choice.end_dist
cpu.FETCH:count                               6188286                       # Number of instructions fetched
cpu.FETCH:count_0                             1366382                       # Number of instructions fetched
cpu.FETCH:count_1                             1380875                       # Number of instructions fetched
cpu.FETCH:count_2                             1913100                       # Number of instructions fetched
cpu.FETCH:count_3                             1527929                       # Number of instructions fetched
cpu.FETCH:decisions                            844488                       # number of times the fetch stage chose between threads
cpu.FETCH:idle_cycles                          932019                       # number of cycles where fetch stage was idle
cpu.FETCH:idle_icache_blocked_cycles               58                       # number of cycles where fetch was idle due to icache blocked
cpu.FETCH:idle_rate                             52.46                       # percent of cycles fetch stage was idle
cpu.FETCH:prio_changes                              0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_0                            0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_1                            0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_2                            0                       # Number of times priorities were changed
cpu.FETCH:prio_changes_3                            0                       # Number of times priorities were changed
cpu.FETCH:rate                               3.483401                       # Number of inst fetches per cycle
cpu.FETCH:rate_0                             0.769140                       # Number of inst fetches per cycle
cpu.FETCH:rate_1                             0.777298                       # Number of inst fetches per cycle
cpu.FETCH:rate_2                             1.076889                       # Number of inst fetches per cycle
cpu.FETCH:rate_3                             0.860075                       # Number of inst fetches per cycle
cpu.FETCH:rate_dist.start_dist                                 # Number of instructions fetched each cycle (Total)
cpu.FETCH:rate_dist.samples                    844488                      
cpu.FETCH:rate_dist.min_value                       0                      
                               0         1618     19.16%           
                               1        12919    152.98%           
                               2        11262    133.36%           
                               3        19288    228.40%           
                               4        32559    385.55%           
                               5        25221    298.65%           
                               6        31033    367.48%           
                               7        32264    382.05%           
                               8       678324   8032.37%           
cpu.FETCH:rate_dist.max_value                       8                      
cpu.FETCH:rate_dist.end_dist

cpu.FETCH:rate_dist_0.start_dist                               # Number of instructions fetched each cycle (Thread 0)
cpu.FETCH:rate_dist_0.samples                  188628                      
cpu.FETCH:rate_dist_0.min_value                     0                      
                               0          468     24.81%           
                               1         3210    170.18%           
                               2         2790    147.91%           
                               3         4873    258.34%           
                               4         8341    442.19%           
                               5         6301    334.04%           
                               6         7657    405.93%           
                               7         7742    410.44%           
                               8       147246   7806.16%           
cpu.FETCH:rate_dist_0.max_value                     8                      
cpu.FETCH:rate_dist_0.end_dist

cpu.FETCH:rate_dist_1.start_dist                               # Number of instructions fetched each cycle (Thread 1)
cpu.FETCH:rate_dist_1.samples                  190088                      
cpu.FETCH:rate_dist_1.min_value                     0                      
                               0           55      2.89%           
                               1         3208    168.76%           
                               2         2840    149.40%           
                               3         4876    256.51%           
                               4         8285    435.85%           
                               5         6386    335.95%           
                               6         7716    405.92%           
                               7         7783    409.44%           
                               8       148939   7835.27%           
cpu.FETCH:rate_dist_1.max_value                     8                      
cpu.FETCH:rate_dist_1.end_dist

cpu.FETCH:rate_dist_2.start_dist                               # Number of instructions fetched each cycle (Thread 2)
cpu.FETCH:rate_dist_2.samples                  256949                      
cpu.FETCH:rate_dist_2.min_value                     0                      
                               0          940     36.58%           
                               1         3114    121.19%           
                               2         2709    105.43%           
                               3         4665    181.55%           
                               4         7619    296.52%           
                               5         6203    241.41%           
                               6         7874    306.44%           
                               7         8762    341.00%           
                               8       215063   8369.87%           
cpu.FETCH:rate_dist_2.max_value                     8                      
cpu.FETCH:rate_dist_2.end_dist

cpu.FETCH:rate_dist_3.start_dist                               # Number of instructions fetched each cycle (Thread 3)
cpu.FETCH:rate_dist_3.samples                  208823                      
cpu.FETCH:rate_dist_3.min_value                     0                      
                               0          155      7.42%           
                               1         3387    162.19%           
                               2         2923    139.98%           
                               3         4874    233.40%           
                               4         8314    398.14%           
                               5         6331    303.18%           
                               6         7786    372.85%           
                               7         7977    382.00%           
                               8       167076   8000.84%           
cpu.FETCH:rate_dist_3.max_value                     8                      
cpu.FETCH:rate_dist_3.end_dist

cpu.IFQ:count                                52944454                       # cumulative IFQ occupancy
cpu.IFQ:full_count                             441360                       # cumulative IFQ full count
cpu.IFQ:full_count_0                            98965                       # cumulative IFQ full count
cpu.IFQ:full_count_1                           101511                       # cumulative IFQ full count
cpu.IFQ:full_count_2                           129959                       # cumulative IFQ full count
cpu.IFQ:full_count_3                           110925                       # cumulative IFQ full count
cpu.IFQ:full_rate                           24.844259                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_0                          5.570763                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_1                          5.714078                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_2                          7.315423                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:full_rate_3                          6.243995                       # fraction of time (cycle's) IFQ was full
cpu.IFQ:latency                             11.673005                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_0                           50.555215                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_1                           50.236934                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_2                           40.217260                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:latency_3                           47.355721                       # avg IFQ occupant latency (cycle's)
cpu.IFQ:occupancy                           29.802559                       # avg IFQ occupancy (inst's)
cpu.IFQ:qfull_iq_occ                         21025979                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_0                        5077327                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_1                        5169558                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_2                        5431616                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_3                        5347478                       # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_0.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_0.samples            374611                      
cpu.IFQ:qfull_iq_occ_dist_0.min_value               0                      
                               0        92397   2466.48%           
                              10       256080   6835.89%           
                              20        15168    404.90%           
                              30         5860    156.43%           
                              40         1670     44.58%           
                              50         2336     62.36%           
                              60         1100     29.36%           
cpu.IFQ:qfull_iq_occ_dist_0.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_0.end_dist

cpu.IFQ:qfull_iq_occ_dist_1.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_1.samples            374611                      
cpu.IFQ:qfull_iq_occ_dist_1.min_value               0                      
                               0        87923   2347.05%           
                              10       257822   6882.39%           
                              20        18499    493.82%           
                              30         5074    135.45%           
                              40         2095     55.92%           
                              50         1875     50.05%           
                              60         1323     35.32%           
cpu.IFQ:qfull_iq_occ_dist_1.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_1.end_dist

cpu.IFQ:qfull_iq_occ_dist_2.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_2.samples            374611                      
cpu.IFQ:qfull_iq_occ_dist_2.min_value               0                      
                               0        79951   2134.24%           
                              10       261731   6986.74%           
                              20        17982    480.02%           
                              30         5709    152.40%           
                              40         2744     73.25%           
                              50         4130    110.25%           
                              60         2364     63.11%           
cpu.IFQ:qfull_iq_occ_dist_2.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_2.end_dist

cpu.IFQ:qfull_iq_occ_dist_3.start_dist                         # Number of insts in IQ when fetch-queue full
cpu.IFQ:qfull_iq_occ_dist_3.samples            374611                      
cpu.IFQ:qfull_iq_occ_dist_3.min_value               0                      
                               0        86031   2296.54%           
                              10       257063   6862.13%           
                              20        15831    422.60%           
                              30         6367    169.96%           
                              40         3358     89.64%           
                              50         3631     96.93%           
                              60         2330     62.20%           
cpu.IFQ:qfull_iq_occ_dist_3.max_value              64                      
cpu.IFQ:qfull_iq_occ_dist_3.end_dist

cpu.IFQ:qfull_rob_occ                        37040938                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_0                       8897820                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_1                       9132630                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_2                       9760433                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_3                       9250055                       # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_0.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_0.samples           374611                      
cpu.IFQ:qfull_rob_occ_dist_0.min_value              0                      
                               0        56120   1498.09%           
                              10        24948    665.97%           
                              20       250476   6686.30%           
                              30        16410    438.05%           
                              40         7883    210.43%           
                              50         3897    104.03%           
                              60         3147     84.01%           
                              70         2020     53.92%           
                              80         2233     59.61%           
                              90         2313     61.74%           
                             100         1080     28.83%           
                             110          791     21.12%           
                             120          558     14.90%           
                             130          348      9.29%           
                             140          350      9.34%           
                             150          471     12.57%           
                             160          192      5.13%           
                             170          450     12.01%           
                             180          450     12.01%           
                             190          474     12.65%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_0.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_0.end_dist

cpu.IFQ:qfull_rob_occ_dist_1.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_1.samples           374611                      
cpu.IFQ:qfull_rob_occ_dist_1.min_value              0                      
                               0        53225   1420.81%           
                              10        23242    620.43%           
                              20       252222   6732.90%           
                              30        17060    455.41%           
                              40         6742    179.97%           
                              50         5032    134.33%           
                              60         2911     77.71%           
                              70         3039     81.12%           
                              80         2366     63.16%           
                              90         1696     45.27%           
                             100         1495     39.91%           
                             110          852     22.74%           
                             120         1331     35.53%           
                             130         1281     34.20%           
                             140          518     13.83%           
                             150          449     11.99%           
                             160          401     10.70%           
                             170          129      3.44%           
                             180          256      6.83%           
                             190          364      9.72%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_1.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_1.end_dist

cpu.IFQ:qfull_rob_occ_dist_2.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_2.samples           374611                      
cpu.IFQ:qfull_rob_occ_dist_2.min_value              0                      
                               0        50238   1341.07%           
                              10        21023    561.20%           
                              20       253528   6767.77%           
                              30        14391    384.16%           
                              40         8133    217.11%           
                              50         5350    142.81%           
                              60         3374     90.07%           
                              70         3662     97.75%           
                              80         2081     55.55%           
                              90         2788     74.42%           
                             100         1980     52.85%           
                             110         1436     38.33%           
                             120         1004     26.80%           
                             130          840     22.42%           
                             140          559     14.92%           
                             150          574     15.32%           
                             160          394     10.52%           
                             170          464     12.39%           
                             180         1596     42.60%           
                             190         1196     31.93%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_2.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_2.end_dist

cpu.IFQ:qfull_rob_occ_dist_3.start_dist                        # Number of insts in ROB when fetch-queue full
cpu.IFQ:qfull_rob_occ_dist_3.samples           374611                      
cpu.IFQ:qfull_rob_occ_dist_3.min_value              0                      
                               0        53814   1436.53%           
                              10        25991    693.81%           
                              20       249038   6647.91%           
                              30        13854    369.82%           
                              40         7102    189.58%           
                              50         6166    164.60%           
                              60         4563    121.81%           
                              70         3774    100.74%           
                              80         1611     43.00%           
                              90         1779     47.49%           
                             100         1032     27.55%           
                             110          840     22.42%           
                             120          797     21.28%           
                             130          837     22.34%           
                             140          517     13.80%           
                             150          484     12.92%           
                             160          507     13.53%           
                             170          429     11.45%           
                             180          799     21.33%           
                             190          677     18.07%           
                             200            0      0.00%           
cpu.IFQ:qfull_rob_occ_dist_3.max_value            196                      
cpu.IFQ:qfull_rob_occ_dist_3.end_dist

cpu.IQ:cap_events                                   0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_0                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_1                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_2                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_events_3                                 0                       # number of cycles where IQ cap was active
cpu.IQ:cap_inst                                     0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_0                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_1                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_2                                   0                       # number of instructions held up by IQ cap
cpu.IQ:cap_inst_3                                   0                       # number of instructions held up by IQ cap
cpu.IQ:residence:(null).start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:(null).samples                     0                      
cpu.IQ:residence:(null).min_value                   0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:(null).max_value                   0                      
cpu.IQ:residence:(null).end_dist

cpu.IQ:residence:IntAlu.start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:IntAlu.samples               2675396                      
cpu.IQ:residence:IntAlu.min_value                   1                      
                               0       738322   2759.67%   2759.67%
                               2       498495   1863.26%   4622.93%
                               4       256951    960.42%   5583.35%
                               6       400334   1496.35%   7079.71%
                               8       204930    765.98%   7845.69%
                              10       148751    556.00%   8401.68%
                              12        96418    360.39%   8762.07%
                              14        65399    244.45%   9006.52%
                              16        47150    176.24%   9182.75%
                              18        32135    120.11%   9302.87%
                              20        24634     92.08%   9394.94%
                              22        22456     83.94%   9478.88%
                              24        15619     58.38%   9537.26%
                              26        12627     47.20%   9584.45%
                              28        11341     42.39%   9626.84%
                              30         8591     32.11%   9658.96%
                              32         6289     23.51%   9682.46%
                              34         4834     18.07%   9700.53%
                              36         4309     16.11%   9716.64%
                              38         3232     12.08%   9728.72%
                              40         3011     11.25%   9739.97%
                              42         3694     13.81%   9753.78%
                              44         3171     11.85%   9765.63%
                              46         2438      9.11%   9774.74%
                              48         2172      8.12%   9782.86%
                              50         1767      6.60%   9789.47%
                              52         1431      5.35%   9794.82%
                              54         1152      4.31%   9799.12%
                              56         1034      3.86%   9802.99%
                              58         1012      3.78%   9806.77%
                              60         1047      3.91%   9810.68%
                              62         1134      4.24%   9814.92%
                              64         1040      3.89%   9818.81%
                              66          811      3.03%   9821.84%
                              68          614      2.29%   9824.13%
                              70          499      1.87%   9826.00%
                              72          496      1.85%   9827.85%
                              74          565      2.11%   9829.97%
                              76          623      2.33%   9832.29%
                              78          511      1.91%   9834.20%
                              80          469      1.75%   9835.96%
                              82          433      1.62%   9837.58%
                              84          419      1.57%   9839.14%
                              86          320      1.20%   9840.34%
                              88          372      1.39%   9841.73%
                              90          334      1.25%   9842.98%
                              92          342      1.28%   9844.25%
                              94          398      1.49%   9845.74%
                              96          397      1.48%   9847.23%
                              98          414      1.55%   9848.77%
cpu.IQ:residence:IntAlu.overflows               40459                      
cpu.IQ:residence:IntAlu.max_value                1011                      
cpu.IQ:residence:IntAlu.end_dist

cpu.IQ:residence:IntMult.start_dist                            # cycles from dispatch to issue
cpu.IQ:residence:IntMult.samples                 6983                      
cpu.IQ:residence:IntMult.min_value                  1                      
                               0         1250   1790.06%   1790.06%
                               2         1420   2033.51%   3823.57%
                               4          546    781.90%   4605.47%
                               6         1881   2693.68%   7299.16%
                               8          748   1071.17%   8370.33%
                              10          458    655.88%   9026.21%
                              12          298    426.75%   9452.96%
                              14          124    177.57%   9630.53%
                              16           50     71.60%   9702.13%
                              18           29     41.53%   9743.66%
                              20           39     55.85%   9799.51%
                              22           77    110.27%   9909.78%
                              24           23     32.94%   9942.72%
                              26           17     24.34%   9967.06%
                              28            3      4.30%   9971.36%
                              30            2      2.86%   9974.22%
                              32            1      1.43%   9975.66%
                              34            0      0.00%   9975.66%
                              36            1      1.43%   9977.09%
                              38            1      1.43%   9978.52%
                              40            0      0.00%   9978.52%
                              42            0      0.00%   9978.52%
                              44            1      1.43%   9979.95%
                              46            0      0.00%   9979.95%
                              48            0      0.00%   9979.95%
                              50            0      0.00%   9979.95%
                              52            0      0.00%   9979.95%
                              54            0      0.00%   9979.95%
                              56            0      0.00%   9979.95%
                              58            0      0.00%   9979.95%
                              60            0      0.00%   9979.95%
                              62            0      0.00%   9979.95%
                              64            0      0.00%   9979.95%
                              66            0      0.00%   9979.95%
                              68            0      0.00%   9979.95%
                              70            0      0.00%   9979.95%
                              72            0      0.00%   9979.95%
                              74            0      0.00%   9979.95%
                              76            0      0.00%   9979.95%
                              78            0      0.00%   9979.95%
                              80            0      0.00%   9979.95%
                              82            0      0.00%   9979.95%
                              84            0      0.00%   9979.95%
                              86            0      0.00%   9979.95%
                              88            0      0.00%   9979.95%
                              90            1      1.43%   9981.38%
                              92            0      0.00%   9981.38%
                              94            0      0.00%   9981.38%
                              96            0      0.00%   9981.38%
                              98            0      0.00%   9981.38%
cpu.IQ:residence:IntMult.overflows                 13                      
cpu.IQ:residence:IntMult.max_value                139                      
cpu.IQ:residence:IntMult.end_dist

cpu.IQ:residence:IntDiv.start_dist                             # cycles from dispatch to issue
cpu.IQ:residence:IntDiv.samples                     0                      
cpu.IQ:residence:IntDiv.min_value                   0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:IntDiv.max_value                   0                      
cpu.IQ:residence:IntDiv.end_dist

cpu.IQ:residence:FloatAdd.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatAdd.samples                 423                      
cpu.IQ:residence:FloatAdd.min_value                 1                      
                               0           23    543.74%    543.74%
                               2           96   2269.50%   2813.24%
                               4           22    520.09%   3333.33%
                               6           12    283.69%   3617.02%
                               8           17    401.89%   4018.91%
                              10           36    851.06%   4869.98%
                              12           99   2340.43%   7210.40%
                              14            9    212.77%   7423.17%
                              16           12    283.69%   7706.86%
                              18           12    283.69%   7990.54%
                              20            2     47.28%   8037.83%
                              22           10    236.41%   8274.23%
                              24           30    709.22%   8983.45%
                              26           32    756.50%   9739.95%
                              28            1     23.64%   9763.59%
                              30            5    118.20%   9881.80%
                              32            0      0.00%   9881.80%
                              34            0      0.00%   9881.80%
                              36            1     23.64%   9905.44%
                              38            0      0.00%   9905.44%
                              40            0      0.00%   9905.44%
                              42            0      0.00%   9905.44%
                              44            0      0.00%   9905.44%
                              46            0      0.00%   9905.44%
                              48            0      0.00%   9905.44%
                              50            0      0.00%   9905.44%
                              52            0      0.00%   9905.44%
                              54            0      0.00%   9905.44%
                              56            0      0.00%   9905.44%
                              58            0      0.00%   9905.44%
                              60            0      0.00%   9905.44%
                              62            0      0.00%   9905.44%
                              64            0      0.00%   9905.44%
                              66            0      0.00%   9905.44%
                              68            0      0.00%   9905.44%
                              70            0      0.00%   9905.44%
                              72            0      0.00%   9905.44%
                              74            0      0.00%   9905.44%
                              76            0      0.00%   9905.44%
                              78            0      0.00%   9905.44%
                              80            0      0.00%   9905.44%
                              82            0      0.00%   9905.44%
                              84            0      0.00%   9905.44%
                              86            0      0.00%   9905.44%
                              88            0      0.00%   9905.44%
                              90            0      0.00%   9905.44%
                              92            0      0.00%   9905.44%
                              94            0      0.00%   9905.44%
                              96            0      0.00%   9905.44%
                              98            0      0.00%   9905.44%
cpu.IQ:residence:FloatAdd.overflows                 4                      
cpu.IQ:residence:FloatAdd.max_value               139                      
cpu.IQ:residence:FloatAdd.end_dist

cpu.IQ:residence:FloatCmp.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatCmp.samples                   8                      
cpu.IQ:residence:FloatCmp.min_value                 9                      
                               0            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               6            0      0.00%      0.00%
                               8            1   1250.00%   1250.00%
                              10            3   3750.00%   5000.00%
                              12            0      0.00%   5000.00%
                              14            0      0.00%   5000.00%
                              16            0      0.00%   5000.00%
                              18            0      0.00%   5000.00%
                              20            0      0.00%   5000.00%
                              22            0      0.00%   5000.00%
                              24            0      0.00%   5000.00%
                              26            0      0.00%   5000.00%
                              28            0      0.00%   5000.00%
                              30            0      0.00%   5000.00%
                              32            0      0.00%   5000.00%
                              34            0      0.00%   5000.00%
                              36            0      0.00%   5000.00%
                              38            0      0.00%   5000.00%
                              40            0      0.00%   5000.00%
                              42            0      0.00%   5000.00%
                              44            0      0.00%   5000.00%
                              46            0      0.00%   5000.00%
                              48            0      0.00%   5000.00%
                              50            0      0.00%   5000.00%
                              52            0      0.00%   5000.00%
                              54            0      0.00%   5000.00%
                              56            0      0.00%   5000.00%
                              58            0      0.00%   5000.00%
                              60            0      0.00%   5000.00%
                              62            0      0.00%   5000.00%
                              64            0      0.00%   5000.00%
                              66            0      0.00%   5000.00%
                              68            0      0.00%   5000.00%
                              70            0      0.00%   5000.00%
                              72            0      0.00%   5000.00%
                              74            0      0.00%   5000.00%
                              76            0      0.00%   5000.00%
                              78            0      0.00%   5000.00%
                              80            0      0.00%   5000.00%
                              82            0      0.00%   5000.00%
                              84            0      0.00%   5000.00%
                              86            0      0.00%   5000.00%
                              88            0      0.00%   5000.00%
                              90            0      0.00%   5000.00%
                              92            0      0.00%   5000.00%
                              94            0      0.00%   5000.00%
                              96            0      0.00%   5000.00%
                              98            0      0.00%   5000.00%
cpu.IQ:residence:FloatCmp.overflows                 4                      
cpu.IQ:residence:FloatCmp.max_value               137                      
cpu.IQ:residence:FloatCmp.end_dist

cpu.IQ:residence:FloatCvt.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatCvt.samples                 534                      
cpu.IQ:residence:FloatCvt.min_value                 1                      
                               0          210   3932.58%   3932.58%
                               2           44    823.97%   4756.55%
                               4            3     56.18%   4812.73%
                               6            9    168.54%   4981.27%
                               8           11    205.99%   5187.27%
                              10          122   2284.64%   7471.91%
                              12           18    337.08%   7808.99%
                              14            7    131.09%   7940.07%
                              16            7    131.09%   8071.16%
                              18            5     93.63%   8164.79%
                              20            8    149.81%   8314.61%
                              22            5     93.63%   8408.24%
                              24            8    149.81%   8558.05%
                              26           30    561.80%   9119.85%
                              28           33    617.98%   9737.83%
                              30            2     37.45%   9775.28%
                              32            4     74.91%   9850.19%
                              34            0      0.00%   9850.19%
                              36            0      0.00%   9850.19%
                              38            1     18.73%   9868.91%
                              40            0      0.00%   9868.91%
                              42            1     18.73%   9887.64%
                              44            0      0.00%   9887.64%
                              46            0      0.00%   9887.64%
                              48            0      0.00%   9887.64%
                              50            0      0.00%   9887.64%
                              52            0      0.00%   9887.64%
                              54            0      0.00%   9887.64%
                              56            0      0.00%   9887.64%
                              58            0      0.00%   9887.64%
                              60            0      0.00%   9887.64%
                              62            0      0.00%   9887.64%
                              64            0      0.00%   9887.64%
                              66            0      0.00%   9887.64%
                              68            0      0.00%   9887.64%
                              70            0      0.00%   9887.64%
                              72            0      0.00%   9887.64%
                              74            0      0.00%   9887.64%
                              76            0      0.00%   9887.64%
                              78            0      0.00%   9887.64%
                              80            0      0.00%   9887.64%
                              82            0      0.00%   9887.64%
                              84            1     18.73%   9906.37%
                              86            0      0.00%   9906.37%
                              88            1     18.73%   9925.09%
                              90            0      0.00%   9925.09%
                              92            0      0.00%   9925.09%
                              94            0      0.00%   9925.09%
                              96            0      0.00%   9925.09%
                              98            1     18.73%   9943.82%
cpu.IQ:residence:FloatCvt.overflows                 3                      
cpu.IQ:residence:FloatCvt.max_value               139                      
cpu.IQ:residence:FloatCvt.end_dist

cpu.IQ:residence:FloatMult.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:FloatMult.samples                  4                      
cpu.IQ:residence:FloatMult.min_value                6                      
                               0            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               6            4  10000.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.IQ:residence:FloatMult.max_value                7                      
cpu.IQ:residence:FloatMult.end_dist

cpu.IQ:residence:FloatDiv.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:FloatDiv.samples                  99                      
cpu.IQ:residence:FloatDiv.min_value                 1                      
                               0            1    101.01%    101.01%
                               2            1    101.01%    202.02%
                               4            6    606.06%    808.08%
                               6           11   1111.11%   1919.19%
                               8            2    202.02%   2121.21%
                              10            9    909.09%   3030.30%
                              12           28   2828.28%   5858.59%
                              14           33   3333.33%   9191.92%
                              16            1    101.01%   9292.93%
                              18            6    606.06%   9898.99%
                              20            0      0.00%   9898.99%
                              22            0      0.00%   9898.99%
                              24            1    101.01%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.IQ:residence:FloatDiv.max_value                25                      
cpu.IQ:residence:FloatDiv.end_dist

cpu.IQ:residence:FloatSqrt.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:FloatSqrt.samples                  0                      
cpu.IQ:residence:FloatSqrt.min_value                0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:FloatSqrt.max_value                0                      
cpu.IQ:residence:FloatSqrt.end_dist

cpu.IQ:residence:MemRead.start_dist                            # cycles from dispatch to issue
cpu.IQ:residence:MemRead.samples              2049767                      
cpu.IQ:residence:MemRead.min_value                  1                      
                               0       464312   2265.19%   2265.19%
                               2       789066   3849.54%   6114.73%
                               4       229660   1120.42%   7235.15%
                               6       183166    893.59%   8128.75%
                               8       122861    599.39%   8728.14%
                              10        80028    390.42%   9118.56%
                              12        43898    214.16%   9332.72%
                              14        24655    120.28%   9453.01%
                              16        16569     80.83%   9533.84%
                              18        11434     55.78%   9589.62%
                              20         8766     42.77%   9632.39%
                              22         8063     39.34%   9671.72%
                              24         5494     26.80%   9698.53%
                              26         4553     22.21%   9720.74%
                              28         3202     15.62%   9736.36%
                              30         2477     12.08%   9748.44%
                              32         2373     11.58%   9760.02%
                              34         1986      9.69%   9769.71%
                              36         1517      7.40%   9777.11%
                              38         1455      7.10%   9784.21%
                              40         1534      7.48%   9791.69%
                              42         1684      8.22%   9799.91%
                              44         1452      7.08%   9806.99%
                              46          947      4.62%   9811.61%
                              48          841      4.10%   9815.72%
                              50          630      3.07%   9818.79%
                              52          529      2.58%   9821.37%
                              54          467      2.28%   9823.65%
                              56          441      2.15%   9825.80%
                              58          413      2.01%   9827.81%
                              60          632      3.08%   9830.90%
                              62          643      3.14%   9834.03%
                              64          482      2.35%   9836.39%
                              66          355      1.73%   9838.12%
                              68          242      1.18%   9839.30%
                              70          237      1.16%   9840.46%
                              72          251      1.22%   9841.68%
                              74          229      1.12%   9842.80%
                              76          217      1.06%   9843.86%
                              78          276      1.35%   9845.20%
                              80          200      0.98%   9846.18%
                              82          280      1.37%   9847.54%
                              84          251      1.22%   9848.77%
                              86          241      1.18%   9849.94%
                              88          252      1.23%   9851.17%
                              90          250      1.22%   9852.39%
                              92          249      1.21%   9853.61%
                              94          269      1.31%   9854.92%
                              96          290      1.41%   9856.33%
                              98          269      1.31%   9857.65%
cpu.IQ:residence:MemRead.overflows              29179                      
cpu.IQ:residence:MemRead.max_value                990                      
cpu.IQ:residence:MemRead.end_dist

cpu.IQ:residence:MemWrite.start_dist                           # cycles from dispatch to issue
cpu.IQ:residence:MemWrite.samples             1001486                      
cpu.IQ:residence:MemWrite.min_value                 1                      
                               0       162584   1623.43%   1623.43%
                               2       405195   4045.94%   5669.37%
                               4       136723   1365.20%   7034.57%
                               6       103186   1030.33%   8064.90%
                               8        65637    655.40%   8720.29%
                              10        47618    475.47%   9195.77%
                              12        27145    271.05%   9466.81%
                              14        12354    123.36%   9590.17%
                              16         7738     77.27%   9667.43%
                              18         4800     47.93%   9715.36%
                              20         3467     34.62%   9749.98%
                              22         3088     30.83%   9780.82%
                              24         2159     21.56%   9802.37%
                              26         1874     18.71%   9821.09%
                              28         1427     14.25%   9835.33%
                              30          969      9.68%   9845.01%
                              32          851      8.50%   9853.51%
                              34          578      5.77%   9859.28%
                              36          431      4.30%   9863.58%
                              38          366      3.65%   9867.24%
                              40          323      3.23%   9870.46%
                              42          308      3.08%   9873.54%
                              44          211      2.11%   9875.64%
                              46          123      1.23%   9876.87%
                              48          170      1.70%   9878.57%
                              50          141      1.41%   9879.98%
                              52          193      1.93%   9881.91%
                              54          164      1.64%   9883.54%
                              56           94      0.94%   9884.48%
                              58          104      1.04%   9885.52%
                              60          107      1.07%   9886.59%
                              62          120      1.20%   9887.79%
                              64          158      1.58%   9889.36%
                              66          148      1.48%   9890.84%
                              68          113      1.13%   9891.97%
                              70          116      1.16%   9893.13%
                              72           87      0.87%   9894.00%
                              74          114      1.14%   9895.14%
                              76          156      1.56%   9896.69%
                              78          205      2.05%   9898.74%
                              80          136      1.36%   9900.10%
                              82          101      1.01%   9901.11%
                              84          121      1.21%   9902.32%
                              86          112      1.12%   9903.43%
                              88          154      1.54%   9904.97%
                              90          176      1.76%   9906.73%
                              92          194      1.94%   9908.67%
                              94          224      2.24%   9910.90%
                              96          212      2.12%   9913.02%
                              98          299      2.99%   9916.00%
cpu.IQ:residence:MemWrite.overflows              8412                      
cpu.IQ:residence:MemWrite.max_value               508                      
cpu.IQ:residence:MemWrite.end_dist

cpu.IQ:residence:IprAccess.start_dist                          # cycles from dispatch to issue
cpu.IQ:residence:IprAccess.samples                  0                      
cpu.IQ:residence:IprAccess.min_value                0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:IprAccess.max_value                0                      
cpu.IQ:residence:IprAccess.end_dist

cpu.IQ:residence:InstPrefetch.start_dist                       # cycles from dispatch to issue
cpu.IQ:residence:InstPrefetch.samples               0                      
cpu.IQ:residence:InstPrefetch.min_value             0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.IQ:residence:InstPrefetch.max_value             0                      
cpu.IQ:residence:InstPrefetch.end_dist

cpu.ISSUE:(null)_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:(null)_delay.samples                      0                      
cpu.ISSUE:(null)_delay.min_value                    0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:(null)_delay.max_value                    0                      
cpu.ISSUE:(null)_delay.end_dist

cpu.ISSUE:IntAlu_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:IntAlu_delay.samples                2675396                      
cpu.ISSUE:IntAlu_delay.min_value                    0                      
                               0      2277968   8514.51%   8514.51%
                               2       247701    925.85%   9440.36%
                               4        77716    290.48%   9730.84%
                               6        39294    146.87%   9877.71%
                               8        22815     85.28%   9962.99%
                              10         9264     34.63%   9997.62%
                              12          638      2.38%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:IntAlu_delay.max_value                   13                      
cpu.ISSUE:IntAlu_delay.end_dist

cpu.ISSUE:IntMult_delay.start_dist                             # cycles from operands ready to issue
cpu.ISSUE:IntMult_delay.samples                  6983                      
cpu.ISSUE:IntMult_delay.min_value                   0                      
                               0         6367   9117.86%   9117.86%
                               2          549    786.20%   9904.05%
                               4           43     61.58%   9965.63%
                               6           21     30.07%   9995.70%
                               8            3      4.30%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:IntMult_delay.max_value                   8                      
cpu.ISSUE:IntMult_delay.end_dist

cpu.ISSUE:IntDiv_delay.start_dist                              # cycles from operands ready to issue
cpu.ISSUE:IntDiv_delay.samples                      0                      
cpu.ISSUE:IntDiv_delay.min_value                    0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:IntDiv_delay.max_value                    0                      
cpu.ISSUE:IntDiv_delay.end_dist

cpu.ISSUE:FloatAdd_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatAdd_delay.samples                  423                      
cpu.ISSUE:FloatAdd_delay.min_value                  0                      
                               0          418   9881.80%   9881.80%
                               2            5    118.20%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatAdd_delay.max_value                  3                      
cpu.ISSUE:FloatAdd_delay.end_dist

cpu.ISSUE:FloatCmp_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatCmp_delay.samples                    8                      
cpu.ISSUE:FloatCmp_delay.min_value                  0                      
                               0            8  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatCmp_delay.max_value                  0                      
cpu.ISSUE:FloatCmp_delay.end_dist

cpu.ISSUE:FloatCvt_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatCvt_delay.samples                  534                      
cpu.ISSUE:FloatCvt_delay.min_value                  0                      
                               0          504   9438.20%   9438.20%
                               2           27    505.62%   9943.82%
                               4            1     18.73%   9962.55%
                               6            2     37.45%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatCvt_delay.max_value                  7                      
cpu.ISSUE:FloatCvt_delay.end_dist

cpu.ISSUE:FloatMult_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:FloatMult_delay.samples                   4                      
cpu.ISSUE:FloatMult_delay.min_value                 0                      
                               0            4  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatMult_delay.max_value                 0                      
cpu.ISSUE:FloatMult_delay.end_dist

cpu.ISSUE:FloatDiv_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:FloatDiv_delay.samples                   99                      
cpu.ISSUE:FloatDiv_delay.min_value                  0                      
                               0           99  10000.00%  10000.00%
                               2            0      0.00%  10000.00%
                               4            0      0.00%  10000.00%
                               6            0      0.00%  10000.00%
                               8            0      0.00%  10000.00%
                              10            0      0.00%  10000.00%
                              12            0      0.00%  10000.00%
                              14            0      0.00%  10000.00%
                              16            0      0.00%  10000.00%
                              18            0      0.00%  10000.00%
                              20            0      0.00%  10000.00%
                              22            0      0.00%  10000.00%
                              24            0      0.00%  10000.00%
                              26            0      0.00%  10000.00%
                              28            0      0.00%  10000.00%
                              30            0      0.00%  10000.00%
                              32            0      0.00%  10000.00%
                              34            0      0.00%  10000.00%
                              36            0      0.00%  10000.00%
                              38            0      0.00%  10000.00%
                              40            0      0.00%  10000.00%
                              42            0      0.00%  10000.00%
                              44            0      0.00%  10000.00%
                              46            0      0.00%  10000.00%
                              48            0      0.00%  10000.00%
                              50            0      0.00%  10000.00%
                              52            0      0.00%  10000.00%
                              54            0      0.00%  10000.00%
                              56            0      0.00%  10000.00%
                              58            0      0.00%  10000.00%
                              60            0      0.00%  10000.00%
                              62            0      0.00%  10000.00%
                              64            0      0.00%  10000.00%
                              66            0      0.00%  10000.00%
                              68            0      0.00%  10000.00%
                              70            0      0.00%  10000.00%
                              72            0      0.00%  10000.00%
                              74            0      0.00%  10000.00%
                              76            0      0.00%  10000.00%
                              78            0      0.00%  10000.00%
                              80            0      0.00%  10000.00%
                              82            0      0.00%  10000.00%
                              84            0      0.00%  10000.00%
                              86            0      0.00%  10000.00%
                              88            0      0.00%  10000.00%
                              90            0      0.00%  10000.00%
                              92            0      0.00%  10000.00%
                              94            0      0.00%  10000.00%
                              96            0      0.00%  10000.00%
                              98            0      0.00%  10000.00%
cpu.ISSUE:FloatDiv_delay.max_value                  0                      
cpu.ISSUE:FloatDiv_delay.end_dist

cpu.ISSUE:FloatSqrt_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:FloatSqrt_delay.samples                   0                      
cpu.ISSUE:FloatSqrt_delay.min_value                 0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:FloatSqrt_delay.max_value                 0                      
cpu.ISSUE:FloatSqrt_delay.end_dist

cpu.ISSUE:MemRead_delay.start_dist                             # cycles from operands ready to issue
cpu.ISSUE:MemRead_delay.samples               2049767                      
cpu.ISSUE:MemRead_delay.min_value                   0                      
                               0      1724766   8414.45%   8414.45%
                               2       201157    981.37%   9395.81%
                               4        61126    298.21%   9694.02%
                               6        31172    152.08%   9846.10%
                               8        17452     85.14%   9931.24%
                              10         6948     33.90%   9965.14%
                              12          427      2.08%   9967.22%
                              14           79      0.39%   9967.61%
                              16           64      0.31%   9967.92%
                              18           45      0.22%   9968.14%
                              20           24      0.12%   9968.25%
                              22           36      0.18%   9968.43%
                              24           32      0.16%   9968.59%
                              26           39      0.19%   9968.78%
                              28           38      0.19%   9968.96%
                              30           21      0.10%   9969.06%
                              32           18      0.09%   9969.15%
                              34           16      0.08%   9969.23%
                              36           15      0.07%   9969.30%
                              38            5      0.02%   9969.33%
                              40           34      0.17%   9969.49%
                              42           26      0.13%   9969.62%
                              44            3      0.01%   9969.64%
                              46           25      0.12%   9969.76%
                              48           31      0.15%   9969.91%
                              50           19      0.09%   9970.00%
                              52           23      0.11%   9970.11%
                              54           22      0.11%   9970.22%
                              56            5      0.02%   9970.25%
                              58           23      0.11%   9970.36%
                              60           22      0.11%   9970.46%
                              62           22      0.11%   9970.57%
                              64           21      0.10%   9970.67%
                              66           25      0.12%   9970.80%
                              68           61      0.30%   9971.09%
                              70           36      0.18%   9971.27%
                              72           34      0.17%   9971.44%
                              74           52      0.25%   9971.69%
                              76           66      0.32%   9972.01%
                              78           44      0.21%   9972.23%
                              80           60      0.29%   9972.52%
                              82           69      0.34%   9972.86%
                              84           65      0.32%   9973.17%
                              86          124      0.60%   9973.78%
                              88          110      0.54%   9974.31%
                              90          104      0.51%   9974.82%
                              92          146      0.71%   9975.53%
                              94          170      0.83%   9976.36%
                              96          158      0.77%   9977.13%
                              98          249      1.21%   9978.35%
cpu.ISSUE:MemRead_delay.overflows                4438                      
cpu.ISSUE:MemRead_delay.max_value                 254                      
cpu.ISSUE:MemRead_delay.end_dist

cpu.ISSUE:MemWrite_delay.start_dist                            # cycles from operands ready to issue
cpu.ISSUE:MemWrite_delay.samples              1001486                      
cpu.ISSUE:MemWrite_delay.min_value                  0                      
                               0       861399   8601.21%   8601.21%
                               2        86797    866.68%   9467.89%
                               4        24520    244.84%   9712.73%
                               6        12009    119.91%   9832.64%
                               8         6990     69.80%   9902.43%
                              10         2710     27.06%   9929.49%
                              12          232      2.32%   9931.81%
                              14            9      0.09%   9931.90%
                              16           12      0.12%   9932.02%
                              18            7      0.07%   9932.09%
                              20            4      0.04%   9932.13%
                              22            5      0.05%   9932.18%
                              24            6      0.06%   9932.24%
                              26            4      0.04%   9932.28%
                              28            4      0.04%   9932.32%
                              30            5      0.05%   9932.37%
                              32            6      0.06%   9932.43%
                              34            5      0.05%   9932.48%
                              36            2      0.02%   9932.50%
                              38            9      0.09%   9932.59%
                              40           15      0.15%   9932.74%
                              42            5      0.05%   9932.79%
                              44           22      0.22%   9933.01%
                              46           26      0.26%   9933.27%
                              48           29      0.29%   9933.56%
                              50           35      0.35%   9933.91%
                              52           27      0.27%   9934.18%
                              54           10      0.10%   9934.28%
                              56           25      0.25%   9934.53%
                              58           13      0.13%   9934.66%
                              60           12      0.12%   9934.78%
                              62           17      0.17%   9934.95%
                              64           31      0.31%   9935.26%
                              66           29      0.29%   9935.55%
                              68           60      0.60%   9936.14%
                              70           29      0.29%   9936.43%
                              72           38      0.38%   9936.81%
                              74           32      0.32%   9937.13%
                              76           64      0.64%   9937.77%
                              78           59      0.59%   9938.36%
                              80           66      0.66%   9939.02%
                              82           78      0.78%   9939.80%
                              84          105      1.05%   9940.85%
                              86          123      1.23%   9942.08%
                              88          166      1.66%   9943.73%
                              90          199      1.99%   9945.72%
                              92          194      1.94%   9947.66%
                              94          273      2.73%   9950.38%
                              96          251      2.51%   9952.89%
                              98          235      2.35%   9955.24%
cpu.ISSUE:MemWrite_delay.overflows               4483                      
cpu.ISSUE:MemWrite_delay.max_value                128                      
cpu.ISSUE:MemWrite_delay.end_dist

cpu.ISSUE:IprAccess_delay.start_dist                           # cycles from operands ready to issue
cpu.ISSUE:IprAccess_delay.samples                   0                      
cpu.ISSUE:IprAccess_delay.min_value                 0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:IprAccess_delay.max_value                 0                      
cpu.ISSUE:IprAccess_delay.end_dist

cpu.ISSUE:InstPrefetch_delay.start_dist                        # cycles from operands ready to issue
cpu.ISSUE:InstPrefetch_delay.samples                0                      
cpu.ISSUE:InstPrefetch_delay.min_value              0                      
                               0            0                      
                               2            0                      
                               4            0                      
                               6            0                      
                               8            0                      
                              10            0                      
                              12            0                      
                              14            0                      
                              16            0                      
                              18            0                      
                              20            0                      
                              22            0                      
                              24            0                      
                              26            0                      
                              28            0                      
                              30            0                      
                              32            0                      
                              34            0                      
                              36            0                      
                              38            0                      
                              40            0                      
                              42            0                      
                              44            0                      
                              46            0                      
                              48            0                      
                              50            0                      
                              52            0                      
                              54            0                      
                              56            0                      
                              58            0                      
                              60            0                      
                              62            0                      
                              64            0                      
                              66            0                      
                              68            0                      
                              70            0                      
                              72            0                      
                              74            0                      
                              76            0                      
                              78            0                      
                              80            0                      
                              82            0                      
                              84            0                      
                              86            0                      
                              88            0                      
                              90            0                      
                              92            0                      
                              94            0                      
                              96            0                      
                              98            0                      
cpu.ISSUE:InstPrefetch_delay.max_value              0                      
cpu.ISSUE:InstPrefetch_delay.end_dist

cpu.ISSUE:FU_type_0                           1341253                       # Type of FU issued
cpu.ISSUE:FU_type_0.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu       992465     74.00%            # Type of FU issued
                         IntMult         1700      0.13%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd          105      0.01%            # Type of FU issued
                        FloatCmp            2      0.00%            # Type of FU issued
                        FloatCvt          134      0.01%            # Type of FU issued
                       FloatMult            1      0.00%            # Type of FU issued
                        FloatDiv           24      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       237731     17.72%            # Type of FU issued
                        MemWrite       109091      8.13%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_0.end_dist
cpu.ISSUE:FU_type_1                           1345355                       # Type of FU issued
cpu.ISSUE:FU_type_1.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu       995762     74.01%            # Type of FU issued
                         IntMult         1705      0.13%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd          104      0.01%            # Type of FU issued
                        FloatCmp            2      0.00%            # Type of FU issued
                        FloatCvt          129      0.01%            # Type of FU issued
                       FloatMult            1      0.00%            # Type of FU issued
                        FloatDiv           25      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       238578     17.73%            # Type of FU issued
                        MemWrite       109049      8.11%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_1.end_dist
cpu.ISSUE:FU_type_2                           1604628                       # Type of FU issued
cpu.ISSUE:FU_type_2.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu      1193221     74.36%            # Type of FU issued
                         IntMult         1810      0.11%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd          106      0.01%            # Type of FU issued
                        FloatCmp            2      0.00%            # Type of FU issued
                        FloatCvt          137      0.01%            # Type of FU issued
                       FloatMult            1      0.00%            # Type of FU issued
                        FloatDiv           24      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       288499     17.98%            # Type of FU issued
                        MemWrite       120828      7.53%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_2.end_dist
cpu.ISSUE:FU_type_3                           1402032                       # Type of FU issued
cpu.ISSUE:FU_type_3.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu      1039800     74.16%            # Type of FU issued
                         IntMult         1768      0.13%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd          108      0.01%            # Type of FU issued
                        FloatCmp            2      0.00%            # Type of FU issued
                        FloatCvt          134      0.01%            # Type of FU issued
                       FloatMult            1      0.00%            # Type of FU issued
                        FloatDiv           26      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead       249180     17.77%            # Type of FU issued
                        MemWrite       111013      7.92%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type_3.end_dist
cpu.ISSUE:FU_type                             5693268                       # Type of FU issued
cpu.ISSUE:FU_type.start_dist
                          (null)            0      0.00%            # Type of FU issued
                          IntAlu      4221248     74.14%            # Type of FU issued
                         IntMult         6983      0.12%            # Type of FU issued
                          IntDiv            0      0.00%            # Type of FU issued
                        FloatAdd          423      0.01%            # Type of FU issued
                        FloatCmp            8      0.00%            # Type of FU issued
                        FloatCvt          534      0.01%            # Type of FU issued
                       FloatMult            4      0.00%            # Type of FU issued
                        FloatDiv           99      0.00%            # Type of FU issued
                       FloatSqrt            0      0.00%            # Type of FU issued
                         MemRead      1013988     17.81%            # Type of FU issued
                        MemWrite       449981      7.90%            # Type of FU issued
                       IprAccess            0      0.00%            # Type of FU issued
                    InstPrefetch            0      0.00%            # Type of FU issued
cpu.ISSUE:FU_type.end_dist
cpu.ISSUE:IQ_0:fu_full.start_dist
                          (null)            0      0.00%           
                          IntAlu      1099856     84.31%           
                         IntMult          212      0.02%           
                          IntDiv            0      0.00%           
                        FloatAdd            0      0.00%           
                        FloatCmp            0      0.00%           
                        FloatCvt            0      0.00%           
                       FloatMult            0      0.00%           
                        FloatDiv            0      0.00%           
                       FloatSqrt            0      0.00%           
                         MemRead       178866     13.71%           
                        MemWrite        25651      1.97%           
                       IprAccess            0      0.00%           
                    InstPrefetch            0      0.00%           
cpu.ISSUE:IQ_0:fu_full.end_dist
cpu.ISSUE:MSIPC                              0.291959                       # Misspec issue rate
cpu.ISSUE:MSIPC_0                            0.054545                       # Misspec issue rate
cpu.ISSUE:MSIPC_1                            0.056675                       # Misspec issue rate
cpu.ISSUE:MSIPC_2                            0.108560                       # Misspec issue rate
cpu.ISSUE:MSIPC_3                            0.072179                       # Misspec issue rate
cpu.ISSUE:addr_loads                             3730                       # number of invalid-address loads
cpu.ISSUE:addr_loads_0                            772                       # number of invalid-address loads
cpu.ISSUE:addr_loads_1                            743                       # number of invalid-address loads
cpu.ISSUE:addr_loads_2                           1324                       # number of invalid-address loads
cpu.ISSUE:addr_loads_3                            891                       # number of invalid-address loads
cpu.ISSUE:addr_swpfs                               14                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_0                              0                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_1                              2                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_2                              2                       # number of invalid-address SW prefetches
cpu.ISSUE:addr_swpfs_3                             10                       # number of invalid-address SW prefetches
cpu.ISSUE:branches                             665596                       # Number of branches issued
cpu.ISSUE:branches_0                           157610                       # Number of branches issued
cpu.ISSUE:branches_1                           158010                       # Number of branches issued
cpu.ISSUE:branches_2                           185796                       # Number of branches issued
cpu.ISSUE:branches_3                           164180                       # Number of branches issued
cpu.ISSUE:count                               4220394                       # number of insts issued
cpu.ISSUE:count_0                              992316                       # number of insts issued
cpu.ISSUE:count_1                              995623                       # number of insts issued
cpu.ISSUE:count_2                             1192858                       # number of insts issued
cpu.ISSUE:count_3                             1039597                       # number of insts issued
cpu.ISSUE:fu_busy_cnt                         1304585                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_0                        300703                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_1                        299781                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_2                        384716                       # FU busy when requested
cpu.ISSUE:fu_busy_cnt_3                        319385                       # FU busy when requested
cpu.ISSUE:fu_busy_rate                       0.309115                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_0                     0.303031                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_1                     0.301099                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_2                     0.322516                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_busy_rate_3                     0.307220                       # FU busy rate (busy events/executed inst)
cpu.ISSUE:fu_full.start_dist
                          (null)            0      0.00%            # attempts to use FU when none available
                          IntAlu      1099856     84.31%            # attempts to use FU when none available
                         IntMult          212      0.02%            # attempts to use FU when none available
                          IntDiv            0      0.00%            # attempts to use FU when none available
                        FloatAdd            0      0.00%            # attempts to use FU when none available
                        FloatCmp            0      0.00%            # attempts to use FU when none available
                        FloatCvt            0      0.00%            # attempts to use FU when none available
                       FloatMult            0      0.00%            # attempts to use FU when none available
                        FloatDiv            0      0.00%            # attempts to use FU when none available
                       FloatSqrt            0      0.00%            # attempts to use FU when none available
                         MemRead       178866     13.71%            # attempts to use FU when none available
                        MemWrite        25651      1.97%            # attempts to use FU when none available
                       IprAccess            0      0.00%            # attempts to use FU when none available
                    InstPrefetch            0      0.00%            # attempts to use FU when none available
cpu.ISSUE:fu_full.end_dist
cpu.ISSUE:issued_per_cycle                    1325488                       # Number of insts issued each cycle
cpu.ISSUE:issued_per_cycle.start_dist
                               0        82291      6.21%            # Number of insts issued each cycle
                               1       197244     14.88%            # Number of insts issued each cycle
                               2       152204     11.48%            # Number of insts issued each cycle
                               3       131382      9.91%            # Number of insts issued each cycle
                               4       115915      8.75%            # Number of insts issued each cycle
                               5       100096      7.55%            # Number of insts issued each cycle
                               6       182433     13.76%            # Number of insts issued each cycle
                               7       131220      9.90%            # Number of insts issued each cycle
                               8       232703     17.56%            # Number of insts issued each cycle
cpu.ISSUE:issued_per_cycle.end_dist
cpu.ISSUE:loads                               1035779                       # number of load insts issued
cpu.ISSUE:loads_0                              241411                       # number of load insts issued
cpu.ISSUE:loads_1                              242639                       # number of load insts issued
cpu.ISSUE:loads_2                              297152                       # number of load insts issued
cpu.ISSUE:loads_3                              254577                       # number of load insts issued
cpu.ISSUE:lsq_inv_rate                              0                       # Early LSQ issues per cycle
cpu.ISSUE:lsq_invert                                0                       # Number of times LSQ instruction issued early
cpu.ISSUE:misspec_cnt                          518668                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_0                         96900                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_1                        100684                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_2                        192857                       # Number of misspeculated insts issued
cpu.ISSUE:misspec_cnt_3                        128227                       # Number of misspeculated insts issued
cpu.ISSUE:nop                                  491561                       # number of nop insts issued
cpu.ISSUE:nop_0                                108196                       # number of nop insts issued
cpu.ISSUE:nop_1                                108369                       # number of nop insts issued
cpu.ISSUE:nop_2                                152539                       # number of nop insts issued
cpu.ISSUE:nop_3                                122457                       # number of nop insts issued
cpu.ISSUE:op_count                            5734700                       # number of insts issued
cpu.ISSUE:op_count_0                          1348678                       # number of insts issued
cpu.ISSUE:op_count_1                          1352956                       # number of insts issued
cpu.ISSUE:op_count_2                          1620324                       # number of insts issued
cpu.ISSUE:op_count_3                          1412742                       # number of insts issued
cpu.ISSUE:op_rate                            3.228076                       # Operation issue rate
cpu.ISSUE:op_rate_0                          0.759174                       # Operation issue rate
cpu.ISSUE:op_rate_1                          0.761582                       # Operation issue rate
cpu.ISSUE:op_rate_2                          0.912084                       # Operation issue rate
cpu.ISSUE:op_rate_3                          0.795236                       # Operation issue rate
cpu.ISSUE:rate                               2.375670                       # Inst issue rate
cpu.ISSUE:rate_0                             0.558577                       # Inst issue rate
cpu.ISSUE:rate_1                             0.560439                       # Inst issue rate
cpu.ISSUE:rate_2                             0.671463                       # Inst issue rate
cpu.ISSUE:rate_3                             0.585192                       # Inst issue rate
cpu.ISSUE:refs                                1545852                       # number of memory reference insts issued
cpu.ISSUE:refs_0                               361300                       # number of memory reference insts issued
cpu.ISSUE:refs_1                               362906                       # number of memory reference insts issued
cpu.ISSUE:refs_2                               440584                       # number of memory reference insts issued
cpu.ISSUE:refs_3                               381062                       # number of memory reference insts issued
cpu.ISSUE:stores                               510073                       # Number of stores issued
cpu.ISSUE:stores_0                             119889                       # Number of stores issued
cpu.ISSUE:stores_1                             120267                       # Number of stores issued
cpu.ISSUE:stores_2                             143432                       # Number of stores issued
cpu.ISSUE:stores_3                             126485                       # Number of stores issued
cpu.ISSUE:swp                                    8905                       # number of swp insts issued
cpu.ISSUE:swp_0                                  2115                       # number of swp insts issued
cpu.ISSUE:swp_1                                  2105                       # number of swp insts issued
cpu.ISSUE:swp_2                                  2443                       # number of swp insts issued
cpu.ISSUE:swp_3                                  2242                       # number of swp insts issued
cpu.ISSUE:unissued_cause.start_dist
                          (null)            0      0.00%            # Reason ready instruction not issued
                          IntAlu      1099856     82.27%            # Reason ready instruction not issued
                         IntMult          212      0.02%            # Reason ready instruction not issued
                          IntDiv            0      0.00%            # Reason ready instruction not issued
                        FloatAdd            0      0.00%            # Reason ready instruction not issued
                        FloatCmp            0      0.00%            # Reason ready instruction not issued
                        FloatCvt            0      0.00%            # Reason ready instruction not issued
                       FloatMult            0      0.00%            # Reason ready instruction not issued
                        FloatDiv            0      0.00%            # Reason ready instruction not issued
                       FloatSqrt            0      0.00%            # Reason ready instruction not issued
                         MemRead       178866     13.38%            # Reason ready instruction not issued
                        MemWrite            0      0.00%            # Reason ready instruction not issued
                       IprAccess            0      0.00%            # Reason ready instruction not issued
                    InstPrefetch            0      0.00%            # Reason ready instruction not issued
                  DCache_Blocked        57924      4.33%            # Reason ready instruction not issued
                       Too_Young            0      0.00%            # Reason ready instruction not issued
cpu.ISSUE:unissued_cause.end_dist
cpu.LSQ:RQ:rdy_inst                           3049857                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_0                          735416                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_1                          742363                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_2                          830447                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_3                          741631                       # Number of ready instructions (cum)
cpu.LSQ:RQ:rdy_inst_dist_0_mean              0.413967                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_0_stdev             1.642867                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_0_TOT      1776507                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_1_mean              0.417878                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_1_stdev             1.682513                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_1_TOT      1776507                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_2_mean              0.467461                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_2_stdev             1.759726                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_2_TOT      1776507                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_3_mean              0.417466                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_inst_dist_3_stdev             1.599773                       # standard deviation of ready rate
**Ignore: cpu.LSQ:RQ:rdy_inst_dist_3_TOT      1776507                       # standard deviation of ready rate
cpu.LSQ:RQ:rdy_rate                          1.716772                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_0                        0.413967                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_1                        0.417878                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_2                        0.467461                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_rate_3                        0.417466                       # Number of ready insts per cycle
cpu.LSQ:RQ:rdy_x_count                        1507341                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_0                       354635                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_1                       355608                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_2                       425756                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_count_3                       371342                       # number of insts that become ready (cum)
cpu.LSQ:RQ:rdy_x_max                               27                       # largest number of insts that become ready
cpu.LSQ:RQ:rdy_x_rate                        0.848486                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_0                      0.199625                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_1                      0.200173                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_2                      0.239659                       # number of insts that become ready per cycle
cpu.LSQ:RQ:rdy_x_rate_3                      0.209029                       # number of insts that become ready per cycle
cpu.LSQ:avg_residency                        3.314533                       # Average IQ residency
cpu.LSQ:avg_residency_0                      3.255573                       # Average IQ residency
cpu.LSQ:avg_residency_1                      3.270171                       # Average IQ residency
cpu.LSQ:avg_residency_2                      3.377254                       # Average IQ residency
cpu.LSQ:avg_residency_3                      3.341329                       # Average IQ residency
cpu.LSQ:blocked_loads                          667453                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_0                        139928                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_1                        137471                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_2                        225304                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:blocked_loads_3                        164750                       # number of ready loads not issued due to memory disambiguation
cpu.LSQ:cum_num_insts                        13988634                       # Total occupancy
cpu.LSQ:cum_num_insts_0                       3230557                       # Total occupancy
cpu.LSQ:cum_num_insts_1                       3255857                       # Total occupancy
cpu.LSQ:cum_num_insts_2                       4028584                       # Total occupancy
cpu.LSQ:cum_num_insts_3                       3473636                       # Total occupancy
cpu.LSQ:current_count                              15                       # Occupancy this cycle
cpu.LSQ:empty_count                            373386                       # Number of empty cycles
cpu.LSQ:empty_rate                          21.017986                       # Fraction of cycles empty
cpu.LSQ:forw_loads                                354                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_0                               66                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_1                               65                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_2                              134                       # number of loads forwarded via LSQ
cpu.LSQ:forw_loads_3                               89                       # number of loads forwarded via LSQ
cpu.LSQ:full_count                                  0                       # Number of full cycles
cpu.LSQ:full_rate                                   0                       # Fraction of cycles full
cpu.LSQ:occ_dist_0.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_0.samples                    1776507                      
cpu.LSQ:occ_dist_0.min_value                        0                      
                               0      1251364              7043.96%
                               2       174498              8026.21%
                               4       178702              9032.13%
                               6        60172              9370.84%
                               8        36071              9573.88%
                              10        22385              9699.89%
                              12        15261              9785.79%
                              14        10927              9847.30%
                              16         7091              9887.22%
                              18         5587              9918.67%
                              20         5376              9948.93%
                              22         3182              9966.84%
                              24         2625              9981.62%
                              26         1522              9990.18%
                              28         1082              9996.27%
                              30          468              9998.91%
                              32          194             10000.00%
cpu.LSQ:occ_dist_0.max_value                       32                      
cpu.LSQ:occ_dist_0.end_dist

cpu.LSQ:occ_dist_1.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_1.samples                    1776507                      
cpu.LSQ:occ_dist_1.min_value                        0                      
                               0      1250197              7037.39%
                               2       171961              8005.36%
                               4       181916              9029.37%
                               6        59166              9362.42%
                               8        37732              9574.81%
                              10        22187              9699.70%
                              12        14823              9783.14%
                              14        11134              9845.82%
                              16         6935              9884.85%
                              18         6172              9919.60%
                              20         4274              9943.65%
                              22         3720              9964.59%
                              24         2452              9978.40%
                              26         1506              9986.87%
                              28          871              9991.78%
                              30          946              9997.10%
                              32          515             10000.00%
cpu.LSQ:occ_dist_1.max_value                       32                      
cpu.LSQ:occ_dist_1.end_dist

cpu.LSQ:occ_dist_2.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_2.samples                    1776507                      
cpu.LSQ:occ_dist_2.min_value                        0                      
                               0      1192817              6714.40%
                               2       169650              7669.36%
                               4       186335              8718.24%
                               6        68714              9105.04%
                               8        43672              9350.87%
                              10        30751              9523.96%
                              12        21388              9644.36%
                              14        16252              9735.84%
                              16        11379              9799.89%
                              18         9080              9851.01%
                              20         8135              9896.80%
                              22         6386              9932.74%
                              24         4887              9960.25%
                              26         3099              9977.70%
                              28         2059              9989.29%
                              30         1105              9995.51%
                              32          798             10000.00%
cpu.LSQ:occ_dist_2.max_value                       32                      
cpu.LSQ:occ_dist_2.end_dist

cpu.LSQ:occ_dist_3.start_dist                                  # IQ Occupancy per cycle
cpu.LSQ:occ_dist_3.samples                    1776507                      
cpu.LSQ:occ_dist_3.min_value                        0                      
                               0      1237526              6966.06%
                               2       171220              7929.86%
                               4       178475              8934.50%
                               6        61803              9282.40%
                               8        38332              9498.17%
                              10        24850              9638.05%
                              12        17178              9734.74%
                              14        13765              9812.23%
                              16         8766              9861.57%
                              18         7185              9902.02%
                              20         6277              9937.35%
                              22         3553              9957.35%
                              24         2732              9972.73%
                              26         2011              9984.05%
                              28         1357              9991.69%
                              30          802              9996.20%
                              32          675             10000.00%
cpu.LSQ:occ_dist_3.max_value                       32                      
cpu.LSQ:occ_dist_3.end_dist

cpu.LSQ:occ_rate                             7.874235                       # Average occupancy
cpu.LSQ:occ_rate_0                           1.818488                       # Average occupancy
cpu.LSQ:occ_rate_1                           1.832730                       # Average occupancy
cpu.LSQ:occ_rate_2                           2.267699                       # Average occupancy
cpu.LSQ:occ_rate_3                           1.955318                       # Average occupancy
cpu.LSQ:peak_occupancy                            128                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_0                           32                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_1                           32                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_2                           32                       # Peak IQ occupancy
cpu.LSQ:peak_occupancy_3                           32                       # Peak IQ occupancy
cpu.REG:fp:full                                     0                       # number of cycles where there were no FP registers
cpu.REG:fp:occ                                  90741                       # Cumulative count of FP register usage
cpu.REG:fp:occ_0                                20453                       # Cumulative count of FP register usage
cpu.REG:fp:occ_1                                21374                       # Cumulative count of FP register usage
cpu.REG:fp:occ_2                                26985                       # Cumulative count of FP register usage
cpu.REG:fp:occ_3                                21929                       # Cumulative count of FP register usage
cpu.REG:fp:occ_rate                                 0                       # Average FP register usage
cpu.REG:fp:occ_rate_0                               0                       # Average FP register usage
cpu.REG:fp:occ_rate_1                               0                       # Average FP register usage
cpu.REG:fp:occ_rate_2                               0                       # Average FP register usage
cpu.REG:fp:occ_rate_3                               0                       # Average FP register usage
cpu.REG:int:full                                    0                       # number of cycles where there were no INT registers
cpu.REG:int:occ                              66610724                       # Cumulative count of INT register usage
cpu.REG:int:occ_0                            15382927                       # Cumulative count of INT register usage
cpu.REG:int:occ_1                            15416242                       # Cumulative count of INT register usage
cpu.REG:int:occ_2                            19302185                       # Cumulative count of INT register usage
cpu.REG:int:occ_3                            16509370                       # Cumulative count of INT register usage
cpu.REG:int:occ_rate                               37                       # Average INT register usage
cpu.REG:int:occ_rate_0                              9                       # Average INT register usage
cpu.REG:int:occ_rate_1                              9                       # Average INT register usage
cpu.REG:int:occ_rate_2                             11                       # Average INT register usage
cpu.REG:int:occ_rate_3                              9                       # Average INT register usage
cpu.ROB:cap_events                                  0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_0                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_1                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_2                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_events_3                                0                       # number of cycles where ROB cap was active
cpu.ROB:cap_inst                                    0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_0                                  0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_1                                  0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_2                                  0                       # number of instructions held up by ROB cap
cpu.ROB:cap_inst_3                                  0                       # number of instructions held up by ROB cap
cpu.ROB:current_count                              89                       # Current ROB occupancy
cpu.ROB:full_count                              31341                       # number of cycles where ROB was full
cpu.ROB:full_rate                            0.017642                       # ROB full per cycle
cpu.ROB:occ_dist_0.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_0.samples                    1776507                      
cpu.ROB:occ_dist_0.min_value                        0                      
                               0       682540              3842.03%
                               2       147680              4673.33%
                               4       131487              5413.47%
                               6       114254              6056.61%
                               8       110157              6676.69%
                              10        71461              7078.94%
                              12        56442              7396.66%
                              14        43778              7643.08%
                              16        39192              7863.70%
                              18        22981              7993.06%
                              20        64367              8355.38%
                              22        21402              8475.85%
                              24        49104              8752.26%
                              26        16536              8845.34%
                              28        15235              8931.10%
                              30        13355              9006.27%
                              32        10151              9063.41%
                              34        11701              9129.28%
                              36        10241              9186.93%
                              38         9317              9239.37%
                              40         8756              9288.66%
                              42         8954              9339.06%
                              44         8421              9386.46%
                              46         6126              9420.95%
                              48         7078              9460.79%
                              50         6449              9497.09%
                              52         6046              9531.12%
                              54         5155              9560.14%
                              56         4295              9584.32%
                              58         4564              9610.01%
                              60         4053              9632.82%
                              62         3818              9654.32%
                              64         4050              9677.11%
                              66         3444              9696.50%
                              68         3273              9714.92%
                              70         2837              9730.89%
                              72         2871              9747.05%
                              74         2753              9762.55%
                              76         2695              9777.72%
                              78         2174              9789.96%
                              80         2494              9804.00%
                              82         2088              9815.75%
                              84         2074              9827.43%
                              86         1248              9834.45%
                              88         1704              9844.04%
                              90         2112              9855.93%
                              92         1560              9864.71%
                              94         1662              9874.07%
                              96         1372              9881.79%
                              98         1594              9890.76%
                             100          887              9895.76%
                             102         1075              9901.81%
                             104          871              9906.71%
                             106         1043              9912.58%
                             108         1012              9918.28%
                             110          818              9922.88%
                             112          752              9927.12%
                             114          759              9931.39%
                             116          451              9933.93%
                             118          553              9937.04%
                             120          526              9940.00%
                             122          591              9943.33%
                             124          485              9946.06%
                             126          534              9949.06%
                             128          410              9951.37%
                             130          413              9953.70%
                             132          306              9955.42%
                             134          317              9957.20%
                             136          332              9959.07%
                             138          232              9960.38%
                             140          256              9961.82%
                             142          461              9964.41%
                             144          261              9965.88%
                             146          240              9967.23%
                             148          341              9969.15%
                             150          246              9970.54%
                             152          304              9972.25%
                             154          398              9974.49%
                             156          154              9975.36%
                             158          251              9976.77%
                             160          137              9977.54%
                             162          229              9978.83%
                             164          249              9980.23%
                             166          282              9981.82%
                             168          201              9982.95%
                             170          162              9983.86%
                             172          275              9985.41%
                             174          259              9986.87%
                             176          228              9988.15%
                             178          172              9989.12%
                             180          264              9990.61%
                             182          195              9991.70%
                             184          123              9992.40%
                             186          180              9993.41%
                             188          130              9994.14%
                             190           71              9994.54%
                             192          544              9997.60%
                             194           25              9997.74%
                             196          401             10000.00%
cpu.ROB:occ_dist_0.max_value                      196                      
cpu.ROB:occ_dist_0.end_dist

cpu.ROB:occ_dist_1.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_1.samples                    1776507                      
cpu.ROB:occ_dist_1.min_value                        0                      
                               0       680815              3832.32%
                               2       146414              4656.49%
                               4       131909              5399.01%
                               6       114422              6043.09%
                               8       110505              6665.13%
                              10        71518              7067.71%
                              12        55506              7380.15%
                              14        44684              7631.68%
                              16        39973              7856.69%
                              18        22939              7985.81%
                              20        65400              8353.95%
                              22        20920              8471.71%
                              24        49331              8749.39%
                              26        16651              8843.12%
                              28        15368              8929.63%
                              30        14302              9010.14%
                              32        11279              9073.63%
                              34        11058              9135.87%
                              36         9884              9191.51%
                              38         9490              9244.93%
                              40         9548              9298.67%
                              42         8462              9346.31%
                              44         8206              9392.50%
                              46         6382              9428.42%
                              48         6219              9463.43%
                              50         6963              9502.63%
                              52         5851              9535.56%
                              54         4401              9560.33%
                              56         4653              9586.53%
                              58         5034              9614.86%
                              60         4228              9638.66%
                              62         3861              9660.40%
                              64         3914              9682.43%
                              66         3612              9702.76%
                              68         2646              9717.65%
                              70         2723              9732.98%
                              72         2526              9747.20%
                              74         2463              9761.06%
                              76         2736              9776.47%
                              78         2300              9789.41%
                              80         1740              9799.21%
                              82         1986              9810.39%
                              84         1959              9821.41%
                              86         1811              9831.61%
                              88         1595              9840.59%
                              90         1341              9848.13%
                              92         1237              9855.10%
                              94         1224              9861.99%
                              96         1467              9870.25%
                              98         1284              9877.47%
                             100         1191              9884.18%
                             102         1041              9890.04%
                             104         1202              9896.80%
                             106          911              9901.93%
                             108          845              9906.69%
                             110         1114              9912.96%
                             112          658              9916.66%
                             114          850              9921.45%
                             116          689              9925.33%
                             118          683              9929.17%
                             120          595              9932.52%
                             122          624              9936.03%
                             124          569              9939.23%
                             126          548              9942.32%
                             128          949              9947.66%
                             130          677              9951.47%
                             132          533              9954.47%
                             134          652              9958.14%
                             136          482              9960.86%
                             138          437              9963.32%
                             140          411              9965.63%
                             142          541              9968.67%
                             144          233              9969.99%
                             146          347              9971.94%
                             148          386              9974.11%
                             150          240              9975.46%
                             152          356              9977.47%
                             154          337              9979.36%
                             156          191              9980.44%
                             158          263              9981.92%
                             160          276              9983.47%
                             162          410              9985.78%
                             164          110              9986.40%
                             166          170              9987.36%
                             168          262              9988.83%
                             170          120              9989.51%
                             172          201              9990.64%
                             174          219              9991.87%
                             176           98              9992.42%
                             178          108              9993.03%
                             180           44              9993.28%
                             182          152              9994.13%
                             184          280              9995.71%
                             186           56              9996.03%
                             188          185              9997.07%
                             190          143              9997.87%
                             192          116              9998.53%
                             194          168              9999.47%
                             196           94             10000.00%
cpu.ROB:occ_dist_1.max_value                      196                      
cpu.ROB:occ_dist_1.end_dist

cpu.ROB:occ_dist_2.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_2.samples                    1776507                      
cpu.ROB:occ_dist_2.min_value                        0                      
                               0       678611              3819.92%
                               2       123534              4515.29%
                               4       112253              5147.17%
                               6       100681              5713.90%
                               8        98513              6268.44%
                              10        62297              6619.11%
                              12        51897              6911.24%
                              14        41606              7145.44%
                              16        39648              7368.62%
                              18        25186              7510.39%
                              20        68361              7895.20%
                              22        23982              8030.19%
                              24        51320              8319.07%
                              26        21369              8439.36%
                              28        18154              8541.55%
                              30        16560              8634.76%
                              32        14348              8715.53%
                              34        13057              8789.03%
                              36        12524              8859.53%
                              38        11807              8925.99%
                              40        10941              8987.58%
                              42        10571              9047.08%
                              44        10663              9107.10%
                              46         9477              9160.45%
                              48         8026              9205.63%
                              50         8847              9255.43%
                              52         7656              9298.52%
                              54         6564              9335.47%
                              56         6461              9371.84%
                              58         6017              9405.71%
                              60         5720              9437.91%
                              62         4927              9465.64%
                              64         5089              9494.29%
                              66         5085              9522.91%
                              68         4223              9546.68%
                              70         3709              9567.56%
                              72         3931              9589.69%
                              74         4475              9614.88%
                              76         4385              9639.56%
                              78         2833              9655.51%
                              80         2678              9670.58%
                              82         3266              9688.97%
                              84         2774              9704.58%
                              86         2279              9717.41%
                              88         2236              9730.00%
                              90         2417              9743.60%
                              92         2003              9754.88%
                              94         1936              9765.78%
                              96         2338              9778.94%
                              98         1927              9789.78%
                             100         1536              9798.43%
                             102         1859              9808.89%
                             104         2212              9821.35%
                             106         1409              9829.28%
                             108         1653              9838.58%
                             110         1428              9846.62%
                             112         1121              9852.93%
                             114         1282              9860.15%
                             116         1053              9866.07%
                             118         1182              9872.73%
                             120         1127              9879.07%
                             122          922              9884.26%
                             124          915              9889.41%
                             126          818              9894.02%
                             128          969              9899.47%
                             130         1027              9905.25%
                             132          772              9909.60%
                             134          886              9914.59%
                             136          804              9919.11%
                             138          610              9922.54%
                             140          509              9925.41%
                             142          637              9929.00%
                             144          806              9933.53%
                             146          582              9936.81%
                             148          628              9940.34%
                             150          547              9943.42%
                             152          440              9945.90%
                             154          527              9948.87%
                             156          568              9952.06%
                             158          593              9955.40%
                             160          360              9957.43%
                             162          301              9959.12%
                             164          314              9960.89%
                             166          318              9962.68%
                             168          375              9964.79%
                             170          292              9966.43%
                             172          256              9967.88%
                             174          204              9969.02%
                             176          252              9970.44%
                             178          348              9972.40%
                             180          468              9975.04%
                             182          687              9978.90%
                             184          387              9981.08%
                             186          560              9984.23%
                             188          569              9987.44%
                             190          626              9990.96%
                             192          731              9995.07%
                             194          545              9998.14%
                             196          330             10000.00%
cpu.ROB:occ_dist_2.max_value                      196                      
cpu.ROB:occ_dist_2.end_dist

cpu.ROB:occ_dist_3.start_dist                                  # ROB Occupancy per cycle
cpu.ROB:occ_dist_3.samples                    1776507                      
cpu.ROB:occ_dist_3.min_value                        0                      
                               0       680550              3830.83%
                               2       140715              4622.92%
                               4       129968              5354.51%
                               6       111859              5984.17%
                               8       108734              6596.24%
                              10        68538              6982.04%
                              12        55652              7295.30%
                              14        43304              7539.06%
                              16        39579              7761.86%
                              18        23316              7893.10%
                              20        65170              8259.94%
                              22        20789              8376.97%
                              24        47475              8644.20%
                              26        17962              8745.31%
                              28        15211              8830.94%
                              30        13220              8905.35%
                              32        11871              8972.17%
                              34        11052              9034.39%
                              36        10699              9094.61%
                              38         9270              9146.79%
                              40         9356              9199.46%
                              42         9123              9250.81%
                              44         8703              9299.80%
                              46         6754              9337.82%
                              48         7033              9377.41%
                              50         7391              9419.01%
                              52         6319              9454.58%
                              54         5496              9485.52%
                              56         5345              9515.61%
                              58         4566              9541.31%
                              60         4613              9567.27%
                              62         4239              9591.14%
                              64         4777              9618.03%
                              66         4164              9641.46%
                              68         3771              9662.69%
                              70         3632              9683.14%
                              72         3166              9700.96%
                              74         3197              9718.95%
                              76         2822              9734.84%
                              78         2397              9748.33%
                              80         2192              9760.67%
                              82         2007              9771.97%
                              84         2107              9783.83%
                              86         2250              9796.49%
                              88         1728              9806.22%
                              90         1766              9816.16%
                              92         1462              9824.39%
                              94         1487              9832.76%
                              96         1558              9841.53%
                              98         1849              9851.94%
                             100         1016              9857.66%
                             102         1122              9863.97%
                             104         1266              9871.10%
                             106         1164              9877.65%
                             108         1078              9883.72%
                             110         1142              9890.15%
                             112          874              9895.07%
                             114          879              9900.02%
                             116         1030              9905.82%
                             118          693              9909.72%
                             120          632              9913.27%
                             122          808              9917.82%
                             124          510              9920.69%
                             126          815              9925.28%
                             128          657              9928.98%
                             130          613              9932.43%
                             132          680              9936.26%
                             134          499              9939.07%
                             136          458              9941.64%
                             138          582              9944.92%
                             140          523              9947.86%
                             142          556              9950.99%
                             144          447              9953.51%
                             146          533              9956.51%
                             148          486              9959.25%
                             150          282              9960.83%
                             152          384              9962.99%
                             154          516              9965.90%
                             156          278              9967.46%
                             158          184              9968.50%
                             160          273              9970.04%
                             162          216              9971.25%
                             164          200              9972.38%
                             166          347              9974.33%
                             168          374              9976.44%
                             170          335              9978.32%
                             172          196              9979.43%
                             174          284              9981.02%
                             176          135              9981.78%
                             178          237              9983.12%
                             180          262              9984.59%
                             182          237              9985.93%
                             184          361              9987.96%
                             186          445              9990.46%
                             188          306              9992.19%
                             190          292              9993.83%
                             192          275              9995.38%
                             194          235              9996.70%
                             196          586             10000.00%
cpu.ROB:occ_dist_3.max_value                      196                      
cpu.ROB:occ_dist_3.end_dist

cpu.ROB:occ_rate                            51.408561                       # ROB occupancy rate
cpu.ROB:occ_rate_0                          11.907476                       # ROB occupancy rate
cpu.ROB:occ_rate_1                          11.929540                       # ROB occupancy rate
cpu.ROB:occ_rate_2                          14.820917                       # ROB occupancy rate
cpu.ROB:occ_rate_3                          12.750629                       # ROB occupancy rate
cpu.ROB:occupancy                            91327669                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_0                          21153715                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_1                          21192911                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_2                          26329462                       # cpu.ROB occupancy (cumulative)
cpu.ROB:occupancy_3                          22651581                       # cpu.ROB occupancy (cumulative)
cpu.SB:RQ:rdy_inst                            1056732                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_0                           264472                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_1                           249441                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_2                           277368                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_3                           265451                       # Number of ready instructions (cum)
cpu.SB:RQ:rdy_inst_dist_0_mean               0.148872                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_0_stdev              1.032012                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_0_TOT       1776507                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_1_mean               0.140411                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_1_stdev              0.981063                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_1_TOT       1776507                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_2_mean               0.156131                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_2_stdev              1.050226                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_2_TOT       1776507                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_3_mean               0.149423                       # standard deviation of ready rate
cpu.SB:RQ:rdy_inst_dist_3_stdev              1.055132                       # standard deviation of ready rate
**Ignore: cpu.SB:RQ:rdy_inst_dist_3_TOT       1776507                       # standard deviation of ready rate
cpu.SB:RQ:rdy_rate                           0.594837                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_0                         0.148872                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_1                         0.140411                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_2                         0.156131                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_rate_3                         0.149423                       # Number of ready insts per cycle
cpu.SB:RQ:rdy_x_count                          449981                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_0                        109091                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_1                        109049                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_2                        120828                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_count_3                        111013                       # number of insts that become ready (cum)
cpu.SB:RQ:rdy_x_max                                 8                       # largest number of insts that become ready
cpu.SB:RQ:rdy_x_rate                         0.253295                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_0                       0.061408                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_1                       0.061384                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_2                       0.068014                       # number of insts that become ready per cycle
cpu.SB:RQ:rdy_x_rate_3                       0.062489                       # number of insts that become ready per cycle
cpu.SB:full_count                               30378                       # store buffer full events (cumulative)
cpu.SB:full_rate                             0.017100                       # store buffer full rate
cpu.SB:occ_rate                              2.680573                       # store buffer occupancy rate
cpu.SB:occ_rate_0                            0.665449                       # store buffer occupancy rate
cpu.SB:occ_rate_1                            0.654521                       # store buffer occupancy rate
cpu.SB:occ_rate_2                            0.692360                       # store buffer occupancy rate
cpu.SB:occ_rate_3                            0.668243                       # store buffer occupancy rate
cpu.SB:occupancy                              4762057                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_0                            1182175                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_1                            1162761                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_2                            1229982                       # store buffer occupancy (cumulative)
cpu.SB:occupancy_3                            1187139                       # store buffer occupancy (cumulative)
cpu.SB:write_barrier_pending_cycles_0               0                       # number of cycles write barriers were pending
cpu.SB:write_barrier_pending_cycles_1               0                       # number of cycles write barriers were pending
cpu.SB:write_barrier_pending_cycles_2               0                       # number of cycles write barriers were pending
cpu.SB:write_barrier_pending_cycles_3               0                       # number of cycles write barriers were pending
cpu.SB:write_barriers                               0                       # number of write barrier operations
cpu.SB:write_barriers_0                             0                       # number of write barrier operations
cpu.SB:write_barriers_1                             0                       # number of write barrier operations
cpu.SB:write_barriers_2                             0                       # number of write barrier operations
cpu.SB:write_barriers_3                             0                       # number of write barrier operations
cpu.WB:consumers                              4321349                       # num instructions consuming a value
cpu.WB:consumers_0                            1001563                       # num instructions consuming a value
cpu.WB:consumers_1                            1004081                       # num instructions consuming a value
cpu.WB:consumers_2                            1254707                       # num instructions consuming a value
cpu.WB:consumers_3                            1060998                       # num instructions consuming a value
cpu.WB:count                                  5646386                       # cumulative count of insts written-back
cpu.WB:count_0                                1332693                       # cumulative count of insts written-back
cpu.WB:count_1                                1336226                       # cumulative count of insts written-back
cpu.WB:count_2                                1586622                       # cumulative count of insts written-back
cpu.WB:count_3                                1390845                       # cumulative count of insts written-back
cpu.WB:fanout                                1.054120                       # average fanout of values written-back
cpu.WB:fanout_0                              1.071680                       # average fanout of values written-back
cpu.WB:fanout_1                              1.072165                       # average fanout of values written-back
cpu.WB:fanout_2                              1.023340                       # average fanout of values written-back
cpu.WB:fanout_3                              1.056867                       # average fanout of values written-back
cpu.WB:penalized                                    0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_0                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_1                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_2                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_3                                  0                       # number of instrctions required to write to 'other' IQ
cpu.WB:penalized_rate                               0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_0                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_1                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_2                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:penalized_rate_3                             0                       # fraction of instructions written-back that wrote to 'other' IQ
cpu.WB:pred_error.start_dist                                   # error in predicted writeback times
cpu.WB:pred_error.samples                     5646386                      
cpu.WB:pred_error.min_value                       147                      
                             -10            0      0.00%      0.00%
                              -9            0      0.00%      0.00%
                              -8            0      0.00%      0.00%
                              -7            0      0.00%      0.00%
                              -6            0      0.00%      0.00%
                              -5            0      0.00%      0.00%
                              -4            0      0.00%      0.00%
                              -3            0      0.00%      0.00%
                              -2            0      0.00%      0.00%
                              -1            0      0.00%      0.00%
                               0            0      0.00%      0.00%
                               1            0      0.00%      0.00%
                               2            0      0.00%      0.00%
                               3            0      0.00%      0.00%
                               4            0      0.00%      0.00%
                               5            0      0.00%      0.00%
                               6            0      0.00%      0.00%
                               7            0      0.00%      0.00%
                               8            0      0.00%      0.00%
                               9            0      0.00%      0.00%
                              10            0      0.00%      0.00%
                              11            0      0.00%      0.00%
                              12            0      0.00%      0.00%
                              13            0      0.00%      0.00%
                              14            0      0.00%      0.00%
                              15            0      0.00%      0.00%
                              16            0      0.00%      0.00%
                              17            0      0.00%      0.00%
                              18            0      0.00%      0.00%
                              19            0      0.00%      0.00%
                              20            0      0.00%      0.00%
                              21            0      0.00%      0.00%
                              22            0      0.00%      0.00%
                              23            0      0.00%      0.00%
                              24            0      0.00%      0.00%
                              25            0      0.00%      0.00%
                              26            0      0.00%      0.00%
                              27            0      0.00%      0.00%
                              28            0      0.00%      0.00%
                              29            0      0.00%      0.00%
                              30            0      0.00%      0.00%
                              31            0      0.00%      0.00%
                              32            0      0.00%      0.00%
                              33            0      0.00%      0.00%
                              34            0      0.00%      0.00%
                              35            0      0.00%      0.00%
                              36            0      0.00%      0.00%
                              37            0      0.00%      0.00%
                              38            0      0.00%      0.00%
                              39            0      0.00%      0.00%
                              40            0      0.00%      0.00%
                              41            0      0.00%      0.00%
                              42            0      0.00%      0.00%
                              43            0      0.00%      0.00%
                              44            0      0.00%      0.00%
                              45            0      0.00%      0.00%
                              46            0      0.00%      0.00%
                              47            0      0.00%      0.00%
                              48            0      0.00%      0.00%
                              49            0      0.00%      0.00%
                              50            0      0.00%      0.00%
                              51            0      0.00%      0.00%
                              52            0      0.00%      0.00%
                              53            0      0.00%      0.00%
                              54            0      0.00%      0.00%
                              55            0      0.00%      0.00%
                              56            0      0.00%      0.00%
                              57            0      0.00%      0.00%
                              58            0      0.00%      0.00%
                              59            0      0.00%      0.00%
                              60            0      0.00%      0.00%
                              61            0      0.00%      0.00%
                              62            0      0.00%      0.00%
                              63            0      0.00%      0.00%
                              64            0      0.00%      0.00%
                              65            0      0.00%      0.00%
                              66            0      0.00%      0.00%
                              67            0      0.00%      0.00%
                              68            0      0.00%      0.00%
                              69            0      0.00%      0.00%
                              70            0      0.00%      0.00%
                              71            0      0.00%      0.00%
                              72            0      0.00%      0.00%
                              73            0      0.00%      0.00%
                              74            0      0.00%      0.00%
                              75            0      0.00%      0.00%
                              76            0      0.00%      0.00%
                              77            0      0.00%      0.00%
                              78            0      0.00%      0.00%
                              79            0      0.00%      0.00%
                              80            0      0.00%      0.00%
                              81            0      0.00%      0.00%
                              82            0      0.00%      0.00%
                              83            0      0.00%      0.00%
                              84            0      0.00%      0.00%
                              85            0      0.00%      0.00%
                              86            0      0.00%      0.00%
                              87            0      0.00%      0.00%
                              88            0      0.00%      0.00%
                              89            0      0.00%      0.00%
                              90            0      0.00%      0.00%
                              91            0      0.00%      0.00%
                              92            0      0.00%      0.00%
                              93            0      0.00%      0.00%
                              94            0      0.00%      0.00%
                              95            0      0.00%      0.00%
                              96            0      0.00%      0.00%
                              97            0      0.00%      0.00%
                              98            0      0.00%      0.00%
                              99            0      0.00%      0.00%
                             100            0      0.00%      0.00%
cpu.WB:pred_error.overflows                   5646386                      
cpu.WB:pred_error.max_value                   1776507                      
cpu.WB:pred_error.end_dist

cpu.WB:producers                              4555222                       # num instructions producing a value
cpu.WB:producers_0                            1073355                       # num instructions producing a value
cpu.WB:producers_1                            1076541                       # num instructions producing a value
cpu.WB:producers_2                            1283992                       # num instructions producing a value
cpu.WB:producers_3                            1121334                       # num instructions producing a value
cpu.WB:rate                                  3.178364                       # insts written-back per cycle
cpu.WB:rate_0                                0.750176                       # insts written-back per cycle
cpu.WB:rate_1                                0.752165                       # insts written-back per cycle
cpu.WB:rate_2                                0.893113                       # insts written-back per cycle
cpu.WB:rate_3                                0.782910                       # insts written-back per cycle
cpu.branch_pred.btb_accuracy                 0.983647                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_0               0.985384                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_1               0.985355                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_2               0.980205                       # fraction of BTB targets correct
cpu.branch_pred.btb_accuracy_3               0.983943                       # fraction of BTB targets correct
cpu.branch_pred.btb_correct                    323305                       # num correct BTB predictions
cpu.branch_pred.btb_correct_0                   79285                       # num correct BTB predictions
cpu.branch_pred.btb_correct_1                   79122                       # num correct BTB predictions
cpu.branch_pred.btb_correct_2                   85667                       # num correct BTB predictions
cpu.branch_pred.btb_correct_3                   79231                       # num correct BTB predictions
cpu.branch_pred.btb_hit_rate                 0.917489                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_0               0.933911                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_1               0.932160                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_2               0.901980                       # BTB hit ratio
cpu.branch_pred.btb_hit_rate_3               0.908809                       # BTB hit ratio
cpu.branch_pred.btb_hits                       506874                       # Number of BTB hits
cpu.branch_pred.btb_hits_0                     114292                       # Number of BTB hits
cpu.branch_pred.btb_hits_1                     115133                       # Number of BTB hits
cpu.branch_pred.btb_hits_2                     153333                       # Number of BTB hits
cpu.branch_pred.btb_hits_3                     124116                       # Number of BTB hits
cpu.branch_pred.btb_lookups                    552458                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_0                  122380                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_1                  123512                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_2                  169996                       # Number of BTB lookups
cpu.branch_pred.btb_lookups_3                  136570                       # Number of BTB lookups
cpu.branch_pred.cond_correct                   422600                       # num correct dir predictions
cpu.branch_pred.cond_correct_0                 103356                       # num correct dir predictions
cpu.branch_pred.cond_correct_1                 103167                       # num correct dir predictions
cpu.branch_pred.cond_correct_2                 112092                       # num correct dir predictions
cpu.branch_pred.cond_correct_3                 103985                       # num correct dir predictions
cpu.branch_pred.cond_predicted                 448550                       # num committed conditional branches
cpu.branch_pred.cond_predicted_0               108624                       # num committed conditional branches
cpu.branch_pred.cond_predicted_1               108576                       # num committed conditional branches
cpu.branch_pred.cond_predicted_2               120804                       # num committed conditional branches
cpu.branch_pred.cond_predicted_3               110546                       # num committed conditional branches
cpu.branch_pred.dir_accuracy                 0.942147                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_0               0.951502                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_1               0.950182                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_2               0.927883                       # fraction of predictions correct
cpu.branch_pred.dir_accuracy_3               0.940649                       # fraction of predictions correct
cpu.branch_pred.lookup_rate                  0.513122                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_0                0.113794                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_1                0.114739                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_2                0.157937                       # Rate of bpred lookups
cpu.branch_pred.lookup_rate_3                0.126651                       # Rate of bpred lookups
cpu.branch_pred.lookups                        911564                       # num BP lookups
cpu.branch_pred.lookups_0                      202155                       # num BP lookups
cpu.branch_pred.lookups_1                      203835                       # num BP lookups
cpu.branch_pred.lookups_2                      280577                       # num BP lookups
cpu.branch_pred.lookups_3                      224997                       # num BP lookups
cpu.branch_pred.ras_accuracy                 0.978177                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_0               0.986794                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_1               0.986793                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_2               0.964614                       # fraction of RAS targets correct
cpu.branch_pred.ras_accuracy_3               0.975495                       # fraction of RAS targets correct
cpu.branch_pred.ras_correct                     46257                       # num correct RAS predictions
cpu.branch_pred.ras_correct_0                   11433                       # num correct RAS predictions
cpu.branch_pred.ras_correct_1                   11432                       # num correct RAS predictions
cpu.branch_pred.ras_correct_2                   11967                       # num correct RAS predictions
cpu.branch_pred.ras_correct_3                   11425                       # num correct RAS predictions
cpu.branch_pred.used_btb                       328680                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_0                      80461                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_1                      80298                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_2                      87397                       # num committed branches using target from BTB
cpu.branch_pred.used_btb_3                      80524                       # num committed branches using target from BTB
cpu.branch_pred.used_ras                        47289                       # num returns predicted using RAS
cpu.branch_pred.used_ras_0                      11586                       # num returns predicted using RAS
cpu.branch_pred.used_ras_1                      11585                       # num returns predicted using RAS
cpu.branch_pred.used_ras_2                      12406                       # num returns predicted using RAS
cpu.branch_pred.used_ras_3                      11712                       # num returns predicted using RAS
cpu.dcache.advance_pool_dist.start_dist                        # Dist. of Repl. across pools
cpu.dcache.advance_pool_dist.samples           250714                      
cpu.dcache.advance_pool_dist.min_value              0                      
                               0       102848   4102.20%           
                               1        39505   1575.70%           
                               2        19076    760.87%           
                               3        11312    451.19%           
                               4         7861    313.54%           
                               5         6434    256.63%           
                               6         5972    238.20%           
                               7         6309    251.64%           
                               8         6816    271.86%           
                               9         3913    156.07%           
                              10         2655    105.90%           
                              11         2052     81.85%           
                              12         1954     77.94%           
                              13         2463     98.24%           
                              14         3584    142.95%           
                              15         7911    315.54%           
                              16        20049    799.68%           
cpu.dcache.advance_pool_dist.max_value             16                      
cpu.dcache.advance_pool_dist.end_dist

cpu.dcache.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
cpu.dcache.avg_blocked_cycles_no_targets    99.536424                       # average number of cycles each access was blocked
cpu.dcache.avg_refs                         26.434090                       # Average number of references to valid blocks.
cpu.dcache.blocked_no_mshrs                         0                       # number of cycles access was blocked
cpu.dcache.blocked_no_targets                     604                       # number of cycles access was blocked
cpu.dcache.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
cpu.dcache.blocked_cycles_no_targets            60120                       # number of cycles access was blocked
cpu.dcache.cache_copies                             0                       # number of cache copies performed
cpu.dcache.demand_accesses                    1458523                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_0                   345659                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_1                   346481                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_2                   407525                       # number of demand (read+write) accesses
cpu.dcache.demand_accesses_3                   358858                       # number of demand (read+write) accesses
cpu.dcache.demand_avg_miss_latency          55.662518                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_0        55.747470                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_1        55.816856                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_2        55.847194                       # average overall miss latency
cpu.dcache.demand_avg_miss_latency_3        55.240637                       # average overall miss latency
cpu.dcache.demand_avg_mshr_miss_latency     40.699830                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_0    40.432321                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_1    40.626081                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_2    41.391195                       # average overall mshr miss latency
cpu.dcache.demand_avg_mshr_miss_latency_3    40.344952                       # average overall mshr miss latency
cpu.dcache.demand_hits                        1366601                       # number of demand (read+write) hits
cpu.dcache.demand_hits_0                       322933                       # number of demand (read+write) hits
cpu.dcache.demand_hits_1                       323914                       # number of demand (read+write) hits
cpu.dcache.demand_hits_2                       384018                       # number of demand (read+write) hits
cpu.dcache.demand_hits_3                       335736                       # number of demand (read+write) hits
cpu.dcache.demand_miss_latency                5116610                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_0              1266917                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_1              1259619                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_2              1312800                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_latency_3              1277274                       # number of demand (read+write) miss cycles
cpu.dcache.demand_miss_rate                  0.063024                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_0                0.065747                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_1                0.065132                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_2                0.057682                       # miss rate for demand accesses
cpu.dcache.demand_miss_rate_3                0.064432                       # miss rate for demand accesses
cpu.dcache.demand_misses                        91922                       # number of demand (read+write) misses
cpu.dcache.demand_misses_0                      22726                       # number of demand (read+write) misses
cpu.dcache.demand_misses_1                      22567                       # number of demand (read+write) misses
cpu.dcache.demand_misses_2                      23507                       # number of demand (read+write) misses
cpu.dcache.demand_misses_3                      23122                       # number of demand (read+write) misses
cpu.dcache.demand_mshr_hits                     41294                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_0                   10152                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_1                   10075                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_2                   10741                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_hits_3                   10326                       # number of demand (read+write) MSHR hits
cpu.dcache.demand_mshr_miss_latency           2060551                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_0          508396                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_1          507501                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_2          528400                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_latency_3          516254                       # number of demand (read+write) MSHR miss cycles
cpu.dcache.demand_mshr_miss_rate             0.034712                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_0           0.036377                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_1           0.036054                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_2           0.031326                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_miss_rate_3           0.035658                       # mshr miss rate for demand accesses
cpu.dcache.demand_mshr_misses                   50628                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_0                 12574                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_1                 12492                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_2                 12766                       # number of demand (read+write) MSHR misses
cpu.dcache.demand_mshr_misses_3                 12796                       # number of demand (read+write) MSHR misses
cpu.dcache.demote_pool_dist.start_dist                         # Dist. of Repl. across pools
cpu.dcache.demote_pool_dist.samples           3704160                      
cpu.dcache.demote_pool_dist.min_value               0                      
                               0      3067974   8282.51%           
                               1       155304    419.27%           
                               2        91013    245.70%           
                               3        70613    190.63%           
                               4        62880    169.76%           
                               5        59447    160.49%           
                               6        58037    156.68%           
                               7        57594    155.48%           
                               8        26330     71.08%           
                               9         6797     18.35%           
                              10         3898     10.52%           
                              11         2640      7.13%           
                              12         2037      5.50%           
                              13         1940      5.24%           
                              14         2456      6.63%           
                              15         3580      9.66%           
                              16        31620     85.36%           
cpu.dcache.demote_pool_dist.max_value              16                      
cpu.dcache.demote_pool_dist.end_dist

cpu.dcache.fast_writes                            389                       # number of fast writes performed
cpu.dcache.hash_hit                           1366616                       # Total of hites in hash table
cpu.dcache.hash_miss                            93255                       # Total of misses in hash table
cpu.dcache.hit_depth_total                    1366616                       # Total of hit depths
cpu.dcache.hit_hash_depth_dist.start_dist                      # Dist. of Hash lookup depths
cpu.dcache.hit_hash_depth_dist.samples        1366616                      
cpu.dcache.hit_hash_depth_dist.min_value            1                      
                               0            0      0.00%           
                               1      1366616  10000.00%           
                               2            0      0.00%           
                               3            0      0.00%           
                               4            0      0.00%           
                               5            0      0.00%           
                               6            0      0.00%           
                               7            0      0.00%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
                              17            0      0.00%           
                              18            0      0.00%           
                              19            0      0.00%           
                              20            0      0.00%           
cpu.dcache.hit_hash_depth_dist.max_value            1                      
cpu.dcache.hit_hash_depth_dist.end_dist

cpu.dcache.miss_depth_total                    237203                       # Total of miss depths
cpu.dcache.miss_hash_depth_dist.start_dist                     # Dist. of Hash lookup depths
cpu.dcache.miss_hash_depth_dist.samples         93255                      
cpu.dcache.miss_hash_depth_dist.min_value            1                      
                               0            0      0.00%           
                               1        44135   4732.72%           
                               2        15911   1706.18%           
                               3         8972    962.09%           
                               4         7557    810.36%           
                               5         6666    714.81%           
                               6         4903    525.76%           
                               7         2094    224.55%           
                               8         1399    150.02%           
                               9          967    103.69%           
                              10          485     52.01%           
                              11           94     10.08%           
                              12           40      4.29%           
                              13           18      1.93%           
                              14           10      1.07%           
                              15            2      0.21%           
                              16            1      0.11%           
                              17            1      0.11%           
                              18            0      0.00%           
                              19            0      0.00%           
                              20            0      0.00%           
cpu.dcache.miss_hash_depth_dist.max_value           17                      
cpu.dcache.miss_hash_depth_dist.end_dist

cpu.dcache.mshr_cap_events                          0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_0                        0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_1                        0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_2                        0                       # number of times MSHR cap was activated
cpu.dcache.mshr_cap_events_3                        0                       # number of times MSHR cap was activated
cpu.dcache.no_allocate_misses                       0                       # Number of misses that were no-allocate
cpu.dcache.overall_accesses                   1459871                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_0                  345984                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_1                  346817                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_2                  407867                       # number of overall (read+write) accesses
cpu.dcache.overall_accesses_3                  359203                       # number of overall (read+write) accesses
cpu.dcache.overall_avg_miss_latency         55.462796                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_0       55.542668                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_1       55.641817                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_2       55.637968                       # average overall miss latency
cpu.dcache.overall_avg_miss_latency_3       55.031711                       # average overall miss latency
cpu.dcache.overall_avg_mshr_miss_latency    40.561041                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_0    40.292078                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_1    40.504702                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_2    41.227505                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_miss_latency_3    40.215668                       # average overall mshr miss latency
cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_0     no value                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_1     no value                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_2     no value                       # average overall mshr uncacheable latency
cpu.dcache.overall_avg_mshr_uncacheable_latency_3     no value                       # average overall mshr uncacheable latency
cpu.dcache.overall_hits                       1367005                       # number of overall hits
cpu.dcache.overall_hits_0                      323016                       # number of overall hits
cpu.dcache.overall_hits_1                      324027                       # number of overall hits
cpu.dcache.overall_hits_2                      384126                       # number of overall hits
cpu.dcache.overall_hits_3                      335836                       # number of overall hits
cpu.dcache.overall_miss_latency               5150608                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_0             1275704                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_1             1268077                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_2             1320901                       # number of overall miss cycles
cpu.dcache.overall_miss_latency_3             1285926                       # number of overall miss cycles
cpu.dcache.overall_miss_rate                 0.063612                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_0               0.066385                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_1               0.065712                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_2               0.058208                       # miss rate for overall accesses
cpu.dcache.overall_miss_rate_3               0.065052                       # miss rate for overall accesses
cpu.dcache.overall_misses                       92866                       # number of overall misses
cpu.dcache.overall_misses_0                     22968                       # number of overall misses
cpu.dcache.overall_misses_1                     22790                       # number of overall misses
cpu.dcache.overall_misses_2                     23741                       # number of overall misses
cpu.dcache.overall_misses_3                     23367                       # number of overall misses
cpu.dcache.overall_mshr_hits                    41556                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_0                  10218                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_1                  10135                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_2                  10805                       # number of overall MSHR hits
cpu.dcache.overall_mshr_hits_3                  10398                       # number of overall MSHR hits
cpu.dcache.overall_mshr_miss_latency          2081187                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_0         513724                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_1         512587                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_2         533319                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_latency_3         521557                       # number of overall MSHR miss cycles
cpu.dcache.overall_mshr_miss_rate            0.035147                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_0          0.036851                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_1          0.036489                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_2          0.031716                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_miss_rate_3          0.036105                       # mshr miss rate for overall accesses
cpu.dcache.overall_mshr_misses                  51310                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_0                12750                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_1                12655                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_2                12936                       # number of overall MSHR misses
cpu.dcache.overall_mshr_misses_3                12969                       # number of overall MSHR misses
cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_2            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_latency_3            0                       # number of overall MSHR uncacheable cycles
cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_2            0                       # number of overall MSHR uncacheable misses
cpu.dcache.overall_mshr_uncacheable_misses_3            0                       # number of overall MSHR uncacheable misses
cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.dcache.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
cpu.dcache.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.dcache.read_accesses                      1008542                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_0                     236568                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_1                     237432                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_2                     286697                       # number of read accesses(hits+misses)
cpu.dcache.read_accesses_3                     247845                       # number of read accesses(hits+misses)
cpu.dcache.read_avg_miss_latency            44.303550                       # average read miss latency
cpu.dcache.read_avg_miss_latency_0          44.084092                       # average read miss latency
cpu.dcache.read_avg_miss_latency_1          43.959622                       # average read miss latency
cpu.dcache.read_avg_miss_latency_2          45.274893                       # average read miss latency
cpu.dcache.read_avg_miss_latency_3          43.866983                       # average read miss latency
cpu.dcache.read_avg_mshr_miss_latency       38.027864                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_0     37.758366                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_1     37.844467                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_2     38.795154                       # average read mshr miss latency
cpu.dcache.read_avg_mshr_miss_latency_3     37.703576                       # average read mshr miss latency
cpu.dcache.read_hits                           948341                       # number of read hits
cpu.dcache.read_hits_0                         221739                       # number of read hits
cpu.dcache.read_hits_1                         222622                       # number of read hits
cpu.dcache.read_hits_2                         271291                       # number of read hits
cpu.dcache.read_hits_3                         232689                       # number of read hits
cpu.dcache.read_miss_latency                  2667118                       # number of read miss cycles
cpu.dcache.read_miss_latency_0                 653723                       # number of read miss cycles
cpu.dcache.read_miss_latency_1                 651042                       # number of read miss cycles
cpu.dcache.read_miss_latency_2                 697505                       # number of read miss cycles
cpu.dcache.read_miss_latency_3                 664848                       # number of read miss cycles
cpu.dcache.read_miss_rate                    0.059691                       # miss rate for read accesses
cpu.dcache.read_miss_rate_0                  0.062684                       # miss rate for read accesses
cpu.dcache.read_miss_rate_1                  0.062376                       # miss rate for read accesses
cpu.dcache.read_miss_rate_2                  0.053736                       # miss rate for read accesses
cpu.dcache.read_miss_rate_3                  0.061151                       # miss rate for read accesses
cpu.dcache.read_misses                          60201                       # number of read misses
cpu.dcache.read_misses_0                        14829                       # number of read misses
cpu.dcache.read_misses_1                        14810                       # number of read misses
cpu.dcache.read_misses_2                        15406                       # number of read misses
cpu.dcache.read_misses_3                        15156                       # number of read misses
cpu.dcache.read_mshr_hits                       15305                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_0                      3713                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_1                      3732                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_2                      4056                       # number of read MSHR hits
cpu.dcache.read_mshr_hits_3                      3804                       # number of read MSHR hits
cpu.dcache.read_mshr_miss_latency             1707299                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_0            419722                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_1            419241                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_2            440325                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_latency_3            428011                       # number of read MSHR miss cycles
cpu.dcache.read_mshr_miss_rate               0.044516                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_0             0.046989                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_1             0.046658                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_2             0.039589                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_miss_rate_3             0.045803                       # mshr miss rate for read accesses
cpu.dcache.read_mshr_misses                     44896                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_0                   11116                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_1                   11078                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_2                   11350                       # number of read MSHR misses
cpu.dcache.read_mshr_misses_3                   11352                       # number of read MSHR misses
cpu.dcache.repl_pool_dist.start_dist                           # Dist. of Repl. across pools
cpu.dcache.repl_pool_dist.samples               50675                      
cpu.dcache.repl_pool_dist.min_value                 0                      
                               0        50675  10000.00%           
                               1            0      0.00%           
                               2            0      0.00%           
                               3            0      0.00%           
                               4            0      0.00%           
                               5            0      0.00%           
                               6            0      0.00%           
                               7            0      0.00%           
                               8            0      0.00%           
                               9            0      0.00%           
                              10            0      0.00%           
                              11            0      0.00%           
                              12            0      0.00%           
                              13            0      0.00%           
                              14            0      0.00%           
                              15            0      0.00%           
                              16            0      0.00%           
cpu.dcache.repl_pool_dist.max_value                 0                      
cpu.dcache.repl_pool_dist.end_dist

cpu.dcache.replacements                         50675                       # number of replacements
cpu.dcache.replacements_0                       12591                       # number of replacements
cpu.dcache.replacements_1                       12491                       # number of replacements
cpu.dcache.replacements_2                       12777                       # number of replacements
cpu.dcache.replacements_3                       12816                       # number of replacements
cpu.dcache.sampled_refs                         51699                       # Sample count of references to valid blocks.
cpu.dcache.set_access_dist.start_dist                          # Dist. of Accesses across sets
cpu.dcache.set_access_dist.samples            1459871                      
cpu.dcache.set_access_dist.min_value                0                      
                               0          784      5.37%           
                               1          761      5.21%           
                               2         1250      8.56%           
                               3          752      5.15%           
                               4          810      5.55%           
                               5          982      6.73%           
                               6         1012      6.93%           
                               7          915      6.27%           
                               8          894      6.12%           
                               9          648      4.44%           
                              10         1332      9.12%           
                              11          879      6.02%           
                              12          702      4.81%           
                              13          932      6.38%           
                              14          616      4.22%           
                              15          810      5.55%           
                              16          552      3.78%           
                              17          607      4.16%           
                              18          787      5.39%           
                              19         1148      7.86%           
                              20          697      4.77%           
                              21          693      4.75%           
                              22          932      6.38%           
                              23          854      5.85%           
                              24         1002      6.86%           
                              25          777      5.32%           
                              26          735      5.03%           
                              27          848      5.81%           
                              28         2209     15.13%           
                              29          868      5.95%           
                              30          708      4.85%           
                              31          919      6.30%           
                              32          721      4.94%           
                              33          826      5.66%           
                              34          653      4.47%           
                              35          638      4.37%           
                              36          720      4.93%           
                              37         1005      6.88%           
                              38          824      5.64%           
                              39          667      4.57%           
                              40          759      5.20%           
                              41          934      6.40%           
                              42          624      4.27%           
                              43          857      5.87%           
                              44         1517     10.39%           
                              45         2112     14.47%           
                              46         2281     15.62%           
                              47         1260      8.63%           
                              48          824      5.64%           
                              49         1558     10.67%           
                              50        60715    415.89%           
                              51         1047      7.17%           
                              52          828      5.67%           
                              53          652      4.47%           
                              54          790      5.41%           
                              55         1065      7.30%           
                              56         5771     39.53%           
                              57          978      6.70%           
                              58         3311     22.68%           
                              59         8751     59.94%           
                              60         1756     12.03%           
                              61          845      5.79%           
                              62         1072      7.34%           
                              63         1138      7.80%           
                              64          935      6.40%           
                              65          611      4.19%           
                              66          353      2.42%           
                              67          509      3.49%           
                              68         1682     11.52%           
                              69         1672     11.45%           
                              70          292      2.00%           
                              71          400      2.74%           
                              72          536      3.67%           
                              73          568      3.89%           
                              74          854      5.85%           
                              75          901      6.17%           
                              76          412      2.82%           
                              77          472      3.23%           
                              78          272      1.86%           
                              79          622      4.26%           
                              80          352      2.41%           
                              81         3429     23.49%           
                              82          377      2.58%           
                              83          641      4.39%           
                              84          301      2.06%           
                              85          328      2.25%           
                              86         5774     39.55%           
                              87        11314     77.50%           
                              88          663      4.54%           
                              89          526      3.60%           
                              90          400      2.74%           
                              91          714      4.89%           
                              92          262      1.79%           
                              93          297      2.03%           
                              94          493      3.38%           
                              95          346      2.37%           
                              96        13512     92.56%           
                              97        26381    180.71%           
                              98        15799    108.22%           
                              99        13456     92.17%           
                             100        39196    268.49%           
                             101        50675    347.12%           
                             102        38358    262.75%           
                             103        55786    382.13%           
                             104          366      2.51%           
                             105        79654    545.62%           
                             106        32731    224.20%           
                             107        16884    115.65%           
                             108          163      1.12%           
                             109          326      2.23%           
                             110        44936    307.81%           
                             111         9099     62.33%           
                             112          691      4.73%           
                             113          547      3.75%           
                             114         1967     13.47%           
                             115         3967     27.17%           
                             116         2374     16.26%           
                             117         5756     39.43%           
                             118          995      6.82%           
                             119          867      5.94%           
                             120        22527    154.31%           
                             121         2083     14.27%           
                             122         9707     66.49%           
                             123        26117    178.90%           
                             124        11711     80.22%           
                             125        13952     95.57%           
                             126         6375     43.67%           
                             127        11753     80.51%           
                             128         9145     62.64%           
                             129         5929     40.61%           
                             130         3522     24.13%           
                             131         4986     34.15%           
                             132         7545     51.68%           
                             133         5734     39.28%           
                             134         5701     39.05%           
                             135         7188     49.24%           
                             136         3543     24.27%           
                             137         2550     17.47%           
                             138        14401     98.65%           
                             139         9647     66.08%           
                             140          334      2.29%           
                             141          541      3.71%           
                             142         7975     54.63%           
                             143          100      0.68%           
                             144         2233     15.30%           
                             145         4947     33.89%           
                             146          944      6.47%           
                             147         2221     15.21%           
                             148          411      2.82%           
                             149         1819     12.46%           
                             150         3059     20.95%           
                             151         3551     24.32%           
                             152         1934     13.25%           
                             153         1643     11.25%           
                             154          703      4.82%           
                             155          318      2.18%           
                             156         1995     13.67%           
                             157         6787     46.49%           
                             158         1506     10.32%           
                             159         2781     19.05%           
                             160           64      0.44%           
                             161          542      3.71%           
                             162         2063     14.13%           
                             163         1656     11.34%           
                             164         1408      9.64%           
                             165          245      1.68%           
                             166          408      2.79%           
                             167          388      2.66%           
                             168          201      1.38%           
                             169          241      1.65%           
                             170          370      2.53%           
                             171          709      4.86%           
                             172         1677     11.49%           
                             173           84      0.58%           
                             174         1126      7.71%           
                             175          595      4.08%           
                             176           65      0.45%           
                             177         1646     11.27%           
                             178          118      0.81%           
                             179          106      0.73%           
                             180           65      0.45%           
                             181         1768     12.11%           
                             182         2527     17.31%           
                             183         1434      9.82%           
                             184          378      2.59%           
                             185          147      1.01%           
                             186          332      2.27%           
                             187          458      3.14%           
                             188          251      1.72%           
                             189          283      1.94%           
                             190          362      2.48%           
                             191         1877     12.86%           
                             192          210      1.44%           
                             193          124      0.85%           
                             194          146      1.00%           
                             195          281      1.92%           
                             196          279      1.91%           
                             197          359      2.46%           
                             198          210      1.44%           
                             199          112      0.77%           
                             200          359      2.46%           
                             201          232      1.59%           
                             202         1122      7.69%           
                             203          294      2.01%           
                             204          406      2.78%           
                             205          199      1.36%           
                             206          273      1.87%           
                             207          278      1.90%           
                             208         1885     12.91%           
                             209         3751     25.69%           
                             210          744      5.10%           
                             211         1589     10.88%           
                             212         2343     16.05%           
                             213          408      2.79%           
                             214          229      1.57%           
                             215          397      2.72%           
                             216          734      5.03%           
                             217          350      2.40%           
                             218         5710     39.11%           
                             219          896      6.14%           
                             220          473      3.24%           
                             221         5869     40.20%           
                             222          171      1.17%           
                             223         1421      9.73%           
                             224          486      3.33%           
                             225          181      1.24%           
                             226          123      0.84%           
                             227          166      1.14%           
                             228         2620     17.95%           
                             229         1609     11.02%           
                             230         2273     15.57%           
                             231         1850     12.67%           
                             232          296      2.03%           
                             233          474      3.25%           
                             234          220      1.51%           
                             235         1472     10.08%           
                             236           95      0.65%           
                             237          185      1.27%           
                             238          116      0.79%           
                             239          355      2.43%           
                             240          118      0.81%           
                             241          377      2.58%           
                             242          704      4.82%           
                             243          245      1.68%           
                             244          819      5.61%           
                             245         2621     17.95%           
                             246        21389    146.51%           
                             247          133      0.91%           
                             248         4274     29.28%           
                             249         2392     16.39%           
                             250        10104     69.21%           
                             251          262      1.79%           
                             252          318      2.18%           
                             253          851      5.83%           
                             254          503      3.45%           
                             255          202      1.38%           
                             256        28924    198.13%           
                             257          891      6.10%           
                             258          439      3.01%           
                             259          248      1.70%           
                             260          252      1.73%           
                             261          562      3.85%           
                             262         2121     14.53%           
                             263        69243    474.31%           
                             264         1656     11.34%           
                             265         2381     16.31%           
                             266         1294      8.86%           
                             267         3209     21.98%           
                             268         1103      7.56%           
                             269         1481     10.14%           
                             270          346      2.37%           
                             271          602      4.12%           
                             272         1003      6.87%           
                             273         1584     10.85%           
                             274          394      2.70%           
                             275         3604     24.69%           
                             276         1727     11.83%           
                             277         1006      6.89%           
                             278          469      3.21%           
                             279          206      1.41%           
                             280          236      1.62%           
                             281         5710     39.11%           
                             282         6282     43.03%           
                             283          274      1.88%           
                             284         1284      8.80%           
                             285         1308      8.96%           
                             286         1173      8.03%           
                             287          150      1.03%           
                             288          431      2.95%           
                             289          189      1.29%           
                             290          160      1.10%           
                             291          124      0.85%           
                             292          389      2.66%           
                             293          370      2.53%           
                             294          672      4.60%           
                             295          291      1.99%           
                             296         1153      7.90%           
                             297          979      6.71%           
                             298          971      6.65%           
                             299          221      1.51%           
                             300         4516     30.93%           
                             301         6009     41.16%           
                             302         1190      8.15%           
                             303          257      1.76%           
                             304          192      1.32%           
                             305          134      0.92%           
                             306          182      1.25%           
                             307          936      6.41%           
                             308        13785     94.43%           
                             309         4680     32.06%           
                             310          481      3.29%           
                             311         3578     24.51%           
                             312         1865     12.78%           
                             313          523      3.58%           
                             314          250      1.71%           
                             315          570      3.90%           
                             316          104      0.71%           
                             317          556      3.81%           
                             318          383      2.62%           
                             319          214      1.47%           
                             320          232      1.59%           
                             321          249      1.71%           
                             322           97      0.66%           
                             323          322      2.21%           
                             324          295      2.02%           
                             325          115      0.79%           
                             326          232      1.59%           
                             327          156      1.07%           
                             328         4655     31.89%           
                             329         1899     13.01%           
                             330         7008     48.00%           
                             331          318      2.18%           
                             332          514      3.52%           
                             333          116      0.79%           
                             334          373      2.56%           
                             335          257      1.76%           
                             336          309      2.12%           
                             337          212      1.45%           
                             338          334      2.29%           
                             339          117      0.80%           
                             340          908      6.22%           
                             341         7171     49.12%           
                             342          340      2.33%           
                             343         2245     15.38%           
                             344          412      2.82%           
                             345          339      2.32%           
                             346         1260      8.63%           
                             347          626      4.29%           
                             348          299      2.05%           
                             349          207      1.42%           
                             350          398      2.73%           
                             351          294      2.01%           
                             352          910      6.23%           
                             353         7696     52.72%           
                             354          579      3.97%           
                             355        20391    139.68%           
                             356          916      6.27%           
                             357          465      3.19%           
                             358         2301     15.76%           
                             359         5732     39.26%           
                             360          847      5.80%           
                             361          841      5.76%           
                             362         2983     20.43%           
                             363         6678     45.74%           
                             364          690      4.73%           
                             365          176      1.21%           
                             366          293      2.01%           
                             367          697      4.77%           
                             368          832      5.70%           
                             369          514      3.52%           
                             370          363      2.49%           
                             371         2400     16.44%           
                             372          985      6.75%           
                             373          510      3.49%           
                             374        33415    228.89%           
                             375        22292    152.70%           
                             376         1439      9.86%           
                             377          367      2.51%           
                             378          473      3.24%           
                             379          140      0.96%           
                             380          742      5.08%           
                             381          449      3.08%           
                             382          813      5.57%           
                             383         3170     21.71%           
                             384          805      5.51%           
                             385          651      4.46%           
                             386          847      5.80%           
                             387          975      6.68%           
                             388          590      4.04%           
                             389          754      5.16%           
                             390        21662    148.38%           
                             391        13173     90.23%           
                             392          781      5.35%           
                             393          954      6.53%           
                             394          721      4.94%           
                             395          965      6.61%           
                             396          802      5.49%           
                             397          795      5.45%           
                             398          840      5.75%           
                             399          783      5.36%           
                             400          463      3.17%           
                             401          701      4.80%           
                             402          751      5.14%           
                             403         4312     29.54%           
                             404          755      5.17%           
                             405          753      5.16%           
                             406          671      4.60%           
                             407          506      3.47%           
                             408         1079      7.39%           
                             409          735      5.03%           
                             410          696      4.77%           
                             411          973      6.66%           
                             412          449      3.08%           
                             413          832      5.70%           
                             414          671      4.60%           
                             415          690      4.73%           
                             416          552      3.78%           
                             417          354      2.42%           
                             418          302      2.07%           
                             419          218      1.49%           
                             420          667      4.57%           
                             421          353      2.42%           
                             422          556      3.81%           
                             423          554      3.79%           
                             424          362      2.48%           
                             425          369      2.53%           
                             426          479      3.28%           
                             427          679      4.65%           
                             428          637      4.36%           
                             429          585      4.01%           
                             430          462      3.16%           
                             431          669      4.58%           
                             432          388      2.66%           
                             433          632      4.33%           
                             434         1163      7.97%           
                             435          505      3.46%           
                             436          836      5.73%           
                             437          520      3.56%           
                             438          558      3.82%           
                             439          646      4.43%           
                             440          536      3.67%           
                             441         1238      8.48%           
                             442          592      4.06%           
                             443          465      3.19%           
                             444          512      3.51%           
                             445          306      2.10%           
                             446          636      4.36%           
                             447          814      5.58%           
                             448          923      6.32%           
                             449          985      6.75%           
                             450          534      3.66%           
                             451          613      4.20%           
                             452          581      3.98%           
                             453          643      4.40%           
                             454          595      4.08%           
                             455          741      5.08%           
                             456         1352      9.26%           
                             457         1807     12.38%           
                             458          544      3.73%           
                             459          672      4.60%           
                             460          607      4.16%           
                             461          618      4.23%           
                             462          583      3.99%           
                             463          597      4.09%           
                             464          365      2.50%           
                             465          878      6.01%           
                             466          359      2.46%           
                             467          326      2.23%           
                             468          380      2.60%           
                             469          446      3.06%           
                             470          313      2.14%           
                             471          204      1.40%           
                             472          970      6.64%           
                             473         2073     14.20%           
                             474          678      4.64%           
                             475          467      3.20%           
                             476          583      3.99%           
                             477          760      5.21%           
                             478          400      2.74%           
                             479          729      4.99%           
                             480          358      2.45%           
                             481        11200     76.72%           
                             482          341      2.34%           
                             483          445      3.05%           
                             484          379      2.60%           
                             485          689      4.72%           
                             486          236      1.62%           
                             487          687      4.71%           
                             488          373      2.56%           
                             489          659      4.51%           
                             490          211      1.45%           
                             491          370      2.53%           
                             492          310      2.12%           
                             493          275      1.88%           
                             494          299      2.05%           
                             495          209      1.43%           
                             496          330      2.26%           
                             497          658      4.51%           
                             498          605      4.14%           
                             499          230      1.58%           
                             500          906      6.21%           
                             501         1662     11.38%           
                             502          563      3.86%           
                             503          316      2.16%           
                             504         1961     13.43%           
                             505         1397      9.57%           
                             506          426      2.92%           
                             507          544      3.73%           
                             508        16350    112.00%           
                             509          297      2.03%           
                             510         2296     15.73%           
                             511          851      5.83%           
                             512            0      0.00%           
cpu.dcache.set_access_dist.max_value              511                      
cpu.dcache.set_access_dist.end_dist

cpu.dcache.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_0                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_1                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_2                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.soft_prefetch_mshr_full_3                0                       # number of mshr full events for SW prefetching instrutions
cpu.dcache.swpf_accesses                         1348                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_0                        325                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_1                        336                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_2                        342                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_accesses_3                        345                       # number of swpf accesses(hits+misses)
cpu.dcache.swpf_avg_miss_latency            36.014831                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_0          36.309917                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_1          37.928251                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_2          34.619658                       # average swpf miss latency
cpu.dcache.swpf_avg_miss_latency_3          35.314286                       # average swpf miss latency
cpu.dcache.swpf_avg_mshr_miss_latency       30.258065                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_0     30.272727                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_1     31.202454                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_2     28.935294                       # average swpf mshr miss latency
cpu.dcache.swpf_avg_mshr_miss_latency_3     30.653179                       # average swpf mshr miss latency
cpu.dcache.swpf_hits                              404                       # number of swpf hits
cpu.dcache.swpf_hits_0                             83                       # number of swpf hits
cpu.dcache.swpf_hits_1                            113                       # number of swpf hits
cpu.dcache.swpf_hits_2                            108                       # number of swpf hits
cpu.dcache.swpf_hits_3                            100                       # number of swpf hits
cpu.dcache.swpf_miss_latency                    33998                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_0                   8787                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_1                   8458                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_2                   8101                       # number of swpf miss cycles
cpu.dcache.swpf_miss_latency_3                   8652                       # number of swpf miss cycles
cpu.dcache.swpf_miss_rate                    0.700297                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_0                  0.744615                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_1                  0.663690                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_2                  0.684211                       # miss rate for swpf accesses
cpu.dcache.swpf_miss_rate_3                  0.710145                       # miss rate for swpf accesses
cpu.dcache.swpf_misses                            944                       # number of swpf misses
cpu.dcache.swpf_misses_0                          242                       # number of swpf misses
cpu.dcache.swpf_misses_1                          223                       # number of swpf misses
cpu.dcache.swpf_misses_2                          234                       # number of swpf misses
cpu.dcache.swpf_misses_3                          245                       # number of swpf misses
cpu.dcache.swpf_mshr_hits                         262                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_0                        66                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_1                        60                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_2                        64                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_hits_3                        72                       # number of swpf MSHR hits
cpu.dcache.swpf_mshr_miss_latency               20636                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_0              5328                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_1              5086                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_2              4919                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_latency_3              5303                       # number of swpf MSHR miss cycles
cpu.dcache.swpf_mshr_miss_rate               0.505935                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_0             0.541538                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_1             0.485119                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_2             0.497076                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_miss_rate_3             0.501449                       # mshr miss rate for swpf accesses
cpu.dcache.swpf_mshr_misses                       682                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_0                     176                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_1                     163                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_2                     170                       # number of swpf MSHR misses
cpu.dcache.swpf_mshr_misses_3                     173                       # number of swpf MSHR misses
cpu.dcache.tagsinuse                      1008.741481                       # Cycle average of tags in use
cpu.dcache.total_refs                         1366616                       # Total number of references to valid blocks.
cpu.dcache.warmup_cycle                         65948                       # Cycle when the warmup percentage was hit.
cpu.dcache.write_accesses                      449981                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_0                    109091                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_1                    109049                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_2                    120828                       # number of write accesses(hits+misses)
cpu.dcache.write_accesses_3                    111013                       # number of write accesses(hits+misses)
cpu.dcache.write_avg_miss_latency           77.219886                       # average write miss latency
cpu.dcache.write_avg_miss_latency_0         77.648981                       # average write miss latency
cpu.dcache.write_avg_miss_latency_1         78.455202                       # average write miss latency
cpu.dcache.write_avg_miss_latency_2         75.952969                       # average write miss latency
cpu.dcache.write_avg_miss_latency_3         76.879990                       # average write miss latency
cpu.dcache.write_avg_mshr_miss_latency      61.628053                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_0    60.818930                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_1    62.418670                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_2    62.199859                       # average write mshr miss latency
cpu.dcache.write_avg_mshr_miss_latency_3    61.110111                       # average write mshr miss latency
cpu.dcache.write_hits                          418260                       # number of write hits
cpu.dcache.write_hits_0                        101194                       # number of write hits
cpu.dcache.write_hits_1                        101292                       # number of write hits
cpu.dcache.write_hits_2                        112727                       # number of write hits
cpu.dcache.write_hits_3                        103047                       # number of write hits
cpu.dcache.write_miss_latency                 2449492                       # number of write miss cycles
cpu.dcache.write_miss_latency_0                613194                       # number of write miss cycles
cpu.dcache.write_miss_latency_1                608577                       # number of write miss cycles
cpu.dcache.write_miss_latency_2                615295                       # number of write miss cycles
cpu.dcache.write_miss_latency_3                612426                       # number of write miss cycles
cpu.dcache.write_miss_rate                   0.070494                       # miss rate for write accesses
cpu.dcache.write_miss_rate_0                 0.072389                       # miss rate for write accesses
cpu.dcache.write_miss_rate_1                 0.071133                       # miss rate for write accesses
cpu.dcache.write_miss_rate_2                 0.067046                       # miss rate for write accesses
cpu.dcache.write_miss_rate_3                 0.071757                       # miss rate for write accesses
cpu.dcache.write_misses                         31721                       # number of write misses
cpu.dcache.write_misses_0                        7897                       # number of write misses
cpu.dcache.write_misses_1                        7757                       # number of write misses
cpu.dcache.write_misses_2                        8101                       # number of write misses
cpu.dcache.write_misses_3                        7966                       # number of write misses
cpu.dcache.write_mshr_hits                      25989                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_0                     6439                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_1                     6343                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_2                     6685                       # number of write MSHR hits
cpu.dcache.write_mshr_hits_3                     6522                       # number of write MSHR hits
cpu.dcache.write_mshr_miss_latency             353252                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_0            88674                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_1            88260                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_2            88075                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_latency_3            88243                       # number of write MSHR miss cycles
cpu.dcache.write_mshr_miss_rate              0.012738                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_0            0.013365                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_1            0.012967                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_2            0.011719                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_miss_rate_3            0.013007                       # mshr miss rate for write accesses
cpu.dcache.write_mshr_misses                     5732                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_0                   1458                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_1                   1414                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_2                   1416                       # number of write MSHR misses
cpu.dcache.write_mshr_misses_3                   1444                       # number of write MSHR misses
cpu.dcache.writebacks                           10382                       # number of writebacks
cpu.dcache.writebacks_0                          2596                       # number of writebacks
cpu.dcache.writebacks_1                          2562                       # number of writebacks
cpu.dcache.writebacks_2                          2595                       # number of writebacks
cpu.dcache.writebacks_3                          2629                       # number of writebacks
cpu.floss.fetch_0.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_0.end_dist
cpu.floss.fetch_1.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_1.end_dist
cpu.floss.fetch_2.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_2.end_dist
cpu.floss.fetch_3.start_dist
                            None            0                      
                       Bandwidth            0                      
                           BrLim            0                      
                           InvPC            0                      
                        BTB_Miss            0                      
                       BrRecover            0                      
                      FaultFlush            0                      
                            Sync            0                      
                         LowConf            0                      
                          Policy            0                      
                         Unknown            0                      
                       Zero_Prio            0                      
                    meta: ICache            0                      
                     meta: QFull            0                      
cpu.floss.fetch_3.end_dist
cpu.floss.icache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_0.end_dist
cpu.floss.icache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_1.end_dist
cpu.floss.icache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_2.end_dist
cpu.floss.icache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.icache_3.end_dist
cpu.floss.iq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_0.end_dist
cpu.floss.iq_full_1.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_1.end_dist
cpu.floss.iq_full_2.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_2.end_dist
cpu.floss.iq_full_3.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.iq_full_3.end_dist
cpu.floss.iq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_0.end_dist
cpu.floss.iq_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_1.end_dist
cpu.floss.iq_full_dcache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_2.end_dist
cpu.floss.iq_full_dcache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.iq_full_dcache_3.end_dist
cpu.floss.iq_full_deps_0.start_dist
(null)                                              0                      
IntAlu                                              0                      
IntMult                                             0                      
IntDiv                                              0                      
FloatAdd                                            0                      
FloatCmp                                            0                      
FloatCvt                                            0                      
FloatMult                                           0                      
FloatDiv                                            0                      
FloatSqrt                                           0                      
MemRead                                             0                      
MemWrite                                            0                      
IprAccess                                           0                      
InstPrefetch                                        0                      
cpu.floss.iq_full_deps_0.end_dist
cpu.floss.iq_full_deps_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_1.end_dist
cpu.floss.iq_full_deps_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_2.end_dist
cpu.floss.iq_full_deps_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_deps_3.end_dist
cpu.floss.iq_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_0.end_dist
cpu.floss.iq_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_1.end_dist
cpu.floss.iq_full_fu_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_2.end_dist
cpu.floss.iq_full_fu_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.iq_full_fu_3.end_dist
cpu.floss.lsq_full_0.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_0.end_dist
cpu.floss.lsq_full_1.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_1.end_dist
cpu.floss.lsq_full_2.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_2.end_dist
cpu.floss.lsq_full_3.start_dist
                         NoInsts            0                      
                           Queue            0                      
                         IssueBW            0                      
                        TooYoung            0                      
                    IssueInorder            0                      
                      meta: Deps            0                      
                        meta: FU            0                      
                       meta: Mem            0                      
cpu.floss.lsq_full_3.end_dist
cpu.floss.lsq_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_0.end_dist
cpu.floss.lsq_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_1.end_dist
cpu.floss.lsq_full_dcache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_2.end_dist
cpu.floss.lsq_full_dcache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.lsq_full_dcache_3.end_dist
cpu.floss.lsq_full_deps_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_0.end_dist
cpu.floss.lsq_full_deps_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_1.end_dist
cpu.floss.lsq_full_deps_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_2.end_dist
cpu.floss.lsq_full_deps_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_deps_3.end_dist
cpu.floss.lsq_full_fu_0.start_dist
(null)                                              0                      
IntAlu                                              0                      
IntMult                                             0                      
IntDiv                                              0                      
FloatAdd                                            0                      
FloatCmp                                            0                      
FloatCvt                                            0                      
FloatMult                                           0                      
FloatDiv                                            0                      
FloatSqrt                                           0                      
MemRead                                             0                      
MemWrite                                            0                      
IprAccess                                           0                      
InstPrefetch                                        0                      
cpu.floss.lsq_full_fu_0.end_dist
cpu.floss.lsq_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_1.end_dist
cpu.floss.lsq_full_fu_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_2.end_dist
cpu.floss.lsq_full_fu_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.lsq_full_fu_3.end_dist
cpu.floss.qfull_0.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_0.end_dist
cpu.floss.qfull_1.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_1.end_dist
cpu.floss.qfull_2.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_2.end_dist
cpu.floss.qfull_3.start_dist
                       IREG_Full            0                      
                      FPREG_Full            0                      
                         No_Inst            0                      
                         ROB_cap            0                      
                          IQ_cap            0                      
                              BW            0                      
                          Policy            0                      
                     Serializing            0                      
                          Broken            0                      
                   meta: IQ full            0                      
                  meta: LSQ full            0                      
                  meta: ROB full            0                      
cpu.floss.qfull_3.end_dist
cpu.floss.rob_full_0.start_dist
ROB_Empty                                           0                      
Commit_BW                                           0                      
StoreBuf                                            0                      
MemBarrier                                          0                      
meta: FU                                            0                      
meta: DCache                                        0                      
cpu.floss.rob_full_0.end_dist
cpu.floss.rob_full_1.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_1.end_dist
cpu.floss.rob_full_2.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_2.end_dist
cpu.floss.rob_full_3.start_dist
                       ROB_Empty            0                      
                       Commit_BW            0                      
                        StoreBuf            0                      
                      MemBarrier            0                      
                        meta: FU            0                      
                    meta: DCache            0                      
cpu.floss.rob_full_3.end_dist
cpu.floss.rob_full_dcache_0.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_0.end_dist
cpu.floss.rob_full_dcache_1.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_1.end_dist
cpu.floss.rob_full_dcache_2.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_2.end_dist
cpu.floss.rob_full_dcache_3.start_dist
                             Hit            0                      
                            Miss            0                      
                        TLB miss            0                      
                     Bad address            0                      
                      MSHRs full            0                      
               MSHR targets full            0                      
                    Miss pending            0                      
                      Not issued            0                      
                   Not predicted            0                      
                        Canceled            0                      
                         Dropped            0                      
                        Filtered            0                      
                       No result            0                      
                         Success            0                      
           Blocked hard prefetch            0                      
                Blocked prefetch            0                      
                     Blocked all            0                      
cpu.floss.rob_full_dcache_3.end_dist
cpu.floss.rob_full_fu_0.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_0.end_dist
cpu.floss.rob_full_fu_1.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_1.end_dist
cpu.floss.rob_full_fu_2.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_2.end_dist
cpu.floss.rob_full_fu_3.start_dist
                          (null)            0                      
                          IntAlu            0                      
                         IntMult            0                      
                          IntDiv            0                      
                        FloatAdd            0                      
                        FloatCmp            0                      
                        FloatCvt            0                      
                       FloatMult            0                      
                        FloatDiv            0                      
                       FloatSqrt            0                      
                         MemRead            0                      
                        MemWrite            0                      
                       IprAccess            0                      
                    InstPrefetch            0                      
cpu.floss.rob_full_fu_3.end_dist
cpu.icache.avg_blocked_cycles_no_mshrs       8.918033                       # average number of cycles each access was blocked
cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
cpu.icache.avg_refs                          3.352523                       # Average number of references to valid blocks.
cpu.icache.blocked_no_mshrs                        61                       # number of cycles access was blocked
cpu.icache.blocked_no_targets                       0                       # number of cycles access was blocked
cpu.icache.blocked_cycles_no_mshrs                544                       # number of cycles access was blocked
cpu.icache.blocked_cycles_no_targets                0                       # number of cycles access was blocked
cpu.icache.cache_copies                             0                       # number of cache copies performed
cpu.icache.demand_accesses                    1472645                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_0                   324038                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_1                   327668                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_2                   458053                       # number of demand (read+write) accesses
cpu.icache.demand_accesses_3                   362886                       # number of demand (read+write) accesses
cpu.icache.demand_avg_miss_latency          16.605997                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_0        16.813085                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_1        16.772123                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_2        16.327927                       # average overall miss latency
cpu.icache.demand_avg_miss_latency_3        16.489730                       # average overall miss latency
cpu.icache.demand_avg_mshr_miss_latency     17.333748                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_0    17.215166                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_1    17.237077                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_2    17.526680                       # average overall mshr miss latency
cpu.icache.demand_avg_mshr_miss_latency_3    17.371092                       # average overall mshr miss latency
cpu.icache.demand_hits                        1126716                       # number of demand (read+write) hits
cpu.icache.demand_hits_0                       235613                       # number of demand (read+write) hits
cpu.icache.demand_hits_1                       239401                       # number of demand (read+write) hits
cpu.icache.demand_hits_2                       375864                       # number of demand (read+write) hits
cpu.icache.demand_hits_3                       275838                       # number of demand (read+write) hits
cpu.icache.demand_miss_latency                5744496                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_0              1486697                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_1              1480425                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_2              1341976                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_latency_3              1435398                       # number of demand (read+write) miss cycles
cpu.icache.demand_miss_rate                  0.234903                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_0                0.272885                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_1                0.269379                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_2                0.179431                       # miss rate for demand accesses
cpu.icache.demand_miss_rate_3                0.239877                       # miss rate for demand accesses
cpu.icache.demand_misses                       345929                       # number of demand (read+write) misses
cpu.icache.demand_misses_0                      88425                       # number of demand (read+write) misses
cpu.icache.demand_misses_1                      88267                       # number of demand (read+write) misses
cpu.icache.demand_misses_2                      82189                       # number of demand (read+write) misses
cpu.icache.demand_misses_3                      87048                       # number of demand (read+write) misses
cpu.icache.demand_mshr_hits                      5061                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_0                    1097                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_1                    1156                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_2                    1453                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_hits_3                    1355                       # number of demand (read+write) MSHR hits
cpu.icache.demand_mshr_miss_latency           5908520                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_0         1503366                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_1         1501539                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_2         1415034                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_latency_3         1488581                       # number of demand (read+write) MSHR miss cycles
cpu.icache.demand_mshr_miss_rate             0.231467                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_0           0.269499                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_1           0.265851                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_2           0.176259                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_miss_rate_3           0.236143                       # mshr miss rate for demand accesses
cpu.icache.demand_mshr_misses                  340868                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_0                 87328                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_1                 87111                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_2                 80736                       # number of demand (read+write) MSHR misses
cpu.icache.demand_mshr_misses_3                 85693                       # number of demand (read+write) MSHR misses
cpu.icache.fast_writes                              0                       # number of fast writes performed
cpu.icache.mshr_cap_events                          0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_0                        0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_1                        0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_2                        0                       # number of times MSHR cap was activated
cpu.icache.mshr_cap_events_3                        0                       # number of times MSHR cap was activated
cpu.icache.no_allocate_misses                       0                       # Number of misses that were no-allocate
cpu.icache.overall_accesses                   1472645                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_0                  324038                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_1                  327668                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_2                  458053                       # number of overall (read+write) accesses
cpu.icache.overall_accesses_3                  362886                       # number of overall (read+write) accesses
cpu.icache.overall_avg_miss_latency         16.605997                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_0       16.813085                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_1       16.772123                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_2       16.327927                       # average overall miss latency
cpu.icache.overall_avg_miss_latency_3       16.489730                       # average overall miss latency
cpu.icache.overall_avg_mshr_miss_latency    17.333748                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_0    17.215166                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_1    17.237077                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_2    17.526680                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_miss_latency_3    17.371092                       # average overall mshr miss latency
cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_2 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_avg_mshr_uncacheable_latency_3 <err: div-0>                       # average overall mshr uncacheable latency
cpu.icache.overall_hits                       1126716                       # number of overall hits
cpu.icache.overall_hits_0                      235613                       # number of overall hits
cpu.icache.overall_hits_1                      239401                       # number of overall hits
cpu.icache.overall_hits_2                      375864                       # number of overall hits
cpu.icache.overall_hits_3                      275838                       # number of overall hits
cpu.icache.overall_miss_latency               5744496                       # number of overall miss cycles
cpu.icache.overall_miss_latency_0             1486697                       # number of overall miss cycles
cpu.icache.overall_miss_latency_1             1480425                       # number of overall miss cycles
cpu.icache.overall_miss_latency_2             1341976                       # number of overall miss cycles
cpu.icache.overall_miss_latency_3             1435398                       # number of overall miss cycles
cpu.icache.overall_miss_rate                 0.234903                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_0               0.272885                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_1               0.269379                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_2               0.179431                       # miss rate for overall accesses
cpu.icache.overall_miss_rate_3               0.239877                       # miss rate for overall accesses
cpu.icache.overall_misses                      345929                       # number of overall misses
cpu.icache.overall_misses_0                     88425                       # number of overall misses
cpu.icache.overall_misses_1                     88267                       # number of overall misses
cpu.icache.overall_misses_2                     82189                       # number of overall misses
cpu.icache.overall_misses_3                     87048                       # number of overall misses
cpu.icache.overall_mshr_hits                     5061                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_0                   1097                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_1                   1156                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_2                   1453                       # number of overall MSHR hits
cpu.icache.overall_mshr_hits_3                   1355                       # number of overall MSHR hits
cpu.icache.overall_mshr_miss_latency          5908520                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_0        1503366                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_1        1501539                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_2        1415034                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_latency_3        1488581                       # number of overall MSHR miss cycles
cpu.icache.overall_mshr_miss_rate            0.231467                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_0          0.269499                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_1          0.265851                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_2          0.176259                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_miss_rate_3          0.236143                       # mshr miss rate for overall accesses
cpu.icache.overall_mshr_misses                 340868                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_0                87328                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_1                87111                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_2                80736                       # number of overall MSHR misses
cpu.icache.overall_mshr_misses_3                85693                       # number of overall MSHR misses
cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_2            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_latency_3            0                       # number of overall MSHR uncacheable cycles
cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_2            0                       # number of overall MSHR uncacheable misses
cpu.icache.overall_mshr_uncacheable_misses_3            0                       # number of overall MSHR uncacheable misses
cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.icache.prefetcher.num_hwpf_evicted              0                       # number of hwpf removed due to no buffer left
cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
cpu.icache.prefetcher.num_hwpf_issued               0                       # number of hwpf issued
cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.icache.read_accesses                      1472645                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_0                     324038                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_1                     327668                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_2                     458053                       # number of read accesses(hits+misses)
cpu.icache.read_accesses_3                     362886                       # number of read accesses(hits+misses)
cpu.icache.read_avg_miss_latency            16.605997                       # average read miss latency
cpu.icache.read_avg_miss_latency_0          16.813085                       # average read miss latency
cpu.icache.read_avg_miss_latency_1          16.772123                       # average read miss latency
cpu.icache.read_avg_miss_latency_2          16.327927                       # average read miss latency
cpu.icache.read_avg_miss_latency_3          16.489730                       # average read miss latency
cpu.icache.read_avg_mshr_miss_latency       17.333748                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_0     17.215166                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_1     17.237077                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_2     17.526680                       # average read mshr miss latency
cpu.icache.read_avg_mshr_miss_latency_3     17.371092                       # average read mshr miss latency
cpu.icache.read_hits                          1126716                       # number of read hits
cpu.icache.read_hits_0                         235613                       # number of read hits
cpu.icache.read_hits_1                         239401                       # number of read hits
cpu.icache.read_hits_2                         375864                       # number of read hits
cpu.icache.read_hits_3                         275838                       # number of read hits
cpu.icache.read_miss_latency                  5744496                       # number of read miss cycles
cpu.icache.read_miss_latency_0                1486697                       # number of read miss cycles
cpu.icache.read_miss_latency_1                1480425                       # number of read miss cycles
cpu.icache.read_miss_latency_2                1341976                       # number of read miss cycles
cpu.icache.read_miss_latency_3                1435398                       # number of read miss cycles
cpu.icache.read_miss_rate                    0.234903                       # miss rate for read accesses
cpu.icache.read_miss_rate_0                  0.272885                       # miss rate for read accesses
cpu.icache.read_miss_rate_1                  0.269379                       # miss rate for read accesses
cpu.icache.read_miss_rate_2                  0.179431                       # miss rate for read accesses
cpu.icache.read_miss_rate_3                  0.239877                       # miss rate for read accesses
cpu.icache.read_misses                         345929                       # number of read misses
cpu.icache.read_misses_0                        88425                       # number of read misses
cpu.icache.read_misses_1                        88267                       # number of read misses
cpu.icache.read_misses_2                        82189                       # number of read misses
cpu.icache.read_misses_3                        87048                       # number of read misses
cpu.icache.read_mshr_hits                        5061                       # number of read MSHR hits
cpu.icache.read_mshr_hits_0                      1097                       # number of read MSHR hits
cpu.icache.read_mshr_hits_1                      1156                       # number of read MSHR hits
cpu.icache.read_mshr_hits_2                      1453                       # number of read MSHR hits
cpu.icache.read_mshr_hits_3                      1355                       # number of read MSHR hits
cpu.icache.read_mshr_miss_latency             5908520                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_0           1503366                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_1           1501539                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_2           1415034                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_latency_3           1488581                       # number of read MSHR miss cycles
cpu.icache.read_mshr_miss_rate               0.231467                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_0             0.269499                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_1             0.265851                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_2             0.176259                       # mshr miss rate for read accesses
cpu.icache.read_mshr_miss_rate_3             0.236143                       # mshr miss rate for read accesses
cpu.icache.read_mshr_misses                    340868                       # number of read MSHR misses
cpu.icache.read_mshr_misses_0                   87328                       # number of read MSHR misses
cpu.icache.read_mshr_misses_1                   87111                       # number of read MSHR misses
cpu.icache.read_mshr_misses_2                   80736                       # number of read MSHR misses
cpu.icache.read_mshr_misses_3                   85693                       # number of read MSHR misses
cpu.icache.replacements                        335059                       # number of replacements
cpu.icache.replacements_0                       86105                       # number of replacements
cpu.icache.replacements_1                       85711                       # number of replacements
cpu.icache.replacements_2                       78956                       # number of replacements
cpu.icache.replacements_3                       84287                       # number of replacements
cpu.icache.sampled_refs                        336080                       # Sample count of references to valid blocks.
cpu.icache.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_0                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_1                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_2                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.soft_prefetch_mshr_full_3                0                       # number of mshr full events for SW prefetching instrutions
cpu.icache.tagsinuse                       952.370223                       # Cycle average of tags in use
cpu.icache.total_refs                         1126716                       # Total number of references to valid blocks.
cpu.icache.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
cpu.icache.writebacks                               0                       # number of writebacks
cpu.icache.writebacks_0                             0                       # number of writebacks
cpu.icache.writebacks_1                             0                       # number of writebacks
cpu.icache.writebacks_2                             0                       # number of writebacks
cpu.icache.writebacks_3                             0                       # number of writebacks
cpu.iq:RQ:rdy_inst                            6726366                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_0                          1568405                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_1                          1572282                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_2                          1931220                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_3                          1654459                       # Number of ready instructions (cum)
cpu.iq:RQ:rdy_inst_dist_0_mean               0.882859                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_0_stdev              2.100732                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_0_TOT       1776507                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_1_mean               0.885041                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_1_stdev              2.103078                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_1_TOT       1776507                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_2_mean               1.087088                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_2_stdev              2.524358                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_2_TOT       1776507                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_3_mean               0.931299                       # standard deviation of ready rate
cpu.iq:RQ:rdy_inst_dist_3_stdev              2.208679                       # standard deviation of ready rate
**Ignore: cpu.iq:RQ:rdy_inst_dist_3_TOT       1776507                       # standard deviation of ready rate
cpu.iq:RQ:rdy_rate                           3.786287                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_0                         0.882859                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_1                         0.885041                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_2                         1.087088                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_rate_3                         0.931299                       # Number of ready insts per cycle
cpu.iq:RQ:rdy_x_count                         4278834                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_0                       1002781                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_1                       1006712                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_2                       1215204                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_count_3                       1054137                       # number of insts that become ready (cum)
cpu.iq:RQ:rdy_x_max                                33                       # largest number of insts that become ready
cpu.iq:RQ:rdy_x_rate                         2.408566                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_0                       0.564468                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_1                       0.566681                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_2                       0.684041                       # number of insts that become ready per cycle
cpu.iq:RQ:rdy_x_rate_3                       0.593376                       # number of insts that become ready per cycle
cpu.iq:avg_residency                         8.617776                       # Average IQ residency
cpu.iq:avg_residency_0                       8.452211                       # Average IQ residency
cpu.iq:avg_residency_1                       8.482296                       # Average IQ residency
cpu.iq:avg_residency_2                       8.780531                       # Average IQ residency
cpu.iq:avg_residency_3                       8.718813                       # Average IQ residency
cpu.iq:cum_num_insts                         36370412                       # Total occupancy
cpu.iq:cum_num_insts_0                        8387264                       # Total occupancy
cpu.iq:cum_num_insts_1                        8445169                       # Total occupancy
cpu.iq:cum_num_insts_2                       10473927                       # Total occupancy
cpu.iq:cum_num_insts_3                        9064052                       # Total occupancy
cpu.iq:current_count                               49                       # Occupancy this cycle
cpu.iq:empty_count                             185627                       # Number of empty cycles
cpu.iq:empty_rate                           10.448988                       # Fraction of cycles empty
cpu.iq:full_count                              159266                       # Number of full cycles
cpu.iq:full_rate                             8.965121                       # Fraction of cycles full
cpu.iq:occ_dist_0.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_0.samples                     1776507                      
cpu.iq:occ_dist_0.min_value                         0                      
                               0       983874              5538.25%
                               2       200705              6668.02%
                               4       123202              7361.53%
                               6        83306              7830.46%
                               8        73315              8243.15%
                              10        42262              8481.05%
                              12        32167              8662.12%
                              14        28020              8819.84%
                              16       100103              9383.32%
                              18        17531              9482.01%
                              20        14701              9564.76%
                              22        12994              9637.90%
                              24         8881              9687.89%
                              26         7940              9732.59%
                              28         6727              9770.45%
                              30         7536              9812.87%
                              32         5084              9841.49%
                              34         3485              9861.11%
                              36         3298              9879.67%
                              38         2496              9893.72%
                              40         2242              9906.34%
                              42         1703              9915.93%
                              44         1522              9924.50%
                              46         1639              9933.72%
                              48         1404              9941.63%
                              50         1832              9951.94%
                              52         1343              9959.50%
                              54         1440              9967.60%
                              56         1191              9974.31%
                              58         1077              9980.37%
                              60         1232              9987.31%
                              62         1009              9992.99%
                              64         1246             10000.00%
cpu.iq:occ_dist_0.max_value                        64                      
cpu.iq:occ_dist_0.end_dist

cpu.iq:occ_dist_1.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_1.samples                     1776507                      
cpu.iq:occ_dist_1.min_value                         0                      
                               0       982133              5528.45%
                               2       198742              6647.17%
                               4       123309              7341.28%
                               6        83280              7810.07%
                               8        73134              8221.74%
                              10        41664              8456.27%
                              12        33436              8644.48%
                              14        28025              8802.23%
                              16       100658              9368.84%
                              18        18051              9470.45%
                              20        14674              9553.05%
                              22        13193              9627.31%
                              24        10024              9683.74%
                              26         8059              9729.10%
                              28         7350              9770.48%
                              30         7503              9812.71%
                              32         5244              9842.23%
                              34         3503              9861.95%
                              36         2985              9878.75%
                              38         2620              9893.50%
                              40         2460              9907.35%
                              42         2536              9921.62%
                              44         1795              9931.73%
                              46         1533              9940.35%
                              48         1361              9948.02%
                              50         1486              9956.38%
                              52         1261              9963.48%
                              54         1162              9970.02%
                              56         1135              9976.41%
                              58          919              9981.58%
                              60         1182              9988.24%
                              62         1041              9994.10%
                              64         1049             10000.00%
cpu.iq:occ_dist_1.max_value                        64                      
cpu.iq:occ_dist_1.end_dist

cpu.iq:occ_dist_2.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_2.samples                     1776507                      
cpu.iq:occ_dist_2.min_value                         0                      
                               0       942146              5303.36%
                               2       182594              6331.19%
                               4       111015              6956.09%
                               6        79353              7402.77%
                               8        73527              7816.66%
                              10        45496              8072.76%
                              12        37582              8284.31%
                              14        33826              8474.71%
                              16       105048              9066.03%
                              18        23369              9197.58%
                              20        19490              9307.29%
                              22        16776              9401.72%
                              24        12996              9474.87%
                              26        11612              9540.24%
                              28        10337              9598.43%
                              30         9530              9652.07%
                              32         8003              9697.12%
                              34         5737              9729.41%
                              36         5485              9760.29%
                              38         4874              9787.72%
                              40         4286              9811.85%
                              42         3652              9832.41%
                              44         3563              9852.46%
                              46         3183              9870.38%
                              48         2846              9886.40%
                              50         3081              9903.74%
                              52         2529              9917.98%
                              54         3153              9935.73%
                              56         2289              9948.61%
                              58         2248              9961.27%
                              60         2481              9975.23%
                              62         2315              9988.26%
                              64         2085             10000.00%
cpu.iq:occ_dist_2.max_value                        64                      
cpu.iq:occ_dist_2.end_dist

cpu.iq:occ_dist_3.start_dist                                   # IQ Occupancy per cycle
cpu.iq:occ_dist_3.samples                     1776507                      
cpu.iq:occ_dist_3.min_value                         0                      
                               0       972797              5475.90%
                               2       197691              6588.70%
                               4       121488              7272.56%
                               6        82309              7735.88%
                               8        72998              8146.79%
                              10        41052              8377.87%
                              12        32428              8560.41%
                              14        29356              8725.66%
                              16        99824              9287.57%
                              18        18337              9390.79%
                              20        14775              9473.96%
                              22        13450              9549.67%
                              24        10456              9608.52%
                              26         8360              9655.58%
                              28         7669              9698.75%
                              30         7781              9742.55%
                              32         6529              9779.30%
                              34         4068              9802.20%
                              36         4021              9824.84%
                              38         3075              9842.15%
                              40         2913              9858.54%
                              42         2781              9874.20%
                              44         2577              9888.70%
                              46         2196              9901.06%
                              48         2394              9914.54%
                              50         2188              9926.86%
                              52         1793              9936.95%
                              54         2122              9948.89%
                              56         1856              9959.34%
                              58         1615              9968.43%
                              60         1709              9978.05%
                              62         1695              9987.59%
                              64         2204             10000.00%
cpu.iq:occ_dist_3.max_value                        64                      
cpu.iq:occ_dist_3.end_dist

cpu.iq:occ_rate                             20.472991                       # Average occupancy
cpu.iq:occ_rate_0                            4.721211                       # Average occupancy
cpu.iq:occ_rate_1                            4.753806                       # Average occupancy
cpu.iq:occ_rate_2                            5.895798                       # Average occupancy
cpu.iq:occ_rate_3                            5.102176                       # Average occupancy
cpu.iq:peak_occupancy                             256                       # Peak IQ occupancy
cpu.iq:peak_occupancy_0                            64                       # Peak IQ occupancy
cpu.iq:peak_occupancy_1                            64                       # Peak IQ occupancy
cpu.iq:peak_occupancy_2                            64                       # Peak IQ occupancy
cpu.iq:peak_occupancy_3                            64                       # Peak IQ occupancy
cpu.l2.avg_blocked_cycles_no_mshrs       <err: div-0>                       # average number of cycles each access was blocked
cpu.l2.avg_blocked_cycles_no_targets     <err: div-0>                       # average number of cycles each access was blocked
cpu.l2.avg_refs                          <err: div-0>                       # Average number of references to valid blocks.
cpu.l2.blocked_no_mshrs                             0                       # number of cycles access was blocked
cpu.l2.blocked_no_targets                           0                       # number of cycles access was blocked
cpu.l2.blocked_cycles_no_mshrs                      0                       # number of cycles access was blocked
cpu.l2.blocked_cycles_no_targets                    0                       # number of cycles access was blocked
cpu.l2.cache_copies                                 0                       # number of cache copies performed
cpu.l2.demand_accesses                         387392                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_0                        99088                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_1                        98765                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_2                        92134                       # number of demand (read+write) accesses
cpu.l2.demand_accesses_3                        97405                       # number of demand (read+write) accesses
cpu.l2.demand_avg_miss_latency             128.286161                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_0           128.379654                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_1           128.273329                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_2           128.270786                       # average overall miss latency
cpu.l2.demand_avg_miss_latency_3           128.224219                       # average overall miss latency
cpu.l2.demand_avg_mshr_miss_latency        114.296840                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_0      114.337323                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_1      114.267814                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_2      114.314949                       # average overall mshr miss latency
cpu.l2.demand_avg_mshr_miss_latency_3      114.267223                       # average overall mshr miss latency
cpu.l2.demand_hits                             368850                       # number of demand (read+write) hits
cpu.l2.demand_hits_0                            94576                       # number of demand (read+write) hits
cpu.l2.demand_hits_1                            94232                       # number of demand (read+write) hits
cpu.l2.demand_hits_2                            87311                       # number of demand (read+write) hits
cpu.l2.demand_hits_3                            92731                       # number of demand (read+write) hits
cpu.l2.demand_miss_latency                    2378682                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_0                   579249                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_1                   581463                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_2                   618650                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_latency_3                   599320                       # number of demand (read+write) miss cycles
cpu.l2.demand_miss_rate                      0.047864                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_0                    0.045535                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_1                    0.045897                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_2                    0.052348                       # miss rate for demand accesses
cpu.l2.demand_miss_rate_3                    0.047985                       # miss rate for demand accesses
cpu.l2.demand_misses                            18542                       # number of demand (read+write) misses
cpu.l2.demand_misses_0                           4512                       # number of demand (read+write) misses
cpu.l2.demand_misses_1                           4533                       # number of demand (read+write) misses
cpu.l2.demand_misses_2                           4823                       # number of demand (read+write) misses
cpu.l2.demand_misses_3                           4674                       # number of demand (read+write) misses
cpu.l2.demand_mshr_hits                             0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_0                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_1                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_2                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_hits_3                           0                       # number of demand (read+write) MSHR hits
cpu.l2.demand_mshr_miss_latency               2119292                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_0              515890                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_1              517976                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_2              551341                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_latency_3              534085                       # number of demand (read+write) MSHR miss cycles
cpu.l2.demand_mshr_miss_rate                 0.047864                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_0               0.045535                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_1               0.045897                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_2               0.052348                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_miss_rate_3               0.047985                       # mshr miss rate for demand accesses
cpu.l2.demand_mshr_misses                       18542                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_0                      4512                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_1                      4533                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_2                      4823                       # number of demand (read+write) MSHR misses
cpu.l2.demand_mshr_misses_3                      4674                       # number of demand (read+write) MSHR misses
cpu.l2.falru_accesses                          397774                       # The number of accesses to the FA LRU cache.
cpu.l2.falru_hits_128K                         199287                       # Hits in a 128K cache
cpu.l2.falru_hits_256K                         295873                       # Hits in a 256K cache
cpu.l2.falru_hits_512K                         369010                       # Hits in a 512K cache
cpu.l2.falru_hits_1M                           378215                       # Hits in a 1M cache
cpu.l2.falru_hits_2M                           378986                       # Hits in a 2M cache
cpu.l2.falru_misses_128K                       198487                       # Misses in a 128K cache
cpu.l2.falru_misses_256K                       101901                       # Misses in a 256K cache
cpu.l2.falru_misses_512K                        28764                       # Misses in a 512K cache
cpu.l2.falru_misses_1M                          19559                       # Misses in a 1M cache
cpu.l2.falru_misses_2M                          18788                       # Misses in a 2M cache
cpu.l2.fast_writes                                  0                       # number of fast writes performed
cpu.l2.mshr_cap_events                              0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_0                            0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_1                            0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_2                            0                       # number of times MSHR cap was activated
cpu.l2.mshr_cap_events_3                            0                       # number of times MSHR cap was activated
cpu.l2.no_allocate_misses                           0                       # Number of misses that were no-allocate
cpu.l2.overall_accesses                        397774                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_0                      101684                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_1                      101327                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_2                       94729                       # number of overall (read+write) accesses
cpu.l2.overall_accesses_3                      100034                       # number of overall (read+write) accesses
cpu.l2.overall_avg_miss_latency            126.606451                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_0          126.611803                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_1          126.597649                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_2          126.616865                       # average overall miss latency
cpu.l2.overall_avg_miss_latency_3          126.599071                       # average overall miss latency
cpu.l2.overall_avg_mshr_miss_latency       114.296840                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_0     114.337323                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_1     114.267814                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_2     114.314949                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_miss_latency_3     114.267223                       # average overall mshr miss latency
cpu.l2.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_0 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_1 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_2 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_avg_mshr_uncacheable_latency_3 <err: div-0>                       # average overall mshr uncacheable latency
cpu.l2.overall_hits                            378986                       # number of overall hits
cpu.l2.overall_hits_0                           97109                       # number of overall hits
cpu.l2.overall_hits_1                           96734                       # number of overall hits
cpu.l2.overall_hits_2                           89843                       # number of overall hits
cpu.l2.overall_hits_3                           95300                       # number of overall hits
cpu.l2.overall_miss_latency                   2378682                       # number of overall miss cycles
cpu.l2.overall_miss_latency_0                  579249                       # number of overall miss cycles
cpu.l2.overall_miss_latency_1                  581463                       # number of overall miss cycles
cpu.l2.overall_miss_latency_2                  618650                       # number of overall miss cycles
cpu.l2.overall_miss_latency_3                  599320                       # number of overall miss cycles
cpu.l2.overall_miss_rate                     0.047233                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_0                   0.044992                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_1                   0.045328                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_2                   0.051579                       # miss rate for overall accesses
cpu.l2.overall_miss_rate_3                   0.047324                       # miss rate for overall accesses
cpu.l2.overall_misses                           18788                       # number of overall misses
cpu.l2.overall_misses_0                          4575                       # number of overall misses
cpu.l2.overall_misses_1                          4593                       # number of overall misses
cpu.l2.overall_misses_2                          4886                       # number of overall misses
cpu.l2.overall_misses_3                          4734                       # number of overall misses
cpu.l2.overall_mshr_hits                            0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_0                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_1                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_2                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_hits_3                          0                       # number of overall MSHR hits
cpu.l2.overall_mshr_miss_latency              2119292                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_0             515890                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_1             517976                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_2             551341                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_latency_3             534085                       # number of overall MSHR miss cycles
cpu.l2.overall_mshr_miss_rate                0.046614                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_0              0.044373                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_1              0.044736                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_2              0.050914                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_miss_rate_3              0.046724                       # mshr miss rate for overall accesses
cpu.l2.overall_mshr_misses                      18542                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_0                     4512                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_1                     4533                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_2                     4823                       # number of overall MSHR misses
cpu.l2.overall_mshr_misses_3                     4674                       # number of overall MSHR misses
cpu.l2.overall_mshr_uncacheable_latency             0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_0            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_1            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_2            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_latency_3            0                       # number of overall MSHR uncacheable cycles
cpu.l2.overall_mshr_uncacheable_misses              0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_0            0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_1            0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_2            0                       # number of overall MSHR uncacheable misses
cpu.l2.overall_mshr_uncacheable_misses_3            0                       # number of overall MSHR uncacheable misses
cpu.l2.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
cpu.l2.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
cpu.l2.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
cpu.l2.prefetcher.num_hwpf_evicted                  0                       # number of hwpf removed due to no buffer left
cpu.l2.prefetcher.num_hwpf_identified               0                       # number of hwpf identified
cpu.l2.prefetcher.num_hwpf_issued                   0                       # number of hwpf issued
cpu.l2.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
cpu.l2.prefetcher.num_hwpf_span_page                0                       # number of hwpf spanning a virtual page
cpu.l2.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
cpu.l2.read_accesses                           387392                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_0                          99088                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_1                          98765                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_2                          92134                       # number of read accesses(hits+misses)
cpu.l2.read_accesses_3                          97405                       # number of read accesses(hits+misses)
cpu.l2.read_avg_miss_latency               128.286161                       # average read miss latency
cpu.l2.read_avg_miss_latency_0             128.379654                       # average read miss latency
cpu.l2.read_avg_miss_latency_1             128.273329                       # average read miss latency
cpu.l2.read_avg_miss_latency_2             128.270786                       # average read miss latency
cpu.l2.read_avg_miss_latency_3             128.224219                       # average read miss latency
cpu.l2.read_avg_mshr_miss_latency          114.296840                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_0        114.337323                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_1        114.267814                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_2        114.314949                       # average read mshr miss latency
cpu.l2.read_avg_mshr_miss_latency_3        114.267223                       # average read mshr miss latency
cpu.l2.read_hits                               368850                       # number of read hits
cpu.l2.read_hits_0                              94576                       # number of read hits
cpu.l2.read_hits_1                              94232                       # number of read hits
cpu.l2.read_hits_2                              87311                       # number of read hits
cpu.l2.read_hits_3                              92731                       # number of read hits
cpu.l2.read_miss_latency                      2378682                       # number of read miss cycles
cpu.l2.read_miss_latency_0                     579249                       # number of read miss cycles
cpu.l2.read_miss_latency_1                     581463                       # number of read miss cycles
cpu.l2.read_miss_latency_2                     618650                       # number of read miss cycles
cpu.l2.read_miss_latency_3                     599320                       # number of read miss cycles
cpu.l2.read_miss_rate                        0.047864                       # miss rate for read accesses
cpu.l2.read_miss_rate_0                      0.045535                       # miss rate for read accesses
cpu.l2.read_miss_rate_1                      0.045897                       # miss rate for read accesses
cpu.l2.read_miss_rate_2                      0.052348                       # miss rate for read accesses
cpu.l2.read_miss_rate_3                      0.047985                       # miss rate for read accesses
cpu.l2.read_misses                              18542                       # number of read misses
cpu.l2.read_misses_0                             4512                       # number of read misses
cpu.l2.read_misses_1                             4533                       # number of read misses
cpu.l2.read_misses_2                             4823                       # number of read misses
cpu.l2.read_misses_3                             4674                       # number of read misses
cpu.l2.read_mshr_miss_latency                 2119292                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_0                515890                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_1                517976                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_2                551341                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_latency_3                534085                       # number of read MSHR miss cycles
cpu.l2.read_mshr_miss_rate                   0.047864                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_0                 0.045535                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_1                 0.045897                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_2                 0.052348                       # mshr miss rate for read accesses
cpu.l2.read_mshr_miss_rate_3                 0.047985                       # mshr miss rate for read accesses
cpu.l2.read_mshr_misses                         18542                       # number of read MSHR misses
cpu.l2.read_mshr_misses_0                        4512                       # number of read MSHR misses
cpu.l2.read_mshr_misses_1                        4533                       # number of read MSHR misses
cpu.l2.read_mshr_misses_2                        4823                       # number of read MSHR misses
cpu.l2.read_mshr_misses_3                        4674                       # number of read MSHR misses
cpu.l2.replacements                                 0                       # number of replacements
cpu.l2.replacements_0                               0                       # number of replacements
cpu.l2.replacements_1                               0                       # number of replacements
cpu.l2.replacements_2                               0                       # number of replacements
cpu.l2.replacements_3                               0                       # number of replacements
cpu.l2.sampled_refs                                 0                       # Sample count of references to valid blocks.
cpu.l2.soft_prefetch_mshr_full                      0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_0                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_1                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_2                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.soft_prefetch_mshr_full_3                    0                       # number of mshr full events for SW prefetching instrutions
cpu.l2.tagsinuse                         13805.782916                       # Cycle average of tags in use
cpu.l2.total_refs                                   0                       # Total number of references to valid blocks.
cpu.l2.warmup_cycle                                 0                       # Cycle when the warmup percentage was hit.
cpu.l2.writeback_accesses                       10382                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_0                      2596                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_1                      2562                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_2                      2595                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_accesses_3                      2629                       # number of writeback accesses(hits+misses)
cpu.l2.writeback_hits                           10136                       # number of writeback hits
cpu.l2.writeback_hits_0                          2533                       # number of writeback hits
cpu.l2.writeback_hits_1                          2502                       # number of writeback hits
cpu.l2.writeback_hits_2                          2532                       # number of writeback hits
cpu.l2.writeback_hits_3                          2569                       # number of writeback hits
cpu.l2.writeback_miss_rate                   0.023695                       # miss rate for writeback accesses
cpu.l2.writeback_miss_rate_0                 0.024268                       # miss rate for writeback accesses
cpu.l2.writeback_miss_rate_1                 0.023419                       # miss rate for writeback accesses
cpu.l2.writeback_miss_rate_2                 0.024277                       # miss rate for writeback accesses
cpu.l2.writeback_miss_rate_3                 0.022822                       # miss rate for writeback accesses
cpu.l2.writeback_misses                           246                       # number of writeback misses
cpu.l2.writeback_misses_0                          63                       # number of writeback misses
cpu.l2.writeback_misses_1                          60                       # number of writeback misses
cpu.l2.writeback_misses_2                          63                       # number of writeback misses
cpu.l2.writeback_misses_3                          60                       # number of writeback misses
cpu.l2.writeback_mshr_miss_rate              0.023695                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_miss_rate_0            0.024268                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_miss_rate_1            0.023419                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_miss_rate_2            0.024277                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_miss_rate_3            0.022822                       # mshr miss rate for writeback accesses
cpu.l2.writeback_mshr_misses                      246                       # number of writeback MSHR misses
cpu.l2.writeback_mshr_misses_0                     63                       # number of writeback MSHR misses
cpu.l2.writeback_mshr_misses_1                     60                       # number of writeback MSHR misses
cpu.l2.writeback_mshr_misses_2                     63                       # number of writeback MSHR misses
cpu.l2.writeback_mshr_misses_3                     60                       # number of writeback MSHR misses
cpu.l2.writebacks                                   0                       # number of writebacks
cpu.l2.writebacks_0                                 0                       # number of writebacks
cpu.l2.writebacks_1                                 0                       # number of writebacks
cpu.l2.writebacks_2                                 0                       # number of writebacks
cpu.l2.writebacks_3                                 0                       # number of writebacks
cpu.numCycles                                 1776507                       # number of cpu cycles simulated
cpu.toL2Bus.addr_idle_cycles                  1378731                       # number of cycles bus was idle
cpu.toL2Bus.addr_idle_fraction               0.776091                       # fraction of time addr bus was idle
cpu.toL2Bus.addr_queued                      3.113047                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_0                    3.109496                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_1                    3.109092                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_2                    3.120945                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_3                    3.113182                       # average queueing delay seen by bus request
cpu.toL2Bus.addr_queued_cycles                1238289                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_0               316186                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_1               315035                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_2               295644                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_queued_cycles_3               311424                       # total number of queued cycles for all requests
cpu.toL2Bus.addr_requests                      397774                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_0                    101684                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_1                    101327                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_2                     94729                       # number of transmissions on bus
cpu.toL2Bus.addr_requests_3                    100034                       # number of transmissions on bus
cpu.toL2Bus.bus_blocked                             0                       # number of times bus was blocked
cpu.toL2Bus.bus_blocked_cycles                      0                       # number of cycles bus was blocked
cpu.toL2Bus.bus_blocked_fraction                    0                       # fraction of time bus was blocked
cpu.toL2Bus.data_idle_cycles                  1378732                       # number of cycles bus was idle
cpu.toL2Bus.data_idle_fraction               0.776092                       # fraction of time data bus was idle
cpu.toL2Bus.data_queued                      1.016549                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_0                    1.017237                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_1                    1.016170                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_2                    1.016628                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_3                    1.016159                       # average queueing delay seen by bus request
cpu.toL2Bus.data_queued_cycles                 393801                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_0               100795                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_1               100361                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_2                93666                       # total number of queued cycles for all requests
cpu.toL2Bus.data_queued_cycles_3                98979                       # total number of queued cycles for all requests
cpu.toL2Bus.data_requests                      387390                       # number of transmissions on bus
cpu.toL2Bus.data_requests_0                     99087                       # number of transmissions on bus
cpu.toL2Bus.data_requests_1                     98764                       # number of transmissions on bus
cpu.toL2Bus.data_requests_2                     92134                       # number of transmissions on bus
cpu.toL2Bus.data_requests_3                     97405                       # number of transmissions on bus
cpu.toL2Bus.null_grants                          1957                       # number of null grants (wasted cycles)
cpu.workload0.MainMem.page_count                    4                       # total number of pages allocated
cpu.workload0.MainMem.page_mem                     32                       # total size of memory pages allocated
cpu.workload0.MainMem.ptab_accesses           1882831                       # total page table accessess
cpu.workload0.MainMem.ptab_miss_rate           0.0067                       # first level page table miss rate
cpu.workload0.MainMem.ptab_misses               12631                       # total first level page table misses
cpu.workload0.PROG:num_syscalls                   322                       # Number of system calls
cpu.workload1.MainMem.page_count                    4                       # total number of pages allocated
cpu.workload1.MainMem.page_mem                     32                       # total size of memory pages allocated
cpu.workload1.MainMem.ptab_accesses           1900423                       # total page table accessess
cpu.workload1.MainMem.ptab_miss_rate           0.0066                       # first level page table miss rate
cpu.workload1.MainMem.ptab_misses               12504                       # total first level page table misses
cpu.workload1.PROG:num_syscalls                   322                       # Number of system calls
cpu.workload2.MainMem.page_count                    4                       # total number of pages allocated
cpu.workload2.MainMem.page_mem                     32                       # total size of memory pages allocated
cpu.workload2.MainMem.ptab_accesses           2574805                       # total page table accessess
cpu.workload2.MainMem.ptab_miss_rate           0.0070                       # first level page table miss rate
cpu.workload2.MainMem.ptab_misses               18013                       # total first level page table misses
cpu.workload2.PROG:num_syscalls                   340                       # Number of system calls
cpu.workload3.MainMem.page_count                    4                       # total number of pages allocated
cpu.workload3.MainMem.page_mem                     32                       # total size of memory pages allocated
cpu.workload3.MainMem.ptab_accesses           2082641                       # total page table accessess
cpu.workload3.MainMem.ptab_miss_rate           0.0068                       # first level page table miss rate
cpu.workload3.MainMem.ptab_misses               14187                       # total first level page table misses
cpu.workload3.PROG:num_syscalls                   324                       # Number of system calls
cpuinst_class_dist.start_dist
                   All ops ready            0      0.00%            # Operand status at dispatch
                One op not ready            0      0.00%            # Operand status at dispatch
           None rdy, mult chains            0      0.00%            # Operand status at dispatch
           None rdy, one chained            0      0.00%            # Operand status at dispatch
        None rdy, all self-timed            0      0.00%            # Operand status at dispatch
cpuinst_class_dist.end_dist
host_inst_rate                                  58808                       # Simulator instruction rate (inst/s)
host_mem_usage                                  28104                       # Number of bytes of host memory used
host_seconds                                    62.95                       # Real time elapsed on the host
host_tick_rate                                  28223                       # Simulator tick rate (ticks/s)
ram.accesses                                    18788                       # total number of accesses
ram.accesses_0                                   4575                       # total number of accesses
ram.accesses_1                                   4593                       # total number of accesses
ram.accesses_2                                   4886                       # total number of accesses
ram.accesses_3                                   4734                       # total number of accesses
ram.bytes_requested                                 0                       # total number of bytes requested
ram.bytes_requested_0                               0                       # total number of bytes requested
ram.bytes_requested_1                               0                       # total number of bytes requested
ram.bytes_requested_2                               0                       # total number of bytes requested
ram.bytes_requested_3                               0                       # total number of bytes requested
ram.bytes_sent                                      0                       # total number of bytes sent
ram.bytes_sent_0                                    0                       # total number of bytes sent
ram.bytes_sent_1                                    0                       # total number of bytes sent
ram.bytes_sent_2                                    0                       # total number of bytes sent
ram.bytes_sent_3                                    0                       # total number of bytes sent
ram.compressed_responses                            0                       # total number of accesses that are compressed
ram.compressed_responses_0                          0                       # total number of accesses that are compressed
ram.compressed_responses_1                          0                       # total number of accesses that are compressed
ram.compressed_responses_2                          0                       # total number of accesses that are compressed
ram.compressed_responses_3                          0                       # total number of accesses that are compressed
sim_freq                                    200000000                       # Frequency of simulated ticks
sim_insts                                     3701726                       # Number of instructions simulated
sim_seconds                                  0.008883                       # Number of seconds simulated
sim_ticks                                     1776506                       # Number of ticks simulated
toMemBus.addr_idle_cycles                     1757472                       # number of cycles bus was idle
toMemBus.addr_idle_fraction                  0.989286                       # fraction of time addr bus was idle
toMemBus.addr_queued                        10.716787                       # average queueing delay seen by bus request
toMemBus.addr_queued_0                      10.820546                       # average queueing delay seen by bus request
toMemBus.addr_queued_1                      10.952754                       # average queueing delay seen by bus request
toMemBus.addr_queued_2                      10.529063                       # average queueing delay seen by bus request
toMemBus.addr_queued_3                      10.581327                       # average queueing delay seen by bus request
toMemBus.addr_queued_cycles                    201347                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_0                   49504                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_1                   50306                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_2                   51445                       # total number of queued cycles for all requests
toMemBus.addr_queued_cycles_3                   50092                       # total number of queued cycles for all requests
toMemBus.addr_requests                          18788                       # number of transmissions on bus
toMemBus.addr_requests_0                         4575                       # number of transmissions on bus
toMemBus.addr_requests_1                         4593                       # number of transmissions on bus
toMemBus.addr_requests_2                         4886                       # number of transmissions on bus
toMemBus.addr_requests_3                         4734                       # number of transmissions on bus
toMemBus.bus_blocked                                0                       # number of times bus was blocked
toMemBus.bus_blocked_cycles                         0                       # number of cycles bus was blocked
toMemBus.bus_blocked_fraction                       0                       # fraction of time bus was blocked
toMemBus.data_idle_cycles                     1701112                       # number of cycles bus was idle
toMemBus.data_idle_fraction                  0.957561                       # fraction of time data bus was idle
toMemBus.data_queued                         2.592331                       # average queueing delay seen by bus request
toMemBus.data_queued_0                       2.531250                       # average queueing delay seen by bus request
toMemBus.data_queued_1                       2.322744                       # average queueing delay seen by bus request
toMemBus.data_queued_2                       2.799917                       # average queueing delay seen by bus request
toMemBus.data_queued_3                       2.698545                       # average queueing delay seen by bus request
toMemBus.data_queued_cycles                     48067                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_0                   11421                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_1                   10529                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_2                   13504                       # total number of queued cycles for all requests
toMemBus.data_queued_cycles_3                   12613                       # total number of queued cycles for all requests
toMemBus.data_requests                          18542                       # number of transmissions on bus
toMemBus.data_requests_0                         4512                       # number of transmissions on bus
toMemBus.data_requests_1                         4533                       # number of transmissions on bus
toMemBus.data_requests_2                         4823                       # number of transmissions on bus
toMemBus.data_requests_3                         4674                       # number of transmissions on bus
toMemBus.null_grants                                0                       # number of null grants (wasted cycles)

---------- End Simulation Statistics   ----------
