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Course Description
This course examines fundamental issues and design trade-offs in
multiprocessor architecture. It covers both quantitative and qualitative
analysis of parallel computer systems and serves as a entry point to further
research in high performance computing.
Course material covers both traditional topics in parallel
architectures such as parallel programming models, symmetric
multiprocessors, coherency policies, distributed shared memories, and
scalable multiprocessors, as well as important emerging topics like
chip multiprocessors and on-chip interconnection networks. The project
component is open-ended and students are encouraged to draw on their
own research interests and prior background for inspiration.
News
- Exam 1 will be in class Wednesday, Feb 7
Course Information
For detailed course information, including grading policies, and
course structure, please see the syllabus.
Required Text
David E. Culler and Jaswinder Pal Singh with Anoop Gupta, Parallel
Computer Architecture: A Hardware/Software Approach, Morgan Kaufmann
Publishers, 1999
Instructor
Assignments
Projects
Tentative Schedule
The schedule below is a best guess given the likely sequence of material
covered in this course. Slight deviations are inevitable.
| Date | Topic |
| 1/3 | Introduction to Parallel Architectures |
| 1/5 | Communication Architectures |
| 1/8 | Programming Models |
| 1/10 | Memory Consistency |
| 1/15 | Basic Bus Based Coherence |
| 1/17 | More Bus Based Coherence |
| 1/22 | Evaluating Coherence Strategies |
| 1/24 | Implementing Snoopy Caches |
| 1/29 | Discussion: CMP Cache Strategies |
| 1/31 | Exam 1 |
| 2/5 | Scaleable Systems |
| 2/7 | Directory Based Coherence |
| 2/12 | Basics of Interconnection Networks |
| 2/14 | Advanced Interconnection Networks |
| 2/19 | Transactional Memory |
| 2/21 | Paper Discussion |
| 2/26 | Paper Discussion |
| 2/28 | Paper Discussion |
| 3/5 | Exam 2 |
| 3/7 | Project Presentations |
Paper Discussion Topics
- Coherence Ordering for Ring-based Chip Multiprocessors: Michael
R. Marty, University of Wisconsin - Madison Mark D. Hill, University
of Wisconsin - Madison [pdf]
- In-Network Cache Coherence: Noel Eisley - Princeton University,
Li-Shiuan Peh - Princeton University, Li Shang - Queens University
[pdf]
- An Analysis of Efficient Multi-Core Global Power Management Policies:
Maximizing Performance for a Given Power Budget: Canturk Isci -
Princeton University, Alper Buyuktosunoglu - IBM, Pradip Bose - IBM,
Margaret Martonosi - Princeton University, Chen-Yong Cher - IBM [pdf]
- Utility-Based Cache Partitioning: A Low-Overhead, High-Performance,
Runtime Mechanism to Partition Shared Caches:
Moinuddin K. Qureshi - University of Texas - Austin,
Yale N. Patt - University of Texas - Austin [pdf]
- Molecular Caches: A Caching Structure for Dynamic Creation of
Application-Specific Heterogeneous Cache Regions:
Keshavan Varadarajan - Indian Institute of Science, Bangalore,
S. K. Nandy - Indian Institute of Science, Bangalore,
Vishal Sharda - Indian Institute of Science, Bangalore,
Amrutur Bharadwaj - Indian Institute of Science, Bangalore,
Ravi Iyer - Intel Corporation,
Srihari Makineni - Intel Corporation,
Donald Newell - Intel Corporation [pdf]
- ASR: Adaptive Selective Replication for CMP Caches:
Bradford M. Beckmann - University of Wisconsin - Madison,
Michael R. Marty - University of Wisconsin- Madison,
David A. Wood - University of Wisconsin- Madison [pdf]
- Managing Distributed, Shared L2 Caches through OS-Level Page
Allocation:
Sangyeun Cho - University of Pittsburgh,
Lei Jin - University of Pittsburgh [pdf]
- Transactional Memory (Read these for in class discussion on
2/28):
- Transactional Memory: Architectural Support for Lock-Free Data
Structures: Maurice Herlihy and J. Eliot B. Moss
[pdf]
- Lowering the Overhead of Nonblocking Software Transactional Memory:
Virendra J. Marathe, Michael F. Spear, Christopher Heriot, Athul
Acharya, David Eisenstat, William N. Scherer III, and Michael
L. Scott [pdf]
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