Book Chapters

·          Strategically Programmable Systems

E. Bozorgzadeh, R. Kastner, S. Ogrenci Memik, M. Sarrafzadeh

The Computer Engineering Handbook, CRC Press, December 2001

 

·          Optimization for Reconfigurable Systems Using Hierarchical Abstraction

E. Bozorgzadeh, A. Kaplan, R. Kastner, S. Ogrenci Memik, M. Sarrafzadeh
J. Cong and J. R. Shinnerl (editors). Multilevel Optimization and VLSICAD. Kluwer Academic Publishers, Boston, 2002.

Journal 

 

·          Song Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik, “An Approach for Adaptive DRAM Temperature and Power Management”, under review, IEEE Transactions  on Very Large Scale Integration Systems (TVLSI)

·          Jieyi Long, Ja-Chun Ku, Seda Ogrenci Memik, Yehea Ismail, “SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation”, under review, IEEE Transactions  on Very Large Scale Integration Systems (TVLSI)

·          Marco Santambrogio, Vincenzo Rana, Seda Ogrenci Memik, Donatella Sciuto, Umut Acar, “Combining Reconfigurable HW techniques and SW Adaptive Computation for a Novel SoC Design Methodology”, under review, ACM Transactions on Reconfigurable Technology and Systems (TRETS)

·          Min Ni, Seda Ogrenci Memik, “A Fast Heuristic Algorithm for Multi-Domain Clock Skew Scheduling”, under review, IEEE Transactions  on Very Large Scale Integration Systems (TVLSI)

·          Jieyi Long, Hai Zhou, Seda Ogrenci Memik, “EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm”, accepted by IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), to appear

·          Seda Ogrenci Memik, Nikolaos Bellas, Somsubhra Mondal, “Pre-synthesis Area Estimation of Reconfigurable Streaming Accelerators”, accepted by IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), to appear

·          A High-Level Clustering Algorithm Targeting Dual Vdd FPGAs

R. Mukherjee, S. Liu, S. Ogrenci Memik, S. Mondal

accepted by ACM Transactions on Design Automation of Electronic Systems (TODAES), to appear

·          Thermal Monitoring Mechanisms for Chip Multiprocessors

J. Long, S. Ogrenci Memik, G. Memik, R. Mukherjee

accepted by ACM Transactions on Architecture and Code Optimization (TACO), to appear

·          Optimizing Thermal Sensor Allocation for Microprocessors

S. Ogrenci Memik, R. Mukherjee, M. Ni, J. Long

IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 3, pp.    

516—527, March 2008.

·          An Integrated Approach to Thermal Management in High-Level Synthesis

R. Mukherjee, S. Ogrenci Memik

IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 14, No. 1, pp. 1165—1174, November

2006.

·          Early Quality Assessment for Low Power Behavioral Synthesis

E. Kursun, R. Mukherjee, S. Ogrenci Memik
Journal of Low Power Electronics (JOLPE), Vol. 1, No. 3, pp.  273—285, December 2005.   

·          On Effective Slack Management in Post-Scheduling Phase

Srivastava, S. Ogrenci Memik, B.K. Choi, M. Sarrafzadeh
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 24, No. 4, April 2005.

·          A Scheduling Algorithm for Optimization and Planning in High-level Synthesis

S. Ogrenci Memik, R. Kastner, E. Bozorgzadeh, M. Sarrafzadeh
ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 10, No. 1, January 2005.

·          Routability-driven Packing: Metrics and Algorithms for Cluster-based FPGAs

E. Bozorgzadeh, S. Ogrenci Memik, X. Yang, M. Sarrafzadeh
Journal of Circuits, Systems, and Computers (JCSC), Vol. 13, No. 1, February 2004.

·          FPGA Implementation and Analysis of an Iterative Image Restoration Algorithm

S. Ogrenci Memik, A. K. Katsaggelos, M. Sarrafzadeh
IEEE Transactions on Computers, Vol. 52 No.3, March 2003.

·          Instruction Generation for Hybrid Reconfigurable Systems

R. Kastner, A. Kaplan, S. Ogrenci Memik, E. Bozorgzadeh
ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 7, No. 4, October 2002.

·          Fast Floorplanning for Effective Prediction and Construction

Ranjan, K. Bazargan, S. Ogrenci, M. Sarrafzadeh
IEEE Transactions on VLSI (TVLSI), Vol. 9, No. 2, April 2001.

 

Conference and Workshop

·          Towards an "Early Neural Circuit Simulator": An FPGA Implementation of Processing In the Rat Whisker System

B. Leung, Y. Pan, C. Schroeder, S. Ogrenci Memik, G. Memik, M. Hartmann

To appear at the International Conference on Field Programmable Logic and Its Applications (FPL), September 8-10 2008, Heidelberg, Germany

·          An Approach for Adaptive DRAM Temperature and Power Management

S. Liu, S. Ogrenci Memik, Y. Zhang, G. Memik

To appear at the ACM International Conference on Supercomputing (ICS), June 7-12, 2008, Kos, Greece

·          Automated Design of Self-Adjusting Pipelines

J. Long, S. Ogrenci Memik

To appear at the IEEE/ACM Design Automation Conference (DAC), June 8-13, 2008, Anaheim, CA

·          A Power and Temperature Aware DRAM Architecture

S. Liu, S. Ogrenci Memik, Y. Zhang, G. Memik

To appear at the IEEE/ACM Design Automation Conference (DAC), June 8-13, 2008, Anaheim, CA

·          Leakage Power-Aware Clock Skew Scheduling: Converting Stolen Time into Leakage Power Reduction

M. Ni, S. Ogrenci Memik

To appear at the IEEE/ACM Design Automation Conference (DAC), June 8-13, 2008, Anaheim, CA

·          An O(nlogn) Edge-Based Algorithm for Obstacle-Avoiding Rectilinear Steiner Tree Construction

J. Long, H. Zhou, S. Ogrenci Memik

ACM International Symposium on Physical Design (ISPD), April 13-16, 2008, Portland, OR

·          Managing Reconfigurable Resources in Heterogeneous Cores using Portable Pre-Synthesized Templates

M. Giani, M. Santambrogio, S. Ogrenci Memik

International Symposium on System-on-Chip, November 19-21, 2007, Tampere, Finland

·          Early Planning for Clock Skew Scheduling during Register Binding

M. Ni, S. Ogrenci Memik

IEEE/ACM International Conference on Computer Aided Design (ICCAD), November 5-8, 2007, San Jose, CA

·          A Self-Adjusting Clock Tree Architecture to Cope with Temperature Variations Best Paper Award Finalist

J. Long, J. Ku, S. Ogrenci Memik, Y. Ismail

IEEE/ACM International Conference on Computer Aided Design (ICCAD), November 5-8, 2007, San Jose, CA

·          A Novel SoC Design Methodology Combining Adaptive Software and Reconfigurable Hardware

M. Santambrogio, V. Rana, S. Ogrenci Memik, U. Acar, D. Scuito

IEEE/ACM International Conference on Computer Aided Design (ICCAD), November 5-8, 2007, San Jose, CA

·          Self-Heating-Aware Optimal Wire Sizing Under Elmore Delay Model

M. Ni, S. Ogrenci Memik

Design, Automation and Test in Europe (DATE), April 16-20, 2007, Nice, France

·          Combining Hardware Reconfiguration and Adaptive Computation for a Novel SoC Design Methodology

V. Rana, M. Santambrogio, D. Scuito, S. Ogrenci Memik

 IEEE International Conference on Field Programmable Technology (FPT), December 13-15, 2006, Bangkok, Thailand

·          Thermal Sensor Allocation and Placement for Reconfigurable Systems

R. Mukherjee, S. Mondal, S. Ogrenci Memik

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November5-9, 2006, San Jose, CA

·          Physical Aware Frequency Selection for Dynamic Thermal Management in Multi-Core Systems

R. Mukherjee, S. Ogrenci Memik

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November5-9, 2006, San Jose, CA

·          Thermal-Induced Leakage Power Optimization by Redundant Resource Allocation

M. Ni, S. Ogrenci Memik

IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November5-9, 2006, San Jose, CA

·          Adaptive Metrics for System-Level Functional Partitioning

M. Santambrogio, G. Agosta, S. Ogrenci Memik

Forum on Specification and Design Languages (FDL), September 19-22, 2006, Darmstadt, Germany

·          Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators

S. Mondal, S. Ogrenci Memik, N. Bellas

International Conference on Field Programmable Logic and Applications (FPL), August 28-30, 2006, Madrid, Spain

·          Systematic Temperature Sensor Allocation and Placement for Microprocessors

R. Mukherjee, S. Ogrenci Memik

IEEE/ACM Design Automation Conference (DAC), July 24-28, 2006, San Francisco, CA

·          A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead

R. Mukherjee, S. Mondal, S. Ogrenci Memik

International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), June 26-29, 2006, Las Vegas, NV

·          Fine-Grain Thermal Profiling and Sensor Insertion for FPGAs

S. Mondal, R. Mukherjee, S. Ogrenci Memik

IEEE International Symposium on Circuits and Systems (ISCAS), May 21-24 2006, Kos, Greece

·          Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs (2-page extended abstract in the proceedings)

S. Mondal, S. Ogrenci Memik, N. Bellas

IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), April24-26, 2006, Napa, CA

·          Real-Time Feature Extraction for High Speed Networks
D. Nguyen, G. Memik, S. Ogrenci Memik, and A. Choudhary

International Conference on Field Programmable Logic and Applications (FPL), August 2005, Tampere, Finland

·          Peak Temperature Control and Leakage Reduction during Binding in High-Level Synthesis

R. Mukherjee, S. Ogrenci Memik, G. Memik

IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 8-10, 2005, San Diego, CA

·          Temperature-Aware Resource Allocation and Binding in High-Level Synthesis, Best Paper Award Nominee

R. Mukherjee, S. Ogrenci Memik, G. Memik

IEEE/ACM Design Automation Conference (DAC), June 13-17, 2005, Anaheim, CA

·          A Low Power FPGA Routing Architecture

S. Mondal, S. Ogrenci Memik

IEEE International Symposium on Circuits and Systems (ISCAS), May 23-26 2005, Kobe, Japan

·          Fine-Grain Leakage Optimization in SRAM based FPGAs

S. Mondal, S. Ogrenci Memik

Great Lakes Symposium on VLSI (GLSVLSI), April 17-19, 2005, Chicago, IL

·          Quick Reconfiguration in Clustered Micro-Sequencer

R. Jafari, S. Ogrenci Memik, M. Sarrafzadeh

IEEE International Parallel and Distributed Processing Symposium (IPDPS), Reconfigurable Architectures Workshop (RAW), April 4-5 2005, Denver, CO

·          Hierarchical LUT Structures for Leakage Power Reduction (poster presentation)

S. Mondal, S. Ogrenci Memik, D. Das

ACM International Symposium on Field Programmable Gate Arrays (FPGA), February 20-22 2005, Monterey, CA

·          Evaluation of Dual Vdd Fabrics for Low Power FPGAs

R. Mukherjee, S. Ogrenci Memik

IEEE/ACM Asia-South Pacific Design Automation Conference (ASP-DAC), January 18-21 2005, Shanghai, China

·          Resource Sharing in Pipelined CDFG Synthesis

S. Mondal, S. Ogrenci Memik

IEEE/ACM Asia-South Pacific Design Automation Conference (ASP-DAC), January 18-21 2005, Shanghai, China

·           Power-Driven Design Partitioning

R. Mukherjee, S. Ogrenci Memik

International Conference on Field Programmable Logic and Its Applications (FPL), August 30-September 1 2004, Antwerp, Belgium

·          Power Management for FPGAs: Power-Driven Design Partitioning (2-page extended abstract in the proceedings)

R. Mukherjee, S. Ogrenci Memik

IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), April 2004, Napa, CA.

·          Achieving Design Closure through Delay Relaxation Parameter

A. Srivastava, S. Ogrenci Memik, B. K. Choi, M. Sarrafzadeh
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2003, San Jose, CA.

·          Design Planning in Hardware Compilers

S. Ogrenci Memik
 IASTED Parallel and Distributed Computing and Systems (PDCS), November 2003, Marina Del Rey.

·          Global Resource Sharing for Synthesis of Control Data Flow Graphs on FPGAs

S. Ogrenci Memik, G. Memik, R. Jafari, E. Kursun
IEEE/ACM Design Automation Conference (DAC), June 2003, Anaheim, CA.

·          Accelerated SAT-based Scheduling of Control/Data Flow Graphs

S. Ogrenci Memik, F. Fallah
IEEE International Conference on Computer Design (ICCD), September 2002, Freiburg, Germany.

·          Early Evaluation Techniques for Low Power Binding

E. Kursun, A. Srivastava, S. Ogrenci Memik, M. Sarrafzadeh
IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 2002, Monterey, CA.

·          Pattern Selection: Customized Block Allocation for Domain-Specific Programmable Systems (poster presentation)

E. Bozorgzadeh, S. Ogrenci Memik, R. Kastner, M. Sarrafzadeh

International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), June 2002, Las Vegas, NV

·          Accelerated Boolean Satisfiability-Based Scheduling for High-Level Synthesis

S. Ogrenci Memik, F. Fallah,
IEEE/ACM International Workshop on Logic & Synthesis (IWLS), June 2002, New Orleans, LA.

·          Algorithmic Aspects of Uncertainty Driven Scheduling

S. Ogrenci Memik, A. Srivastava, E. Kursun, M. Sarrafzadeh
 IEEE International Symposium on Circuits and Systems (ISCAS), May 2002, Scottsdale, AZ.

·          Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic

G. Memik, S. Ogrenci Memik, W. Mangione-Smith
IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), April 2002, Napa, CA.

·          Pattern Selection in Programmable Systems (poster presentation)

E. Bozorgzadeh, R. Kastner, S. Ogrenci Memik and M. Sarrafzadeh
ACM International Symposium on Field Programmable Gate Arrays (FPGA), February 2002, Monterey, CA

·          A Super-Scheduler for Embedded Reconfigurable Systems

S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, M. Sarrafzadeh
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2001, San Jose, CA.

·          Instruction Generation for Hybrid Reconfigurable Systems

R. Kastner, S. Ogrenci Memik, E. Bozorgzadeh, M. Sarrafzadeh
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2001, San Jose, CA.

·          Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures, Best Paper Award Nomination

K. Bazargan, S. Ogrenci, M. Sarrafzadeh

IEEE/ACM Design Automation Conference (DAC), June 2001, Las Vegas, NV.

·          SPS: A Strategically Programmable System
S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, M. Sarrafzadeh

Reconfigurable Architectures Workshop (RAW), San Francisco, April 2001, CA.

·          RPack: Routability-Driven Packing for Cluster-Based FPGAs

E. Bozorgzadeh, S. Ogrenci Memik, M. Sarrafzadeh
IEEE/ACM Asia-South Pacific Design Automation Conference (ASP-DAC), January 2001, Yokohama, Japan.

·          Image Analysis and Partitioning for FPGA Mapping

S. Ogrenci, K. Bazargan, M. Sarrafzadeh
IEEE Workshop on Signal Processing Systems (SiPS), October 2000, Lafayette, LA.

·          A C to Hardware/Software Compiler
K. Bazargan, R. Kastner, S. Ogrenci and M. Sarrafzadeh

IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), April 2000, Napa Valley, CA.

·          FPGA Implementation and Analysis of Image Restoration  (poster presentation)
S. Ogrenci, A. K. Katsaggelos, M. Sarrafzadeh

ACM International Symposium on Field Programmable Gate Arrays (FPGA), February 2000, Monterey, CA

Technical Reports 

Realizing Low Power FPGAs: A Design Partitioning Algorithm for Voltage Scaling and A Comparative Evaluation of Voltage Scaling Techniques for FPGAs, Electrical and Computer Engineering Department, Northwestern University, Technical report no. TR-CMPE-05-0001

 

Part of this material is based upon work supported by the National Science Foundation under Grant No. CNS-0546305, Grant No. CCF-0541337, Grant No. IIS-0536994, Grant No. IIS-0613568, by the Semiconductor Research Corporation (SRC) Grant No. G00639, and a Research Initiation Grant by the Alumnae of Northwestern.

 

Any opinions, findings and conclusions or recomendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF), SRC, or Alumnae of Northwestern.

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