Refereed Journal Publications: Microarchitectures for Managing Chip Revenues under Process Variations. A. Das, S. Ozdemir, G. Memik, J. Zambreno, A. Choudhary. IEEE CAL, Vol 6, June 2007 Thermal Management of On-Chip Caches Through Power Density Minimization. J. C. Ku, S. Ozdemir, G. Memik, Y. Ismail. IEEE TVLSI, Vol 15-5, May 2007 Refereed Conference Publications: Selective Wordline Voltage Boosting for Caches to Manage Yield under Process Variations Y. Pan, J. Kong, S. Ozdemir, G. Memik, S. W. Chung To appear in 46th DAC, San Francisco / CA, July 2009 Evaluating the Effects of Cache Redundancy on Profit A. Das, B. Ozisikyilmaz, S. Ozdemir, G. Memik, A. Choudhary MICRO-41, Lake Como, Italy, Dec. 2008 Variable Latency Caches for Nanoscale Processor                 Best Student Paper Award S. Ozdemir, A. Mallik, J. C. Ku, G. Memik, Y. Ismail. SC'07, Reno, NV, Nov. 2007 Evaluating Voltage Islands in CMPs under Process Variations A. Das, S. Ozdemir, G. Memik, A. Choudhary. ICCD'07, Lake Tahoe, NV, Oct. 2007 Mitigating the Effects of Process Variations: Architectural Approaches for Improving Batch Performance A. Das, S. Ozdemir, G. Memik, J. Zambreno, A. Choudhary. ASGI'07 San Diego, CA, June 2007. Yield-Aware Cache Architectures S. Ozdemir, D. Sinha, G. Memik, J. Adams, H. Zhou. MICRO-39, Orlando, FL, Dec. 2006 Power Density Minimization for Highly-Associative Caches in Embedded Processors J. C. Ku, S. Ozdemir, G. Memik, Y. Ismail. GLSVLSI, Philadelphia, PA, Apr. 2006 Thermal Management of On-Chip Caches Through Power Density Minimization J. C. Ku, S. Ozdemir, G. Memik, Y. Ismail MICRO-38, Barcelona, Spain, Nov. 2005 A Type-II 4th Order Fractional-N Frequency Synthesizer Design for Bluetooth Applications S. Yaldiz, S. Ozdemir, A. Ergintav, I. Tekin, A. Bozkurt, Y. Gurbuz Mediterranean Microwave Symposium (MMS'2005), Athens, Greece, Sep. 2005